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Diffstat (limited to 'src/shader_recompiler/ir_opt/ssa_rewrite_pass.cpp')
-rw-r--r--src/shader_recompiler/ir_opt/ssa_rewrite_pass.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/shader_recompiler/ir_opt/ssa_rewrite_pass.cpp b/src/shader_recompiler/ir_opt/ssa_rewrite_pass.cpp
index ca36253d1..346fcc377 100644
--- a/src/shader_recompiler/ir_opt/ssa_rewrite_pass.cpp
+++ b/src/shader_recompiler/ir_opt/ssa_rewrite_pass.cpp
@@ -116,7 +116,7 @@ IR::Opcode UndefOpcode(IndirectBranchVariable) noexcept {
116} 116}
117 117
118[[nodiscard]] bool IsPhi(const IR::Inst& inst) noexcept { 118[[nodiscard]] bool IsPhi(const IR::Inst& inst) noexcept {
119 return inst.Opcode() == IR::Opcode::Phi; 119 return inst.GetOpcode() == IR::Opcode::Phi;
120} 120}
121 121
122enum class Status { 122enum class Status {
@@ -278,7 +278,7 @@ private:
278}; 278};
279 279
280void VisitInst(Pass& pass, IR::Block* block, IR::Inst& inst) { 280void VisitInst(Pass& pass, IR::Block* block, IR::Inst& inst) {
281 switch (inst.Opcode()) { 281 switch (inst.GetOpcode()) {
282 case IR::Opcode::SetRegister: 282 case IR::Opcode::SetRegister:
283 if (const IR::Reg reg{inst.Arg(0).Reg()}; reg != IR::Reg::RZ) { 283 if (const IR::Reg reg{inst.Arg(0).Reg()}; reg != IR::Reg::RZ) {
284 pass.WriteVariable(reg, block, inst.Arg(1)); 284 pass.WriteVariable(reg, block, inst.Arg(1));