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| author | 2016-12-18 17:25:03 -0800 | |
|---|---|---|
| committer | 2017-01-29 21:31:37 -0800 | |
| commit | 335df895b9f9e9760ed5cd0d6dfaea8befb94dac (patch) | |
| tree | 6cd8e76d529d5b4af5f87ef63f617941ced77f3e /src/video_core/pica.h | |
| parent | VideoCore: Use correct register for immediate mode attribute count (diff) | |
| download | yuzu-335df895b9f9e9760ed5cd0d6dfaea8befb94dac.tar.gz yuzu-335df895b9f9e9760ed5cd0d6dfaea8befb94dac.tar.xz yuzu-335df895b9f9e9760ed5cd0d6dfaea8befb94dac.zip | |
VideoCore: Consistently use shader configuration to load attributes
Diffstat (limited to 'src/video_core/pica.h')
| -rw-r--r-- | src/video_core/pica.h | 39 |
1 files changed, 9 insertions, 30 deletions
diff --git a/src/video_core/pica.h b/src/video_core/pica.h index c772896e0..ac81a3d0f 100644 --- a/src/video_core/pica.h +++ b/src/video_core/pica.h | |||
| @@ -1225,36 +1225,15 @@ struct Regs { | |||
| 1225 | // Offset to shader program entry point (in words) | 1225 | // Offset to shader program entry point (in words) |
| 1226 | BitField<0, 16, u32> main_offset; | 1226 | BitField<0, 16, u32> main_offset; |
| 1227 | 1227 | ||
| 1228 | union { | 1228 | /// Maps input attributes to registers. 4-bits per attribute, specifying a register index |
| 1229 | BitField<0, 4, u64> attribute0_register; | 1229 | u32 input_attribute_to_register_map_low; |
| 1230 | BitField<4, 4, u64> attribute1_register; | 1230 | u32 input_attribute_to_register_map_high; |
| 1231 | BitField<8, 4, u64> attribute2_register; | 1231 | |
| 1232 | BitField<12, 4, u64> attribute3_register; | 1232 | unsigned int GetRegisterForAttribute(unsigned int attribute_index) const { |
| 1233 | BitField<16, 4, u64> attribute4_register; | 1233 | u64 map = ((u64)input_attribute_to_register_map_high << 32) | |
| 1234 | BitField<20, 4, u64> attribute5_register; | 1234 | (u64)input_attribute_to_register_map_low; |
| 1235 | BitField<24, 4, u64> attribute6_register; | 1235 | return (map >> (attribute_index * 4)) & 0b1111; |
| 1236 | BitField<28, 4, u64> attribute7_register; | 1236 | } |
| 1237 | BitField<32, 4, u64> attribute8_register; | ||
| 1238 | BitField<36, 4, u64> attribute9_register; | ||
| 1239 | BitField<40, 4, u64> attribute10_register; | ||
| 1240 | BitField<44, 4, u64> attribute11_register; | ||
| 1241 | BitField<48, 4, u64> attribute12_register; | ||
| 1242 | BitField<52, 4, u64> attribute13_register; | ||
| 1243 | BitField<56, 4, u64> attribute14_register; | ||
| 1244 | BitField<60, 4, u64> attribute15_register; | ||
| 1245 | |||
| 1246 | int GetRegisterForAttribute(int attribute_index) const { | ||
| 1247 | u64 fields[] = { | ||
| 1248 | attribute0_register, attribute1_register, attribute2_register, | ||
| 1249 | attribute3_register, attribute4_register, attribute5_register, | ||
| 1250 | attribute6_register, attribute7_register, attribute8_register, | ||
| 1251 | attribute9_register, attribute10_register, attribute11_register, | ||
| 1252 | attribute12_register, attribute13_register, attribute14_register, | ||
| 1253 | attribute15_register, | ||
| 1254 | }; | ||
| 1255 | return (int)fields[attribute_index]; | ||
| 1256 | } | ||
| 1257 | } input_register_map; | ||
| 1258 | 1237 | ||
| 1259 | BitField<0, 16, u32> output_mask; | 1238 | BitField<0, 16, u32> output_mask; |
| 1260 | 1239 | ||