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| author | 2017-01-27 21:47:34 -0800 | |
|---|---|---|
| committer | 2017-02-04 13:59:11 -0800 | |
| commit | 23713d5dee8015a73ecab1bf944ebcab908e347c (patch) | |
| tree | 160bdc8411a899f690e51d055ad1213e19abba5c /src/video_core/pica.h | |
| parent | VideoCore: Split texturing regs from Regs struct (diff) | |
| download | yuzu-23713d5dee8015a73ecab1bf944ebcab908e347c.tar.gz yuzu-23713d5dee8015a73ecab1bf944ebcab908e347c.tar.xz yuzu-23713d5dee8015a73ecab1bf944ebcab908e347c.zip | |
VideoCore: Split framebuffer regs from Regs struct
Diffstat (limited to 'src/video_core/pica.h')
| -rw-r--r-- | src/video_core/pica.h | 270 |
1 files changed, 6 insertions, 264 deletions
diff --git a/src/video_core/pica.h b/src/video_core/pica.h index 71194198a..50a549c42 100644 --- a/src/video_core/pica.h +++ b/src/video_core/pica.h | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | #include "common/common_types.h" | 18 | #include "common/common_types.h" |
| 19 | #include "common/logging/log.h" | 19 | #include "common/logging/log.h" |
| 20 | #include "common/vector_math.h" | 20 | #include "common/vector_math.h" |
| 21 | #include "video_core/regs_framebuffer.h" | ||
| 21 | #include "video_core/regs_rasterizer.h" | 22 | #include "video_core/regs_rasterizer.h" |
| 22 | #include "video_core/regs_texturing.h" | 23 | #include "video_core/regs_texturing.h" |
| 23 | 24 | ||
| @@ -51,268 +52,7 @@ struct Regs { | |||
| 51 | INSERT_PADDING_WORDS(0x2f); | 52 | INSERT_PADDING_WORDS(0x2f); |
| 52 | RasterizerRegs rasterizer; | 53 | RasterizerRegs rasterizer; |
| 53 | TexturingRegs texturing; | 54 | TexturingRegs texturing; |
| 54 | 55 | FramebufferRegs framebuffer; | |
| 55 | enum class LogicOp : u32 { | ||
| 56 | Clear = 0, | ||
| 57 | And = 1, | ||
| 58 | AndReverse = 2, | ||
| 59 | Copy = 3, | ||
| 60 | Set = 4, | ||
| 61 | CopyInverted = 5, | ||
| 62 | NoOp = 6, | ||
| 63 | Invert = 7, | ||
| 64 | Nand = 8, | ||
| 65 | Or = 9, | ||
| 66 | Nor = 10, | ||
| 67 | Xor = 11, | ||
| 68 | Equiv = 12, | ||
| 69 | AndInverted = 13, | ||
| 70 | OrReverse = 14, | ||
| 71 | OrInverted = 15, | ||
| 72 | }; | ||
| 73 | |||
| 74 | enum class BlendEquation : u32 { | ||
| 75 | Add = 0, | ||
| 76 | Subtract = 1, | ||
| 77 | ReverseSubtract = 2, | ||
| 78 | Min = 3, | ||
| 79 | Max = 4, | ||
| 80 | }; | ||
| 81 | |||
| 82 | enum class BlendFactor : u32 { | ||
| 83 | Zero = 0, | ||
| 84 | One = 1, | ||
| 85 | SourceColor = 2, | ||
| 86 | OneMinusSourceColor = 3, | ||
| 87 | DestColor = 4, | ||
| 88 | OneMinusDestColor = 5, | ||
| 89 | SourceAlpha = 6, | ||
| 90 | OneMinusSourceAlpha = 7, | ||
| 91 | DestAlpha = 8, | ||
| 92 | OneMinusDestAlpha = 9, | ||
| 93 | ConstantColor = 10, | ||
| 94 | OneMinusConstantColor = 11, | ||
| 95 | ConstantAlpha = 12, | ||
| 96 | OneMinusConstantAlpha = 13, | ||
| 97 | SourceAlphaSaturate = 14, | ||
| 98 | }; | ||
| 99 | |||
| 100 | enum class CompareFunc : u32 { | ||
| 101 | Never = 0, | ||
| 102 | Always = 1, | ||
| 103 | Equal = 2, | ||
| 104 | NotEqual = 3, | ||
| 105 | LessThan = 4, | ||
| 106 | LessThanOrEqual = 5, | ||
| 107 | GreaterThan = 6, | ||
| 108 | GreaterThanOrEqual = 7, | ||
| 109 | }; | ||
| 110 | |||
| 111 | enum class StencilAction : u32 { | ||
| 112 | Keep = 0, | ||
| 113 | Zero = 1, | ||
| 114 | Replace = 2, | ||
| 115 | Increment = 3, | ||
| 116 | Decrement = 4, | ||
| 117 | Invert = 5, | ||
| 118 | IncrementWrap = 6, | ||
| 119 | DecrementWrap = 7, | ||
| 120 | }; | ||
| 121 | |||
| 122 | struct { | ||
| 123 | union { | ||
| 124 | // If false, logic blending is used | ||
| 125 | BitField<8, 1, u32> alphablend_enable; | ||
| 126 | }; | ||
| 127 | |||
| 128 | union { | ||
| 129 | BitField<0, 8, BlendEquation> blend_equation_rgb; | ||
| 130 | BitField<8, 8, BlendEquation> blend_equation_a; | ||
| 131 | |||
| 132 | BitField<16, 4, BlendFactor> factor_source_rgb; | ||
| 133 | BitField<20, 4, BlendFactor> factor_dest_rgb; | ||
| 134 | |||
| 135 | BitField<24, 4, BlendFactor> factor_source_a; | ||
| 136 | BitField<28, 4, BlendFactor> factor_dest_a; | ||
| 137 | } alpha_blending; | ||
| 138 | |||
| 139 | union { | ||
| 140 | BitField<0, 4, LogicOp> logic_op; | ||
| 141 | }; | ||
| 142 | |||
| 143 | union { | ||
| 144 | u32 raw; | ||
| 145 | BitField<0, 8, u32> r; | ||
| 146 | BitField<8, 8, u32> g; | ||
| 147 | BitField<16, 8, u32> b; | ||
| 148 | BitField<24, 8, u32> a; | ||
| 149 | } blend_const; | ||
| 150 | |||
| 151 | union { | ||
| 152 | BitField<0, 1, u32> enable; | ||
| 153 | BitField<4, 3, CompareFunc> func; | ||
| 154 | BitField<8, 8, u32> ref; | ||
| 155 | } alpha_test; | ||
| 156 | |||
| 157 | struct { | ||
| 158 | union { | ||
| 159 | // Raw value of this register | ||
| 160 | u32 raw_func; | ||
| 161 | |||
| 162 | // If true, enable stencil testing | ||
| 163 | BitField<0, 1, u32> enable; | ||
| 164 | |||
| 165 | // Comparison operation for stencil testing | ||
| 166 | BitField<4, 3, CompareFunc> func; | ||
| 167 | |||
| 168 | // Mask used to control writing to the stencil buffer | ||
| 169 | BitField<8, 8, u32> write_mask; | ||
| 170 | |||
| 171 | // Value to compare against for stencil testing | ||
| 172 | BitField<16, 8, u32> reference_value; | ||
| 173 | |||
| 174 | // Mask to apply on stencil test inputs | ||
| 175 | BitField<24, 8, u32> input_mask; | ||
| 176 | }; | ||
| 177 | |||
| 178 | union { | ||
| 179 | // Raw value of this register | ||
| 180 | u32 raw_op; | ||
| 181 | |||
| 182 | // Action to perform when the stencil test fails | ||
| 183 | BitField<0, 3, StencilAction> action_stencil_fail; | ||
| 184 | |||
| 185 | // Action to perform when stencil testing passed but depth testing fails | ||
| 186 | BitField<4, 3, StencilAction> action_depth_fail; | ||
| 187 | |||
| 188 | // Action to perform when both stencil and depth testing pass | ||
| 189 | BitField<8, 3, StencilAction> action_depth_pass; | ||
| 190 | }; | ||
| 191 | } stencil_test; | ||
| 192 | |||
| 193 | union { | ||
| 194 | BitField<0, 1, u32> depth_test_enable; | ||
| 195 | BitField<4, 3, CompareFunc> depth_test_func; | ||
| 196 | BitField<8, 1, u32> red_enable; | ||
| 197 | BitField<9, 1, u32> green_enable; | ||
| 198 | BitField<10, 1, u32> blue_enable; | ||
| 199 | BitField<11, 1, u32> alpha_enable; | ||
| 200 | BitField<12, 1, u32> depth_write_enable; | ||
| 201 | }; | ||
| 202 | |||
| 203 | INSERT_PADDING_WORDS(0x8); | ||
| 204 | } output_merger; | ||
| 205 | |||
| 206 | // Components are laid out in reverse byte order, most significant bits first. | ||
| 207 | enum class ColorFormat : u32 { | ||
| 208 | RGBA8 = 0, | ||
| 209 | RGB8 = 1, | ||
| 210 | RGB5A1 = 2, | ||
| 211 | RGB565 = 3, | ||
| 212 | RGBA4 = 4, | ||
| 213 | }; | ||
| 214 | |||
| 215 | enum class DepthFormat : u32 { | ||
| 216 | D16 = 0, | ||
| 217 | D24 = 2, | ||
| 218 | D24S8 = 3, | ||
| 219 | }; | ||
| 220 | |||
| 221 | // Returns the number of bytes in the specified color format | ||
| 222 | static unsigned BytesPerColorPixel(ColorFormat format) { | ||
| 223 | switch (format) { | ||
| 224 | case ColorFormat::RGBA8: | ||
| 225 | return 4; | ||
| 226 | case ColorFormat::RGB8: | ||
| 227 | return 3; | ||
| 228 | case ColorFormat::RGB5A1: | ||
| 229 | case ColorFormat::RGB565: | ||
| 230 | case ColorFormat::RGBA4: | ||
| 231 | return 2; | ||
| 232 | default: | ||
| 233 | LOG_CRITICAL(HW_GPU, "Unknown color format %u", format); | ||
| 234 | UNIMPLEMENTED(); | ||
| 235 | } | ||
| 236 | } | ||
| 237 | |||
| 238 | struct FramebufferConfig { | ||
| 239 | INSERT_PADDING_WORDS(0x3); | ||
| 240 | |||
| 241 | union { | ||
| 242 | BitField<0, 4, u32> allow_color_write; // 0 = disable, else enable | ||
| 243 | }; | ||
| 244 | |||
| 245 | INSERT_PADDING_WORDS(0x1); | ||
| 246 | |||
| 247 | union { | ||
| 248 | BitField<0, 2, u32> allow_depth_stencil_write; // 0 = disable, else enable | ||
| 249 | }; | ||
| 250 | |||
| 251 | DepthFormat depth_format; // TODO: Should be a BitField! | ||
| 252 | BitField<16, 3, ColorFormat> color_format; | ||
| 253 | |||
| 254 | INSERT_PADDING_WORDS(0x4); | ||
| 255 | |||
| 256 | u32 depth_buffer_address; | ||
| 257 | u32 color_buffer_address; | ||
| 258 | |||
| 259 | union { | ||
| 260 | // Apparently, the framebuffer width is stored as expected, | ||
| 261 | // while the height is stored as the actual height minus one. | ||
| 262 | // Hence, don't access these fields directly but use the accessors | ||
| 263 | // GetWidth() and GetHeight() instead. | ||
| 264 | BitField<0, 11, u32> width; | ||
| 265 | BitField<12, 10, u32> height; | ||
| 266 | }; | ||
| 267 | |||
| 268 | INSERT_PADDING_WORDS(0x1); | ||
| 269 | |||
| 270 | inline u32 GetColorBufferPhysicalAddress() const { | ||
| 271 | return DecodeAddressRegister(color_buffer_address); | ||
| 272 | } | ||
| 273 | inline u32 GetDepthBufferPhysicalAddress() const { | ||
| 274 | return DecodeAddressRegister(depth_buffer_address); | ||
| 275 | } | ||
| 276 | |||
| 277 | inline u32 GetWidth() const { | ||
| 278 | return width; | ||
| 279 | } | ||
| 280 | |||
| 281 | inline u32 GetHeight() const { | ||
| 282 | return height + 1; | ||
| 283 | } | ||
| 284 | } framebuffer; | ||
| 285 | |||
| 286 | // Returns the number of bytes in the specified depth format | ||
| 287 | static u32 BytesPerDepthPixel(DepthFormat format) { | ||
| 288 | switch (format) { | ||
| 289 | case DepthFormat::D16: | ||
| 290 | return 2; | ||
| 291 | case DepthFormat::D24: | ||
| 292 | return 3; | ||
| 293 | case DepthFormat::D24S8: | ||
| 294 | return 4; | ||
| 295 | default: | ||
| 296 | LOG_CRITICAL(HW_GPU, "Unknown depth format %u", format); | ||
| 297 | UNIMPLEMENTED(); | ||
| 298 | } | ||
| 299 | } | ||
| 300 | |||
| 301 | // Returns the number of bits per depth component of the specified depth format | ||
| 302 | static u32 DepthBitsPerPixel(DepthFormat format) { | ||
| 303 | switch (format) { | ||
| 304 | case DepthFormat::D16: | ||
| 305 | return 16; | ||
| 306 | case DepthFormat::D24: | ||
| 307 | case DepthFormat::D24S8: | ||
| 308 | return 24; | ||
| 309 | default: | ||
| 310 | LOG_CRITICAL(HW_GPU, "Unknown depth format %u", format); | ||
| 311 | UNIMPLEMENTED(); | ||
| 312 | } | ||
| 313 | } | ||
| 314 | |||
| 315 | INSERT_PADDING_WORDS(0x20); | ||
| 316 | 56 | ||
| 317 | enum class LightingSampler { | 57 | enum class LightingSampler { |
| 318 | Distribution0 = 0, | 58 | Distribution0 = 0, |
| @@ -957,8 +697,10 @@ ASSERT_REG_POSITION(texturing.tev_stage4, 0xf0); | |||
| 957 | ASSERT_REG_POSITION(texturing.tev_stage5, 0xf8); | 697 | ASSERT_REG_POSITION(texturing.tev_stage5, 0xf8); |
| 958 | ASSERT_REG_POSITION(texturing.tev_combiner_buffer_color, 0xfd); | 698 | ASSERT_REG_POSITION(texturing.tev_combiner_buffer_color, 0xfd); |
| 959 | 699 | ||
| 960 | ASSERT_REG_POSITION(output_merger, 0x100); | 700 | ASSERT_REG_POSITION(framebuffer, 0x100); |
| 961 | ASSERT_REG_POSITION(framebuffer, 0x110); | 701 | ASSERT_REG_POSITION(framebuffer.output_merger, 0x100); |
| 702 | ASSERT_REG_POSITION(framebuffer.framebuffer, 0x110); | ||
| 703 | |||
| 962 | ASSERT_REG_POSITION(lighting, 0x140); | 704 | ASSERT_REG_POSITION(lighting, 0x140); |
| 963 | ASSERT_REG_POSITION(vertex_attributes, 0x200); | 705 | ASSERT_REG_POSITION(vertex_attributes, 0x200); |
| 964 | ASSERT_REG_POSITION(index_array, 0x227); | 706 | ASSERT_REG_POSITION(index_array, 0x227); |