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authorGravatar lat9nq2021-04-05 22:25:22 -0400
committerGravatar ameerj2021-07-22 21:51:26 -0400
commit0bb85f6a753c769266c95c4ba146b25b9eaaaffd (patch)
treee5d818ae7dc1d0025bb115c7a63235d866e53286 /src/shader_recompiler/ir_opt/ssa_rewrite_pass.cpp
parentshader: Fix FCMP immediate variant (diff)
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shader_recompiler,video_core: Cleanup some GCC and Clang errors
Mostly fixing unused *, implicit conversion, braced scalar init, fpermissive, and some others. Some Clang errors likely remain in video_core, and std::ranges is still a pertinent issue in shader_recompiler shader_recompiler: cmake: Force bracket depth to 1024 on Clang Increases the maximum fold expression depth thread_worker: Include condition_variable Don't use list initializers in control flow Co-authored-by: ReinUsesLisp <reinuseslisp@airmail.cc>
Diffstat (limited to 'src/shader_recompiler/ir_opt/ssa_rewrite_pass.cpp')
-rw-r--r--src/shader_recompiler/ir_opt/ssa_rewrite_pass.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/shader_recompiler/ir_opt/ssa_rewrite_pass.cpp b/src/shader_recompiler/ir_opt/ssa_rewrite_pass.cpp
index ca36253d1..346fcc377 100644
--- a/src/shader_recompiler/ir_opt/ssa_rewrite_pass.cpp
+++ b/src/shader_recompiler/ir_opt/ssa_rewrite_pass.cpp
@@ -116,7 +116,7 @@ IR::Opcode UndefOpcode(IndirectBranchVariable) noexcept {
116} 116}
117 117
118[[nodiscard]] bool IsPhi(const IR::Inst& inst) noexcept { 118[[nodiscard]] bool IsPhi(const IR::Inst& inst) noexcept {
119 return inst.Opcode() == IR::Opcode::Phi; 119 return inst.GetOpcode() == IR::Opcode::Phi;
120} 120}
121 121
122enum class Status { 122enum class Status {
@@ -278,7 +278,7 @@ private:
278}; 278};
279 279
280void VisitInst(Pass& pass, IR::Block* block, IR::Inst& inst) { 280void VisitInst(Pass& pass, IR::Block* block, IR::Inst& inst) {
281 switch (inst.Opcode()) { 281 switch (inst.GetOpcode()) {
282 case IR::Opcode::SetRegister: 282 case IR::Opcode::SetRegister:
283 if (const IR::Reg reg{inst.Arg(0).Reg()}; reg != IR::Reg::RZ) { 283 if (const IR::Reg reg{inst.Arg(0).Reg()}; reg != IR::Reg::RZ) {
284 pass.WriteVariable(reg, block, inst.Arg(1)); 284 pass.WriteVariable(reg, block, inst.Arg(1));