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1
2
3;******************************************************************************
4;
5; (C) Copyright MICROSOFT Corp. 1986
6;
7; Title: MEMM - MICROSOFT Expanded Memory Manager 386
8;
9; Module: DESC.INC - Descriptor Table Definitions for 286/386
10;
11; Version: 0.02
12;
13; Date: January 31, 1986
14;
15; Author:
16;
17;******************************************************************************
18;
19; Change log:
20;
21; DATE REVISION DESCRIPTION
22; -------- -------- -------------------------------------------------------
23; 01/31/86 Original
24; 04/07/86 A added bit map base to 386 TSS
25; 05/12/86 B Cleanup and segment reorganization
26; 06/25/86 0.02 removed A0 macros
27; 06/28/86 0.02 Name change from MEMM386 to MEMM
28;
29;******************************************************************************
30ifndef INC_LIST
31.xlist
32endif
33
34; ---------------------------------------------------
35;
36; Definitions for the access byte in a descriptor
37;
38; ---------------------------------------------------
39
40
41; Following fields are common to segment and control descriptors
42
43D_PRES equ 080h ; present in memory
44D_NOTPRES equ 0 ; not present in memory
45
46D_DPL0 equ 0 ; Ring 0
47D_DPL1 equ 020h ; Ring 1
48D_DPL2 equ 040h ; Ring 2
49D_DPL3 equ 060h ; Ring 3
50
51D_SEG equ 010h ; Segment descriptor
52D_CTRL equ 0 ; Control descriptor
53
54
55; Following fields are specific to control descriptors
56
57D_TSS equ 01h ; A Free TSS
58D_LDT equ 02h ; LDT
59D_TSS_BUSY equ 03h ; A Busy TSS
60D_CALLGATE equ 04h ; call gate
61D_TASKGATE equ 05h ; task gate
62D_INTGATE equ 06h ; interrupt gate
63D_TRAPGATE equ 07h ; trap gate
64 ; 8 is invalid
65D_386TSS equ 9 ; available 386 TSS
66 ; 0ah - Intel Reserved
67D_BUSY386TSS equ 0bh ; busy 386 TSS
68D_386CALL_GATE equ 0ch ; 386 call gate
69 ; 0dh - Intel Reserved
70D_386INT_GATE equ 0eh ; 386 interrupt gate
71D_386TRAP_GATE equ 0fh ; 386 trap gate
72
73; Following fields are specific to segment descriptors
74
75D_CODE equ 08h ; code
76D_DATA equ 0 ; data
77
78D_CONFORM equ 04h ; if code, conforming
79D_EXPDN equ 04h ; if data, expand down
80
81D_RX equ 02h ; if code, readable
82D_X equ 0 ; if code, exec only
83D_W equ 02h ; if data, writable
84D_R equ 0 ; if data, read only
85
86D_ACCESSED equ 1 ; segment accessed bit
87
88
89; Useful combination access rights bytes
90
91D_DATA0 equ (D_PRES+D_DPL0+D_SEG+D_DATA+D_W) ; Ring 0 rw data
92D_CODE0 equ (D_PRES+D_DPL0+D_SEG+D_CODE+D_RX) ; Ring 0 rx code
93D_TRAP0 equ (D_PRES+D_DPL0+D_CTRL+D_TRAPGATE) ; Ring 0 trap gate
94D_INT0 equ (D_PRES+D_DPL0+D_CTRL+D_INTGATE) ; Ring 0 int gate
95D_TSS0 equ (D_PRES+D_DPL0+D_CTRL+D_TSS) ; Ring 0 TSS
96D_386TSS0 equ (D_PRES+D_DPL0+D_CTRL+D_386TSS) ; Ring 0 TSS
97D_LDT0 equ (D_PRES+D_DPL0+D_CTRL+D_LDT) ; Ring 0 LDT
98D_386INT0 equ (D_PRES+D_DPL0+D_CTRL+D_386INT_GATE) ; Ring 0 int gate
99
100;D_DATA1 equ (D_PRES+D_DPL1+D_SEG+D_DATA+D_W) ; Ring 1 rw data
101;D_CODE1 equ (D_PRES+D_DPL1+D_SEG+D_CODE+D_RX) ; Ring 1 rx code
102
103;D_DATA2 equ (D_PRES+D_DPL2+D_SEG+D_DATA+D_W) ; Ring 2 rw data
104;D_CODE2 equ (D_PRES+D_DPL2+D_SEG+D_CODE+D_RX) ; Ring 2 rx code
105
106D_DATA3 equ (D_PRES+D_DPL3+D_SEG+D_DATA+D_W) ; Ring 3 rw data
107D_CODE3 equ (D_PRES+D_DPL3+D_SEG+D_CODE+D_RX) ; Ring 3 rx code
108D_INT3 equ (D_PRES+D_DPL3+D_CTRL+D_INTGATE) ; Ring 3 int gate
109D_GATE3 equ (D_PRES+D_DPL3+D_CTRL+D_CALLGATE) ; Ring 3 call gate
110D_386INT3 equ (D_PRES+D_DPL3+D_CTRL+D_386INT_GATE) ; Ring 3 int gate
111
112; 386 Extensions
113
114D_B_BIT equ (1 SHL 6) ; 32 bit stack offsets
115
116
117; Masks for selector fields
118
119SELECTOR_MASK equ 0fff8h ; selector index
120SEL_LOW_MASK equ 0f8h ; mask for low byte of sel indx
121TABLE_MASK equ 04h ; table bit
122RPL_MASK equ 03h ; privilige bits
123RPL_CLR equ not 03h ; clear ring bits
124
125
126; Machine Status Word bits
127
128MSW_PROTECT equ 1 ; virtual mode bit
129
130
131; System IOPL
132
133SYS_IOPL equ 3000h ; wide open
134CLEAR_IOPL equ 0cfffh ; mask to remove IOPL bits
135
136
137; Kernel Stack Size (TO BE ADDED)
138
139STK_SIZE equ 4000h ; TO BE ADDED
140
141
142; --------------------------------------------------
143;
144; Macros for creating descriptor table entries
145;
146; --------------------------------------------------
147
148
149
150; structure for 386 descriptor
151
152desc struc
153LIMIT dw 0 ; offset of last byte in segment
154BASE_LOW dw 0 ; Low 16 bits of 24 bit base address
155BASE_HIGH db 0 ; High 8 bits of 24 bit base address
156RIGHTS db 0 ; access rights
157RES386 db 0 ; reserved for 386
158BASE_XHI db 0 ; High 8 bits of 32 bit base address
159desc ends
160
161; MASK for RES386
162
163R_GRAN equ 10000000b ; granularity bit
164R_AVL equ 00010000b ; available
165R_LIMIT_XHI equ 00001111b ; limit bits 16..19
166
167; IDT_ENTRY - for interrupt and task gate definitions in IDT
168
169IDT_ENTRY macro sel, off, acc
170 dw off ; offset
171 dw sel ; selector
172 db 0 ; word count, unused for trap/int gates
173 db acc ; access rights byte
174 dw 0 ; reserved, must be 0 for 386
175endm
176
177
178; GDT_ENTRY - for static initialisation of GDT entries
179
180GDT_ENTRY macro BaseLow, BaseHi, Size, Access
181 dw Size - 1 ; segment limit
182 dw BaseLow ; low word of 24 bit base address
183 db BaseHi ; high byte of base address
184 db Access ; access rights byte
185 dw 0 ; reserved, must be 0 for 386
186endm
187
188
189; LDT_ENTRY - for static initialisation of LDT entries
190
191LDT_ENTRY macro BaseLow, BaseHi, Size, Access
192 dw Size - 1 ; segment limit
193 dw BaseLow ; low word of 24 bit base address
194 db BaseHi ; high byte of base address
195 db Access ; access rights byte
196 dw 0 ; reserved, must be 0 for 386
197endm
198
199
200;*** 286 TSS Format
201;
202
203TSS286STRUC struc
204
205 TSS286_BackLink dw 0 ; back link selector to TSS
206 TSS286_SP0 dw 0 ; ring 0 sp
207 TSS286_SS0 dw 0 ; ring 0 ss
208 TSS286_SP1 dw 0 ; ring 1 sp
209 TSS286_SS1 dw 0 ; ring 1 ss
210 TSS286_SP2 dw 0 ; ring 2 sp
211 TSS286_SS2 dw 0 ; ring 2 ss
212 TSS286_IP dw 0 ; entry point IP
213 TSS286_Flags dw 0 ; flag word
214 TSS286_AX dw 0 ; AX
215 TSS286_CX dw 0 ; CX
216 TSS286_DX dw 0 ; DX
217 TSS286_BX dw 0 ; BX
218 TSS286_SP dw 0 ; SP
219 TSS286_BP dw 0 ; BP
220 TSS286_SI dw 0 ; SI
221 TSS286_DI dw 0 ; DI
222 TSS286_ES dw 0 ; ES
223 TSS286_CS dw 0 ; CS
224 TSS286_SS dw 0 ; SS
225 TSS286_DS dw 0 ; DS
226 TSS286_LDT dw 0 ; LDT
227
228TSS286STRUC ends
229
230;*** 386 TSS Format
231;
232
233TSS386STRUC struc
234
235 TSS386_BackLink dw 0 ; back link selector to TSS
236 TSS386_Unused1 dw 0 ; unused
237 TSS386_ESP0lo dw 0 ; ring 0 ESP low word
238 TSS386_ESP0hi dw 0 ; ring 0 ESP high word
239 TSS386_SS0 dw 0 ; ring 0 SS
240 TSS386_Unused2 dw 0 ; unused
241 TSS386_ESP1 dd 0 ; ring 1 ESP
242 TSS386_SS1 dw 0 ; ring 1 SS
243 TSS386_Unused3 dw 0 ; unused
244 TSS386_ESP2 dd 0 ; ring 2 ESP
245 TSS386_SS2 dw 0 ; ring 2 SS
246 TSS386_Unused4 dw 0 ; unused
247 TSS386_CR3 dd 0 ; CR3
248 TSS386_EIP dd 0 ; EIP
249 TSS386_EFLAGS dd 0 ; EFLAGS
250 TSS386_EAX dd 0 ; EAX
251 TSS386_ECX dd 0 ; ECX
252 TSS386_EDX dd 0 ; EDX
253 TSS386_EBX dd 0 ; EBX
254 TSS386_ESP dd 0 ; ESP
255 TSS386_EBP dd 0 ; EBP
256 TSS386_ESI dd 0 ; ESI
257 TSS386_EDI dd 0 ; EDI
258 TSS386_ES dw 0 ; ES
259 TSS386_Unused5 dw 0 ; Unused
260 TSS386_CS dw 0 ; CS
261 TSS386_Unused6 dw 0 ; Unused
262 TSS386_SS dw 0 ; SS
263 TSS386_Unused7 dw 0 ; Unused
264 TSS386_DS dw 0 ; DS
265 TSS386_Unused8 dw 0 ; Unused
266 TSS386_FS dw 0 ; FS
267 TSS386_Unused9 dw 0 ; Unused
268 TSS386_GS dw 0 ; GS
269 TSS386_Unused10 dw 0 ; Unused
270 TSS386_LDT dw 0 ; LDT
271 TSS386_Unused11 dw 0 ; Unused
272 TaskAttributes dw 0 ; Task Attributes
273 BitMapBase dw 0 ; offset of Base of Bit Map
274TSS386STRUC ends
275
276.list ; end of DESC.INC
277 \ No newline at end of file
HIC SVNT DRACONES