summaryrefslogtreecommitdiff
path: root/v4.0/src/DEV/XMAEM/INDEINS.MAC
diff options
context:
space:
mode:
authorGravatar Mark Zbikowski2024-04-25 21:24:10 +0100
committerGravatar Microsoft Open Source2024-04-25 22:32:27 +0000
commit2d04cacc5322951f187bb17e017c12920ac8ebe2 (patch)
tree80ee017efa878dfd5344b44249e6a241f2a7f6e2 /v4.0/src/DEV/XMAEM/INDEINS.MAC
parentMerge pull request #430 from jpbaltazar/typoptbr (diff)
downloadms-dos-main.tar.gz
ms-dos-main.tar.xz
ms-dos-main.zip
MZ is back!HEADmain
Diffstat (limited to 'v4.0/src/DEV/XMAEM/INDEINS.MAC')
-rw-r--r--v4.0/src/DEV/XMAEM/INDEINS.MAC923
1 files changed, 923 insertions, 0 deletions
diff --git a/v4.0/src/DEV/XMAEM/INDEINS.MAC b/v4.0/src/DEV/XMAEM/INDEINS.MAC
new file mode 100644
index 0000000..c4b13e5
--- /dev/null
+++ b/v4.0/src/DEV/XMAEM/INDEINS.MAC
@@ -0,0 +1,923 @@
1COMMENT #
2* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
3* *
4* MODULE NAME : INDEINS *
5* *
6* 5669-196 (C) COPYRIGHT 1988 Microsoft Corp. *
7* *
8* DESCRIPTIVE NAME: Instructions for the 80386 *
9* *
10* STATUS (LEVEL) : Version (0) Level (1.0) *
11* *
12* FUNCTION : These macros define instructions that are recognized by *
13* the 80386 but that are not recognized by MASM 3.0. We *
14* have to create these instructions ourselves because the *
15* Macro Assembler won't. *
16* *
17* MODULE TYPE : MAC *
18* *
19* REGISTER USAGE : 80286 Standard *
20* *
21* CHANGE ACTIVITY : *
22* *
23* $MAC(INDEINS) COMP(LOAD) PROD(3270PC) : *
24* *
25* $D0=D0004700 410 870604 D : NEW FOR RELEASE 1.1 *
26* $P1=P0000311 410 870804 D : RENAME MODULE'S LIBRARY FILE TYPE TO "MAC" *
27* *
28* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
29#
30
31; Some information about creating instructions
32
33; MODIFIER BYTE VALUES
34
35; MOD REG/OPX R/M
36; --- ------- ---
37; 11 111 111
38
39; EAX AX AL 000 DISP0 00
40; ECX CX CL 001 DISPB 01
41; EDX DX DL 010 DISPW 10
42; EBX BX BL 011 DISPR 11
43; ESP SP AH 100
44; EBP BP CH 101
45; ESI SI DH 110
46; EDI DI BH 111
47
48; ES:0
49; CS:1
50; SS:2
51; DS:3
52; FS:4
53; GS:5
54
55
56; OPX FIELD VALUES
57
58; 00F-000 OPCODE VALUES 00F-001 OPCODE VALUES
59; --------------------- ---------------------
60
61; SLDT 000 SGDT 000
62; STR 001 SIDT 001
63; LLDT 010 LIDT 010
64; LTR 011 LGDT 011
65; VERR 100 SMSW 100
66; VERW 101 ? 101
67; ? 110 LMSW 110
68; ? 111 ? 111
69
70
71PAGE
72
73; Macros to move to and from the 80386 system registers and to and from the
74; new segment registers FS and GS.
75
76
77; CMOV - Move to and From Control Registers
78;
79; Examples:
80;
81; CMOV CRx,EREG
82; CMOV EREG,CRx
83;
84
85CMOV MACRO REG1,REG2
86
87 _CREGFD = 0
88 _CRCNT = 0
89 IRP TREG,<CR3,CR2,CR1,CR0>
90 IFIDN <&REG1>,<&TREG>
91 _CREGFD = 1
92 _CRCNT = 0
93 ELSE
94 _CRCNT = _CRCNT + 1
95 ENDIF
96 ENDM
97 IFE _CREGFD-1
98 F_DREG <&REG2>
99 IF _DREGNUM LT 8
100 DB 0FH
101 DB 22H
102 DB 0C0H + _CRCNT*8 + _DREGNUM
103 ELSE
104 SYNTAX ERROR - EXTENDED REGISTER EXPECTED
105 ENDIF
106 ELSE
107 _CREGFD = 0
108 _CRCNT = 0
109 IRP TREG,<CR3,CR2,CR1,CR0>
110 IFIDN <&REG2>,<&TREG>
111 _CREGFD = 1
112 _CRCNT = 0
113 ELSE
114 _CRCNT = _CRCNT + 1
115 ENDIF
116 ENDM
117 IFE _CREGFD-1
118 F_DREG <&REG1>
119 IF _DREGNUM LT 8
120 DB 0FH
121 DB 20H
122 DB 0C0H + _CRCNT*8 + _DREGNUM
123 ELSE
124 SYNTAX ERROR - EXTENDED REGISTER EXPECTED
125 ENDIF
126 ELSE
127 SYNTAX ERROR - CONTROL REGISTER EXPECTED
128 ENDIF
129 ENDIF
130 ENDM
131
132
133; DMOV - Move to and From Debug Registers
134;
135; Examples:
136;
137; DMOV DRx,EREG
138; DMOV EREG,DRx
139;
140
141DMOV MACRO REG1,REG2
142
143 _DREGFD = 0
144 _DRCNT = 0
145 IRP TREG,<DR7,DR6,DRX,DRX,DR3,DR2,DR1,DR0>
146 IFIDN <&REG1>,<&TREG>
147 _DREGFD = 1
148 _DRCNT = 0
149 ELSE
150 _DRCNT = _DRCNT + 1
151 ENDIF
152 ENDM
153 IFE _DREGFD-1
154 F_DREG <&REG2>
155 IF _DREGNUM LT 8
156 DB 0FH
157 DB 23H
158 DB 0C0H + _DRCNT*8 + _DREGNUM
159 ELSE
160 SYNTAX ERROR - EXTENDED REGISTER EXPECTED
161 ENDIF
162 ELSE
163 _DREGFD = 0
164 _DRCNT = 0
165 IRP TREG,<DR7,DR6,DRX,DRX,DR3,DR2,DR1,DR0>
166 IFIDN <&REG2>,<&TREG>
167 _DREGFD = 1
168 _DRCNT = 0
169 ELSE
170 _DRCNT = _DRCNT + 1
171 ENDIF
172 ENDM
173 IFE _DREGFD-1
174 F_DREG <&REG1>
175 IF _DREGNUM LT 8
176 DB 0FH
177 DB 21H
178 DB 0C0H + _DRCNT*8 + _DREGNUM
179 ELSE
180 SYNTAX ERROR - EXTENDED REGISTER EXPECTED
181 ENDIF
182 ELSE
183 SYNTAX ERROR - DEBUG REGISTER EXPECTED
184 ENDIF
185 ENDIF
186 ENDM
187
188; TMOV - Move to and From Test Registers
189;
190; Examples:
191;
192; TMOV TRx,EREG
193; TMOV EREG,TRx
194;
195
196TMOV MACRO REG1,REG2
197
198 _TREGFD = 0
199 _TRCNT = 0
200 IRP TREG,<TR7,TR6>
201 IFIDN <&REG1>,<&TREG>
202 _TREGFD = 1
203 _TRCNT = 0
204 ELSE
205 _TRCNT = _TRCNT + 1
206 ENDIF
207 ENDM
208 _TRCNT = _TRCNT + 6
209 IFE _TREGFD-1
210 F_DREG <&REG2>
211 IF _DREGNUM LT 8
212 DB 0FH
213 DB 26H
214 DB 0C0H + _TRCNT*8 + _DREGNUM
215 ELSE
216 SYNTAX ERROR - EXTENDED REGISTER EXPECTED
217 ENDIF
218 ELSE
219 _TREGFD = 0
220 _TRCNT = 0
221 IRP TREG,<TR7,TR6>
222 IFIDN <&REG2>,<&TREG>
223 _TREGFD = 1
224 _TRCNT = 0
225 ELSE
226 _TRCNT = _TRCNT + 1
227 ENDIF
228 ENDM
229 _TRCNT = _TRCNT + 6
230 IFE _TREGFD-1
231 F_DREG <&REG1>
232 IF _DREGNUM LT 8
233 DB 0FH
234 DB 24H
235 DB 0C0H + _TRCNT*8 + _DREGNUM
236 ELSE
237 SYNTAX ERROR - EXTENDED REGISTER EXPECTED
238 ENDIF
239 ELSE
240 SYNTAX ERROR - TEST REGISTER EXPECTED
241 ENDIF
242 ENDIF
243 ENDM
244
245; SMOV - Move to/from FS/GS segment registers from/to general registers
246;
247; Examples:
248;
249; SMOV SReg, REG16
250; SMOV REG16, SReg
251;
252
253SMOV MACRO REG1,REG2
254 _SREGNUM = 8
255 _SREG1 = 1
256 IFIDN <&REG1>,<FS>
257 _SREGNUM = 4
258 ELSE
259 IFIDN <&REG1>,<FS>
260 _SREGNUM = 4
261 ENDIF
262 ENDIF
263 IF _SREGNUM GT 7
264 IFIDN <&REG1>,<GS>
265 _SREGNUM = 5
266 ELSE
267 IFIDN <&REG1>,<GS>
268 _SREGNUM = 5
269 ENDIF
270 ENDIF
271 ENDIF
272 IF _SREGNUM GT 7
273 _SREG1 = 0
274 IFIDN <&REG2>,<FS>
275 _SREGNUM = 4
276 ELSE
277 IFIDN <&REG2>,<FS>
278 _SREGNUM = 4
279 ENDIF
280 ENDIF
281 IF _SREGNUM GT 7
282 IFIDN <&REG2>,<GS>
283 _SREGNUM = 5
284 ELSE
285 IFIDN <&REG2>,<GS>
286 _SREGNUM = 5
287 ENDIF
288 ENDIF
289 ENDIF
290 ENDIF
291 IF _SREGNUM GT 7
292 SYNTAX ERROR - FS OR GS SEGMENT REGISTER EXPECTED
293 ELSE
294 IF _SREG1 EQ 1
295 DB 8EH
296 F_WREG <&REG2>
297 ELSE
298 DB 8CH
299 F_WREG <&REG1>
300 ENDIF
301 IF _WREGNUM GT 7
302 SYNTAX ERROR - WORD REGISTER EXPECTED
303 ELSE
304 DB 0C0H + _SREGNUM*8 + _WREGNUM
305 ENDIF
306 ENDIF
307 ENDM
308
309F_MOD MACRO TYPE,DISP1,DISP2
310 _DISP = 2
311;; 1 0
312 IRP _TEST_,<DISP32, DISP8>
313 IFIDN <&TYPE>,<&_TEST_>
314 _DISP = 0
315 ELSE
316 _DISP = _DISP + 1
317 ENDIF
318 ENDM
319 IFE (_DISP LT 2)
320;; 1 0
321 IRP _TEST_,<DISP32, DISP8>
322 IFIDN <&TYPE>,<&_TEST_>
323 _DISP = 0
324 ELSE
325 _DISP = _DISP + 1
326 ENDIF
327 ENDM
328 ENDIF
329 IF _DISP LT 2
330 IFB <&DISP1>
331 SYNTAX ERROR - IMMEDIATE OPERAND EXPECTED
332 ELSE
333 IFE _DISP-1
334 _MOD = 2
335 ELSE
336 _MOD = 1
337 ENDIF
338 ENDIF
339 ELSE
340 _MOD = 0
341 ENDIF
342 ENDM
343
344MK_DISP MACRO P3,P4
345 IFE _DISP
346 DB &P3
347 ELSE
348 DW &P3
349 IFNB <&P4>
350 IFDIF <&P4>,<IMMD>
351 DW &P4
352 ENDIF
353 ELSE
354 DW 0H
355 ENDIF
356 ENDIF
357 ENDM
358
359MK_IMMD MACRO P2,P3,P4,P5
360 _IMMDCNT = 3
361 IRP _PARM,<&P2,&P3,&P4,&P5>
362 IFE _IMMDCNT
363 IF _SIZE EQ 1
364 DB &_PARM
365 ELSE
366 DW &_PARM
367 ENDIF
368 ELSE
369 IFE _IMMDCNT-1
370 IF _SIZE EQ 4
371 IFNB <&_PARM>
372 DW &_PARM
373 ELSE
374 DW 0H
375 ENDIF
376 ENDIF
377 ENDIF
378 ENDIF
379 _IMMDCNT = _IMMDCNT + 1
380 IFIDN <&_PARM>,<IMMD>
381 _IMMDCNT = 0
382 ENDIF
383 ENDM
384 ENDM
385
386F_BREG MACRO TBREG
387 _BREGNUM = 0
388 IRP TREG,<BH,DH,CH,AH,BL,DL,CL,AL>
389 IFIDN <&TBREG>,<&TREG>
390 _BREGNUM = 0
391 ELSE
392 _BREGNUM = _BREGNUM + 1
393 ENDIF
394 ENDM
395 IFE (_BREGNUM LT 8)
396 IRP TREG,<BH,DH,CH,AH,BL,DL,CL,AL>
397 IFIDN <&TDREG>,<&TREG>
398 _BREGNUM = 0
399 ELSE
400 _BREGNUM = _BREGNUM + 1
401 ENDIF
402 ENDM
403 ENDIF
404 ENDM
405
406F_WREG MACRO TWREG
407 _WREGNUM = 0
408 IRP TREG,<DI,SI,BP,SP,BX,DX,CX,AX>
409 IFIDN <&TWREG>,<&TREG>
410 _WREGNUM = 0
411 ELSE
412 _WREGNUM = _WREGNUM + 1
413 ENDIF
414 ENDM
415 IFE (_WREGNUM LT 8)
416 IRP TREG,<DI,SI,BP,SP,BX,DX,CX,AX>
417 IFIDN <&TWREG>,<&TREG>
418 _WREGNUM = 0
419 ELSE
420 _WREGNUM = _WREGNUM + 1
421 ENDIF
422 ENDM
423 ENDIF
424 ENDM
425
426F_DREG MACRO TDREG
427 _DREGNUM = 0
428 IRP TREG,<EDI,ESI,EBP,ESP,EBX,EDX,ECX,EAX>
429 IFIDN <&TDREG>,<&TREG>
430 _DREGNUM = 0
431 ELSE
432 _DREGNUM = _DREGNUM + 1
433 ENDIF
434 ENDM
435 IFE (_DREGNUM LT 8)
436 IRP TREG,<EDI,ESI,EBP,ESP,EBX,EDX,ECX,EAX>
437 IFIDN <&TDREG>,<&TREG>
438 _DREGNUM = 0
439 ELSE
440 _DREGNUM = _DREGNUM + 1
441 ENDIF
442 ENDM
443 ENDIF
444 ENDM
445
446F_BASE MACRO TBASE
447 _BASE = 0
448;; 7 6 5 4 3 2 1 0
449 IRP TREG,<[EDI],[ESI],[EBP],[ESP],[EBX],[EDX],[ECX],[EAX]>
450 IFIDN <&TBASE>,<&TREG>
451 _BASE = 0
452 ELSE
453 _BASE = _BASE + 1
454 ENDIF
455 ENDM
456 IFE (_BASE LT 8)
457;; 7 6 5 4 3 2 1 0
458 IRP TREG,<[EDI],[ESI],[EBP],[ESP],[EBX],[EDX],[ECX],[EAX]>
459 IFIDN <&TBASE>,<&TREG>
460 _BASE = 0
461 ELSE
462 _BASE = _BASE + 1
463 ENDIF
464 ENDM
465 ENDIF
466 ENDM
467
468F_INDEX MACRO INDX
469 _INDEX = 0
470;; 7 6 5 4 3 2 1 0
471 IRP TREG,<[EDI,[ESI,[EBP,_XX_,[EBX,[EDX,[ECX,[EAX>
472 IFIDN <&INDX>,<&TREG>
473 _INDEX = 0
474 ELSE
475 _INDEX = _INDEX + 1
476 ENDIF
477 ENDM
478 IFE (_INDEX LT 8)
479;; 7 6 5 4 3 2 1 0
480 IRP TREG,<[EDI,[ESI,[EBP,_XX_,[EBX,[EDX,[ECX,[EAX>
481 IFIDN <&INDX>,<&TREG>
482 _INDEX = 0
483 ELSE
484 _INDEX = _INDEX + 1
485 ENDIF
486 ENDM
487 ENDIF
488 ENDM
489
490F_SCALE MACRO TSCALE
491 _SCALE = 0
492;; 3 2 1 0
493 IRP TREG,<*8], *4], *2], *1]>
494 IFIDN <&TSCALE>,<&TREG>
495 _SCALE = 0
496 ELSE
497 _SCALE = _SCALE + 1
498 ENDIF
499 ENDM
500 ENDM
501
502PAGE
503
504; Macros to PUSH and POP the new segment registers FS and GS
505
506
507; PUSH_FS - PUSH FS segment register
508
509PUSH_FS MACRO
510 DB 00FH
511 DB 0A0H
512 ENDM
513
514
515; PUSH_GS - PUSH GS segment register
516
517PUSH_GS MACRO
518 DB 00FH
519 DB 0A8H
520 ENDM
521
522
523; POP_FS - POP FS segment register
524
525POP_FS MACRO
526 DB 00FH
527 DB 0A1H
528 ENDM
529
530
531; POP_GS - POP GS segment register
532
533POP_GS MACRO
534 DB 00FH
535 DB 0A9H
536 ENDM
537
538PAGE
539
540; Macros for multiplication instructions
541
542; RIMUL - Uncharacterized Signed Multiply (16-bit)
543; Syntax: RIMUL REG,REG/MEM
544
545RIMUL MACRO REG,OPND
546 LOCAL L1,L2
547 _2BYTEOP = 1
548 DB 0FH
549 .XLIST
550L1 LABEL BYTE
551 .LIST
552 CMP &REG,&OPND
553 .XLIST
554L2 LABEL BYTE
555 ORG OFFSET CS:L1
556 .LIST
557 DB 0AFH
558 .XLIST
559 ORG OFFSET CS:L2
560 .LIST
561 ENDM
562
563; ERIMUL - 32 bit Uncharacterized Signed Multiply
564; Systax: ERIMUL REG,REG/MEM
565
566ERIMUL MACRO REG,OPND
567 DB 66H
568 RIMUL &REG,<&OPND>
569 ENDM
570
571PAGE
572
573; Macros to load pointers with the segment in FS, GS or SS. That is, these are
574; just like the instructions LDS and LES but for the FS, GS and SS registers.
575
576NEWLS MACRO OP,REG,OPND
577 LOCAL L1,L2
578 DB 0FH
579 .XLIST
580L1 LABEL BYTE
581 .LIST
582 LDS &REG,DWORD PTR &OPND
583 .XLIST
584L2 LABEL BYTE
585 ORG OFFSET CS:L1
586 .LIST
587 DB &OP
588 .XLIST
589 ORG OFFSET CS:L2
590 .LIST
591 ENDM
592
593; LFS REG,OPND
594
595LFS MACRO REG,OPND
596 NEWLS 0B4H,&REG,<&OPND>
597 ENDM
598
599; LGS REG,OPND
600
601LGS MACRO REG,OPND
602 NEWLS 0B5H,&REG,<&OPND>
603 ENDM
604
605; LSS REG,OPND
606
607LSS MACRO REG,OPND
608 NEWLS 0B2H,&REG,<&OPND>
609 ENDM
610
611; Now we do 32 bit versions of the above
612
613; ELFS REG,OPND
614
615ELFS MACRO REG,OPND
616 DB 66H
617 NEWLS 0B4H,&REG,<&OPND>
618 ENDM
619
620; ELGS REG,OPND
621
622ELGS MACRO REG,OPND
623 DB 66H
624 NEWLS 0B5H,&REG,<&OPND>
625 ENDM
626
627; ELSS REG,OPND
628
629ELSS MACRO REG,OPND
630 DB 66H
631 NEWLS 0B2H,&REG,<&OPND>
632 ENDM
633
634PAGE
635
636; Macros for some shift instructions
637
638; Shift Left Double R/M, Reg [CL = COUNT] [16-bit Operand]
639; SHLD OPND,REG (Double left shift) [CL = COUNT]
640
641SHLD MACRO OPND,REG
642 SHDOP 0A5H,<&OPND>,&REG
643 ENDM
644
645
646; Shift Right Double R/M, Reg [CL = COUNT] [16-bit Operand]
647; SHRD OPND,REG (Double right shift) [CL = COUNT]
648
649SHRD MACRO OPND,REG
650 SHDOP 0ADH,<&OPND>,&REG
651 ENDM
652
653
654; Shift Left Double R/M, Reg, Immd (8-bit) [16-bit Operand]
655; SHLDI OPND,REG,IMMD-8
656
657SHLDI MACRO OPND,REG,IMMD
658 SHDOP 0A4H,<&OPND>,&REG
659 DB &IMMD
660 ENDM
661
662
663; Shift Right Double R/M, Reg, Immd (8-bit) [16-bit Operand]
664; SHRDI OPND,REG,IMMD-8
665
666SHRDI MACRO OPND,REG,IMMD
667 SHDOP 0ACH,<&OPND>,&REG
668 DB &IMMD
669 ENDM
670
671; Now 32 bit versions of the above
672
673; Shift Left Double R/M, Reg [CL = COUNT] [32-bit Operand]
674; ESHLD OPND,REG (Double left shift) [CL = COUNT]
675
676ESHLD MACRO OPND,REG
677 DB 66H
678 SHDOP 0A5H,<&OPND>,&REG
679 ENDM
680
681
682; Shift Right Double R/M, Reg [CL = COUNT] [32-bit Operand]
683; ESHRD OPND,REG (Double right shift) [CL = COUNT]
684
685ESHRD MACRO OPND,REG
686 DB 66H
687 SHDOP 0ADH,<&OPND>,&REG
688 ENDM
689
690
691; Shift Left Double R/M, Reg, Immd (8-bit) [32-bit Operand]
692; ESHLDI OPND,REG,IMMD-8 (Double left shift)
693
694ESHLDI MACRO OPND,REG,IMMD
695 DB 66H
696 SHDOP 0A4H,<&OPND>,&REG
697 DB &IMMD
698 ENDM
699
700
701; Shift Right Double R/M, Reg, Immd (8-bit) [32-bit Operand]
702; ESHRDI OPND,REG,IMMD-8 (Double right shift)
703
704ESHRDI MACRO OPND,REG,IMMD
705 DB 66H
706 SHDOP 0ACH,<&OPND>,&REG
707 DB &IMMD
708 ENDM
709
710
711SHDOP MACRO OP,OPND,REG
712 LOCAL L1,L2
713 _2BYTEOP = 1
714 DB 0FH
715 .XLIST
716L1 LABEL BYTE
717 .LIST
718 OR &REG,&OPND
719 .XLIST
720L2 LABEL BYTE
721 ORG OFFSET CS:L1
722 .LIST
723 DB &OP
724 .XLIST
725 ORG OFFSET CS:L2
726 .LIST
727 ENDM
728
729PAGE
730
731; The following two instructions, CALLFAR and JUMPFAR, work in the
732; MS Macro Assembler, but not for intersegment direct. The assembler
733; generates segments based on 8088 values, and we need them based
734; on protect-mode selector values. The assembler works just ducky for
735; jump and call far indirect, since you go pick up the offset and
736; segment at execution time.
737
738CALLFAR MACRO DISP,SEGMENT
739
740 DB 09AH ; Call far direct
741 DW (OFFSET &DISP) ; to this offset
742 DW &SEGMENT ; in this segment
743
744 ENDM
745
746
747JUMPFAR MACRO DISP,SEGMENT
748
749 DB 0EAH ; Jump far direct
750 DW (OFFSET &DISP) ; to this offset
751 DW &SEGMENT ; in this segment
752
753 ENDM
754
755PAGE
756
757; Macros for extended jump instructions
758
759LJCOND MACRO OP,DISPL
760 _2BYTEOP = 1
761TEMP = $ + 4
762 DB 0FH
763 DB &OP
764 DW (OFFSET &DISPL)-(&TEMP)
765 ENDM
766
767; LJO DISPL (Long Jump on Overflow)
768LJO MACRO DISPL
769 LJCOND 80H,<&DISPL>
770 ENDM
771
772
773; LJNO DISPL (Long Jump on NO Overflow)
774LJNO MACRO DISPL
775 LJCOND 81H,<&DISPL>
776 ENDM
777
778; LJB DISPL (Long Jump on Below)
779LJB MACRO DISPL
780 LJCOND 82H,<&DISPL>
781 ENDM
782
783; LJC DISPL (Long Jump on Carry)
784LJC MACRO DISPL
785 LJCOND 82H,<&DISPL>
786 ENDM
787
788; LNAE DISPL (Long Jump on Not Above or Equal)
789LNAE MACRO DISPL
790 LJCOND 82H,<&DISPL>
791 ENDM
792
793; LJNB DISPL (Long Jump on Not Below)
794LJNB MACRO DISPL
795 LJCOND 83H,<&DISPL>
796 ENDM
797
798; LJNC DISPL (Long Jump on No Carry)
799LJNC MACRO DISPL
800 LJCOND 83H,<&DISPL>
801 ENDM
802
803; LJAE DISPL (Long Jump on Above or Equal)
804LJAE MACRO DISPL
805 LJCOND 83H,<&DISPL>
806 ENDM
807
808; LJE DISPL (Long Jump on Equal)
809LJE MACRO DISPL
810 LJCOND 84H,<&DISPL>
811 ENDM
812
813; LJZ DISPL (Long Jump on Zero)
814LJZ MACRO DISPL
815 LJCOND 84H,<&DISPL>
816 ENDM
817
818; LJNE DISPL (Long Jump on Not Equal)
819LJNE MACRO DISPL
820 LJCOND 85H,<&DISPL>
821 ENDM
822
823; LJNZ DISPL (Long Jump on Not Zero)
824LJNZ MACRO DISPL
825 LJCOND 85H,<&DISPL>
826 ENDM
827
828; LJBE DISPL (Long Jump on Below or Equal)
829LJBE MACRO DISPL
830 LJCOND 86H,<&DISPL>
831 ENDM
832
833; LJNA DISPL (Long Jump on Not Above)
834LJNA MACRO DISPL
835 LJCOND 86H,<&DISPL>
836 ENDM
837
838; LJNBE DISPL (Long Jump on Not Below or Equal)
839LJNBE MACRO DISPL
840 LJCOND 87H,<&DISPL>
841 ENDM
842
843; LJA DISPL (Long Jump on Above)
844LJA MACRO DISPL
845 LJCOND 87H,<&DISPL>
846 ENDM
847
848; LJS DISPL (Long Jump on Sign)
849LJS MACRO DISPL
850 LJCOND 88H,<&DISPL>
851 ENDM
852
853; LJNS DISPL (Long Jump on No Sign)
854LJNS MACRO DISPL
855 LJCOND 89H,<&DISPL>
856 ENDM
857
858; LJP DISPL (Long Jump on Parity)
859LJP MACRO DISPL
860 LJCOND 8AH,<&DISPL>
861 ENDM
862
863; LJPE DISPL (Long Jump on Parity Even)
864LJPE MACRO DISPL
865 LJCOND 8AH,<&DISPL>
866 ENDM
867
868; LJNP DISPL (Long Jump on No Parity)
869LJNP MACRO DISPL
870 LJCOND 8BH,<&DISPL>
871 ENDM
872
873; LJPO DISPL (Long Jump on Parity Odd)
874LJPO MACRO DISPL
875 LJCOND 8BH,<&DISPL>
876 ENDM
877
878; LJL DISPL (Long Jump on Less)
879LJL MACRO DISPL
880 LJCOND 8CH,<&DISPL>
881 ENDM
882
883; LJNGE DISPL (Long Jump on Not Greater or Equal)
884LJNGE MACRO DISPL
885 LJCOND 8CH,<&DISPL>
886 ENDM
887
888; LJNL DISPL (Long Jump on Not Less)
889LJNL MACRO DISPL
890 LJCOND 8DH,<&DISPL>
891 ENDM
892
893; LJGE DISPL (Long Jump on Greater than or Equal)
894LJGE MACRO DISPL
895 LJCOND 8DH,<&DISPL>
896 ENDM
897
898; LJLE DISPL (Long Jump on Less than or Equal)
899LJLE MACRO DISPL
900 LJCOND 8EH,<&DISPL>
901 ENDM
902
903; LJNG DISPL (Long Jump on Not Greater than)
904LJNG MACRO DISPL
905 LJCOND 8EH,<&DISPL>
906 ENDM
907
908; LJNLE DISPL (Long Jump on Not Less than or Equal)
909LJNLE MACRO DISPL
910 LJCOND 8FH,<&DISPL>
911 ENDM
912
913; LJG DISPL (Long Jump on Greater than)
914LJG MACRO DISPL
915 LJCOND 8FH,<&DISPL>
916 ENDM
917
918; JECXZ DISPL (Jump short on ECX Zero)
919JECEXZ MACRO DISPL
920 DB 66H
921 JCXZ &DISPL
922 ENDM
923
HIC SVNT DRACONES