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* kernel/thread: Use a regular pointer for the owner/current processGravatar Lioncash2018-10-101-1/+1
| | | | | | | | | | | There's no real need to use a shared pointer in these cases, and only makes object management more fragile in terms of how easy it would be to introduce cycles. Instead, just do the simple thing of using a regular pointer. Much of this is just a hold-over from citra anyways. It also doesn't make sense from a behavioral point of view for a process' thread to prolong the lifetime of the process itself (the process is supposed to own the thread, not the other way around).
* kernel/thread: Make all instance variables privateGravatar Lioncash2018-10-042-2/+2
| | | | | | | | | | | | | | | | | | | | Many of the member variables of the thread class aren't even used outside of the class itself, so there's no need to make those variables public. This change follows in the steps of the previous changes that made other kernel types' members private. The main motivation behind this is that the Thread class will likely change in the future as emulation becomes more accurate, and letting random bits of the emulator access data members of the Thread class directly makes it a pain to shuffle around and/or modify internals. Having all data members public like this also makes it difficult to reason about certain bits of behavior without first verifying what parts of the core actually use them. Everything being public also generally follows the tendency for changes to be introduced in completely different translation units that would otherwise be better introduced as an addition to the Thread class' public interface.
* kernel/process: Make data member variables privateGravatar Lioncash2018-09-301-2/+2
| | | | | | | Makes the public interface consistent in terms of how accesses are done on a process object. It also makes it slightly nicer to reason about the logic of the process class, as we don't want to expose everything to external code.
* arm_interface: Add missing fpsr/tpidr members to the ThreadContext structGravatar Lioncash2018-09-302-4/+14
| | | | | | | | | Internally within the kernel, it also includes a member variable for the floating-point status register, and TPIDR, so we should do the same here to match it. While we're at it, also fix up the size of the struct and add a static assertion to ensure it always stays the correct size.
* Merge pull request #1395 from lioncash/vmGravatar bunnei2018-09-291-2/+3
|\ | | | | process/vm_manager: Initial modifications to load NPDM metadata
| * memory: Dehardcode the use of a 36-bit address spaceGravatar Lioncash2018-09-241-2/+3
| | | | | | | | | | Given games can also request a 32-bit or 39-bit address space, we shouldn't be hardcoding the address space range as 36-bit.
* | FPCR register was uninitialized at start upGravatar Philippe Babin2018-09-221-1/+1
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* arm_interface: Replace kernel vm_manager include with a forward declarationGravatar Lioncash2018-09-203-1/+9
| | | | | | Avoids an unnecessary inclusion and also uncovers three places where indirect inclusions were relied upon, which allows us to also resolve those.
* arm_dynarmic: Halt when BRK encounteredGravatar MerryMage2018-09-201-0/+1
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* arm_dynarmic: Support BKPT instructionGravatar MerryMage2018-09-191-0/+11
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* Merge pull request #1344 from lioncash/armGravatar bunnei2018-09-185-72/+59
|\ | | | | arm_interface: Remove ARM11-isms from the CPU interface
| * arm_interface: Remove ARM11-isms from the CPU interfaceGravatar Lioncash2018-09-185-72/+59
| | | | | | | | | | | | | | | | | | This modifies the CPU interface to more accurately match an AArch64-supporting CPU as opposed to an ARM11 one. Two of the methods don't even make sense to keep around for this interface, as Adv Simd is used, rather than the VFP in the primary execution state. This is essentially a modernization change that should have occurred from the get-go.
* | arm_dynarmic: Correct ExclusiveWrite128()'s operationGravatar Lioncash2018-09-181-2/+2
|/ | | | | | Previously the second half of the value being written would overwrite the first half. Thankfully this wasn't a bug that was being encountered, as the function is currently unused.
* Port #4182 from Citra: "Prefix all size_t with std::"Gravatar fearlessTobi2018-09-156-36/+37
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* Update microprofile scopes.Gravatar Markus Wick2018-09-042-2/+6
| | | | | | Blame the subsystems which deserve the blame :) The updated list is not complete, just the ones I've spotted on random sampling the stack trace.
* core/core: Replace includes with forward declarations where applicableGravatar Lioncash2018-08-311-0/+1
| | | | | | | | | | | The follow-up to e2457418dae19b889b2ad85255bb95d4cd0e4bff, which replaces most of the includes in the core header with forward declarations. This makes it so that if any of the headers the core header was previously including change, then no one will need to rebuild the bulk of the core, due to core.h being quite a prevalent inclusion. This should make turnaround for changes much faster for developers.
* core: Namespace all code in the arm subdirectory under the Core namespaceGravatar Lioncash2018-08-247-2/+30
| | | | Gets all of these types and interfaces out of the global namespace.
* dynarmic: Update to 550d662Gravatar MerryMage2018-08-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | 550d662 load_store_exclusive: Define s == t state to be Constraint_NONE 0b69381 A64/translate: Allow for unpredictable behaviour to be defined 6d236d4 system: Implement MRS CNTFRQ_EL0 6cbb6fb A32/testenv: Add missing headers 6729328 externals: Update xbyak to v5.67 1812bd2 Squashed 'externals/xbyak/' changes from 2794cde7..671fc805 9a95802 externals: Document subtrees 714a840 A64: Implement SQ{ADD, SUB}, and UQ{ADD, SUB}'s vector variants 8cab459 A64: Implement UQADD/UQSUB's scalar variants 18a8151 ir: Add opcodes for unsigned saturating add and subtract a5660ee x64/reg_alloc: Use type alias for array returned by GetArgumentInfo() 29489b5 ir/value: Use type alias CoprocessorInfo for std::array<u8, 8> e23ba26 status_register_access: Add support for bits 0 and 1 of mask to MSR 55190bd fuzz_with_unicorn: Split utility functions into fuzz_util 23b049d A32/translate/load_store: Correct detection of writeback 7ec9f15 A32/translate: Add TranslateSingleInstruction efeecb4 A32/ir_emitter: Bug fix: IREmitter::ExceptionRaised using incorrect opcode 08d1d19 A32/decoders: Split instruction list into include file 2d929cc tests: Refactor unicorn_emu to allow for A32 unicorn f672368 microinstruction: Improve assert messages 7ebff50 emit_x64_vector: EmitVectorNarrow16: AVX512 implementation edce230 emit_x64_vector: EmitVectorNarrow32: prefer pblendw to loading constant
* arm_dynarmic: Remove IsExecuting check from PrepareRescheduleGravatar MerryMage2018-08-131-3/+1
| | | | No longer required. HaltExecution is a no-op if it is not currently executing.
* CPU/Timing: Use an approximated amortized amount of ticks when advancing timing.Gravatar Subv2018-08-121-1/+10
| | | | | | | | We divide the number of ticks to add by the number of cores (4) to obtain a more or less rough estimate of the actual number of ticks added. This assumes that all 4 cores are doing similar work. Previously we were adding ~4 times the number of ticks, thus making the games think that time was going way too fast. This lets us bypass certain hangs in some games like Breath of the Wild. We should modify our CoreTiming to support multiple cores (both running in a single thread, and in multiple host threads).
* GDBStub works with both Unicorn and Dynarmic now (#941)Gravatar Hedges2018-08-061-1/+1
| | | | | | * GDBStub works with both Unicorn and Dynarmic now * Tidy up
* Merge pull request #876 from lioncash/includeGravatar bunnei2018-07-311-1/+1
|\ | | | | kernel: Remove unnecessary includes
| * kernel: Remove unnecessary includesGravatar Lioncash2018-07-311-1/+1
| | | | | | | | | | Removes unnecessary direct dependencies in some headers and also gets rid of indirect dependencies that were being relied on to be included.
* | arm_dynarmic: Make SetTlsAddress() prototype and definition consistentGravatar Lioncash2018-07-311-1/+1
| | | | | | | | Makes the definition use the same type aliases as in its prototype.
* | arm_dynarmic: Remove unnecessary qualifying of ThreadContextGravatar Lioncash2018-07-311-3/+3
| | | | | | | | | | Given the ARM_Dynarmic class inherits from ARM_Interface, we don't need to qualify here.
* | arm_dynarmic: Correct initializer list orderGravatar Lioncash2018-07-311-5/+3
|/ | | | | | | | | Amends the initializer list to be in the same order that each variable would be initialized in. We also do this to ensure we don't use a bogus uninitialized instance of the exclusive monitor within MakeJit() We can also remove the jit member from the initializer list as this is initialized by PageTableChanged()
* arm_dynarmic: Make MakeJit() a const member functionGravatar Lioncash2018-07-232-3/+3
| | | | | This functions doesn't modify instance state, so it can be a made a const member function.
* exclusive_monitor: Use consistent type alias for u64Gravatar Lioncash2018-07-233-22/+18
| | | | | Uses the same type aliases we use for virtual addresses, and converts one lingering usage of std::array<uint64_t, 2> to u128 for consistency.
* Implement exclusive monitorGravatar MerryMage2018-07-224-8/+119
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* Merge pull request #750 from lioncash/ctxGravatar bunnei2018-07-213-9/+0
|\ | | | | arm_interface: Remove unused tls_address member of ThreadContext
| * arm_interface: Remove unused tls_address member of ThreadContextGravatar Lioncash2018-07-203-9/+0
| | | | | | | | | | Currently, the TLS address is set within the scheduler, making this member unused.
* | CPU: Save and restore the TPIDR_EL0 system register on every context switch.Gravatar Subv2018-07-205-0/+26
|/ | | | Note that there's currently a dynarmic bug preventing this register from being written.
* scheduler: Clear exclusive state when switching contextsGravatar MerryMage2018-07-165-0/+10
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* More improvements to GDBStub (#653)Gravatar Hedges2018-07-121-2/+2
| | | | | | | | | | | * More improvements to GDBStub - Debugging of threads should work correctly with source and assembly level stepping and modifying registers and memory, meaning threads and callstacks are fully clickable in VS. - List of modules is available to the client, with assumption that .nro and .nso are backed up by an .elf with symbols, while deconstructed ROMs keep N names. - Initial support for floating point registers. * Tidy up as requested in PR feedback * Tidy up as requested in PR feedback
* Update clang formatGravatar James Rowe2018-07-021-1/+1
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* Rename logging macro back to LOG_*Gravatar James Rowe2018-07-021-1/+1
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* GDB Stub Improvements (#508)Gravatar Hedges2018-06-062-1/+41
| | | | | | | | | | * GDB Stub should work now. * Applied clang-format. * Replaced htonll with swap64. * Tidy up.
* core: Implement multicore support.Gravatar bunnei2018-05-101-1/+1
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* general: Make formatting of logged hex values more straightforwardGravatar Lioncash2018-05-022-2/+2
| | | | | | This makes the formatting expectations more obvious (e.g. any zero padding specified is padding that's entirely dedicated to the value being printed, not any pretty-printing that also gets tacked on).
* general: Convert assertion macros over to be fmt-compatibleGravatar Lioncash2018-04-272-3/+3
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* core: Replace remaining old non-generic logger usages with fmt-capable ↵Gravatar Lioncash2018-04-261-2/+2
| | | | | | | | equivalents LOG_GENERIC usages will be amended in a follow-up to keep API changes separate from interface changes, as it will require removing a parameter from the relevant function in the VMManager class.
* arm_dynarmic: Fix timingGravatar MerryMage2018-03-241-7/+3
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* Clean Warnings (?)Gravatar N00byKing2018-03-191-1/+1
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* Merge pull request #193 from N00byKing/3184_2_robotic_boogalooGravatar bunnei2018-03-185-35/+31
|\ | | | | Implement Pull #3184 from citra: core/arm: Improve timing accuracy before service calls in JIT (Rebased)
| * Implements citra-emu/citra#3184Gravatar N00byKing2018-02-255-35/+31
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* | arm_interface: Support unmapping previously mapped memory.Gravatar bunnei2018-03-165-2/+15
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* | core: Move process creation out of global state.Gravatar bunnei2018-03-141-1/+2
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* | Merge pull request #212 from mailwl/stubsGravatar bunnei2018-02-231-1/+2
|\ \ | | | | | | Stub some functions
| * | Stub am::SetScreenShotPermission, and bsd::StartMonitoring functionsGravatar mailwl2018-02-221-1/+2
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* | dynarmic: Update to 6b4c6b0Gravatar MerryMage2018-02-211-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 6b4c6b0 impl: Update PC when raising exception 7a1313a A64: Implement FDIV (vector) b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL b277bf5 Correct FPSR and FPCR 7673933 A64: Implement USHL 8d0e558 A64: Implement UCVTF (vector, integer), scalar variant da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point) 7479684 A64: Implement system register TPIDR_EL0 0fd75fd A64: Implement system registers FPCR and FPSR 31e370c A64: Implement system register CNTPCT_EL0 9a88fd3 A64: Implement system register CTR_EL0 1d16896 A64: Implement NEG (vector) 3184edf IR: Add IR instruction ZeroVector 31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter 567eb1a A64: Implement FMINNM (scalar) c6d8fa1 A64: Implement FMAXNM (scalar) 616056d constant_pool: Add frame parameter a3747cb A64: Implement ADDP (scalar) 5cd5d9f reg_alloc: Only exchange GPRs dd0452a A64: Implement DUP (element), scalar variant e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0 40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar) 7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect 826dce2 travis: Switch unicorn repository 9605f28 a64/config: Allow NaN emulation accuracy to be set e9435bc a64_emit_x64: Add conf to A64EmitContext 30b596d fuzz_with_unicorn: Explicitly test floating point instructions be292a8 A64: Implement FSQRT (scalar) 3c42d48 backend_x64: Accurately handle NaNs 4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
HIC SVNT DRACONES