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-rw-r--r--src/video_core/engines/maxwell_3d.cpp80
-rw-r--r--src/video_core/engines/maxwell_3d.h8
-rw-r--r--src/video_core/textures/texture.h84
3 files changed, 147 insertions, 25 deletions
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index 986165c6d..088d4357e 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -294,8 +294,45 @@ void Maxwell3D::ProcessCBData(u32 value) {
294 regs.const_buffer.cb_pos = regs.const_buffer.cb_pos + 4; 294 regs.const_buffer.cb_pos = regs.const_buffer.cb_pos + 4;
295} 295}
296 296
297std::vector<Texture::TICEntry> Maxwell3D::GetStageTextures(Regs::ShaderStage stage) { 297Texture::TICEntry Maxwell3D::GetTICEntry(u32 tic_index) const {
298 std::vector<Texture::TICEntry> textures; 298 GPUVAddr tic_base_address = regs.tic.TICAddress();
299
300 GPUVAddr tic_address_gpu = tic_base_address + tic_index * sizeof(Texture::TICEntry);
301 VAddr tic_address_cpu = memory_manager.PhysicalToVirtualAddress(tic_address_gpu);
302
303 Texture::TICEntry tic_entry;
304 Memory::ReadBlock(tic_address_cpu, &tic_entry, sizeof(Texture::TICEntry));
305
306 ASSERT_MSG(tic_entry.header_version == Texture::TICHeaderVersion::BlockLinear,
307 "TIC versions other than BlockLinear are unimplemented");
308
309 ASSERT_MSG(tic_entry.texture_type == Texture::TextureType::Texture2D,
310 "Texture types other than Texture2D are unimplemented");
311
312 auto r_type = tic_entry.r_type.Value();
313 auto g_type = tic_entry.g_type.Value();
314 auto b_type = tic_entry.b_type.Value();
315 auto a_type = tic_entry.a_type.Value();
316
317 // TODO(Subv): Different data types for separate components are not supported
318 ASSERT(r_type == g_type && r_type == b_type && r_type == a_type);
319
320 return tic_entry;
321}
322
323Texture::TSCEntry Maxwell3D::GetTSCEntry(u32 tsc_index) const {
324 GPUVAddr tsc_base_address = regs.tsc.TSCAddress();
325
326 GPUVAddr tsc_address_gpu = tsc_base_address + tsc_index * sizeof(Texture::TSCEntry);
327 VAddr tsc_address_cpu = memory_manager.PhysicalToVirtualAddress(tsc_address_gpu);
328
329 Texture::TSCEntry tsc_entry;
330 Memory::ReadBlock(tsc_address_cpu, &tsc_entry, sizeof(Texture::TSCEntry));
331 return tsc_entry;
332}
333
334std::vector<Texture::FullTextureInfo> Maxwell3D::GetStageTextures(Regs::ShaderStage stage) const {
335 std::vector<Texture::FullTextureInfo> textures;
299 336
300 auto& fragment_shader = state.shader_stages[static_cast<size_t>(stage)]; 337 auto& fragment_shader = state.shader_stages[static_cast<size_t>(stage)];
301 auto& tex_info_buffer = fragment_shader.const_buffers[regs.tex_cb_index]; 338 auto& tex_info_buffer = fragment_shader.const_buffers[regs.tex_cb_index];
@@ -309,31 +346,34 @@ std::vector<Texture::TICEntry> Maxwell3D::GetStageTextures(Regs::ShaderStage sta
309 static constexpr size_t TextureInfoOffset = 0x20; 346 static constexpr size_t TextureInfoOffset = 0x20;
310 347
311 for (GPUVAddr current_texture = tex_info_buffer.address + TextureInfoOffset; 348 for (GPUVAddr current_texture = tex_info_buffer.address + TextureInfoOffset;
312 current_texture < tex_info_buffer_end; current_texture += 4) { 349 current_texture < tex_info_buffer_end; current_texture += sizeof(Texture::TextureHandle)) {
313 350
314 Texture::TextureHandle tex_info{ 351 Texture::TextureHandle tex_handle{
315 Memory::Read32(memory_manager.PhysicalToVirtualAddress(current_texture))}; 352 Memory::Read32(memory_manager.PhysicalToVirtualAddress(current_texture))};
316 353
317 if (tex_info.tic_id != 0 || tex_info.tsc_id != 0) { 354 Texture::FullTextureInfo tex_info{};
318 GPUVAddr tic_address_gpu = 355 // TODO(Subv): Use the shader to determine which textures are actually accessed.
319 tic_base_address + tex_info.tic_id * sizeof(Texture::TICEntry); 356 tex_info.index = (current_texture - tex_info_buffer.address - TextureInfoOffset) /
320 VAddr tic_address_cpu = memory_manager.PhysicalToVirtualAddress(tic_address_gpu); 357 sizeof(Texture::TextureHandle);
321 358
322 Texture::TICEntry tic_entry; 359 // Load the TIC data.
323 Memory::ReadBlock(tic_address_cpu, &tic_entry, sizeof(Texture::TICEntry)); 360 if (tex_handle.tic_id != 0) {
361 tex_info.enabled = true;
324 362
325 auto r_type = tic_entry.r_type.Value(); 363 auto tic_entry = GetTICEntry(tex_handle.tic_id);
326 auto g_type = tic_entry.g_type.Value(); 364 // TODO(Subv): Workaround for BitField's move constructor being deleted.
327 auto b_type = tic_entry.b_type.Value(); 365 std::memcpy(&tex_info.tic, &tic_entry, sizeof(tic_entry));
328 auto a_type = tic_entry.a_type.Value(); 366 }
329
330 // TODO(Subv): Different data types for separate components are not supported
331 ASSERT(r_type == g_type && r_type == b_type && r_type == a_type);
332
333 auto format = tic_entry.format.Value();
334 367
335 textures.push_back(tic_entry); 368 // Load the TSC data
369 if (tex_handle.tsc_id != 0) {
370 auto tsc_entry = GetTSCEntry(tex_handle.tsc_id);
371 // TODO(Subv): Workaround for BitField's move constructor being deleted.
372 std::memcpy(&tex_info.tsc, &tsc_entry, sizeof(tsc_entry));
336 } 373 }
374
375 if (tex_info.enabled)
376 textures.push_back(tex_info);
337 } 377 }
338 378
339 return textures; 379 return textures;
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index 441cc0c19..8e2d888e7 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -432,7 +432,7 @@ public:
432 void SubmitMacroCode(u32 entry, std::vector<u32> code); 432 void SubmitMacroCode(u32 entry, std::vector<u32> code);
433 433
434 /// Returns a list of enabled textures for the specified shader stage. 434 /// Returns a list of enabled textures for the specified shader stage.
435 std::vector<Texture::TICEntry> GetStageTextures(Regs::ShaderStage stage); 435 std::vector<Texture::FullTextureInfo> GetStageTextures(Regs::ShaderStage stage) const;
436 436
437private: 437private:
438 MemoryManager& memory_manager; 438 MemoryManager& memory_manager;
@@ -444,6 +444,12 @@ private:
444 /// Parameters that have been submitted to the macro call so far. 444 /// Parameters that have been submitted to the macro call so far.
445 std::vector<u32> macro_params; 445 std::vector<u32> macro_params;
446 446
447 /// Retrieves information about a specific TIC entry from the TIC buffer.
448 Texture::TICEntry GetTICEntry(u32 tic_index) const;
449
450 /// Retrieves information about a specific TSC entry from the TSC buffer.
451 Texture::TSCEntry GetTSCEntry(u32 tsc_index) const;
452
447 /** 453 /**
448 * Call a macro on this engine. 454 * Call a macro on this engine.
449 * @param method Method to call 455 * @param method Method to call
diff --git a/src/video_core/textures/texture.h b/src/video_core/textures/texture.h
index d969bcdd9..07936f8a3 100644
--- a/src/video_core/textures/texture.h
+++ b/src/video_core/textures/texture.h
@@ -17,11 +17,32 @@ enum class TextureFormat : u32 {
17 DXT1 = 0x24, 17 DXT1 = 0x24,
18}; 18};
19 19
20enum class TextureType : u32 {
21 Texture1D = 0,
22 Texture2D = 1,
23 Texture3D = 2,
24 TextureCubemap = 3,
25 Texture1DArray = 4,
26 Texture2DArray = 5,
27 Texture1DBuffer = 6,
28 Texture2DNoMipmap = 7,
29 TextureCubeArray = 8,
30};
31
32enum class TICHeaderVersion : u32 {
33 OneDBuffer = 0,
34 PitchColorKey = 1,
35 Pitch = 2,
36 BlockLinear = 3,
37 BlockLinearColorKey = 4,
38};
39
20union TextureHandle { 40union TextureHandle {
21 u32 raw; 41 u32 raw;
22 BitField<0, 20, u32> tic_id; 42 BitField<0, 20, u32> tic_id;
23 BitField<20, 12, u32> tsc_id; 43 BitField<20, 12, u32> tsc_id;
24}; 44};
45static_assert(sizeof(TextureHandle) == 4, "TextureHandle has wrong size");
25 46
26struct TICEntry { 47struct TICEntry {
27 union { 48 union {
@@ -33,10 +54,15 @@ struct TICEntry {
33 BitField<16, 3, u32> a_type; 54 BitField<16, 3, u32> a_type;
34 }; 55 };
35 u32 address_low; 56 u32 address_low;
36 u16 address_high; 57 union {
37 INSERT_PADDING_BYTES(6); 58 BitField<0, 16, u32> address_high;
38 u16 width_minus_1; 59 BitField<21, 3, TICHeaderVersion> header_version;
39 INSERT_PADDING_BYTES(2); 60 };
61 INSERT_PADDING_BYTES(4);
62 union {
63 BitField<0, 16, u32> width_minus_1;
64 BitField<23, 4, TextureType> texture_type;
65 };
40 u16 height_minus_1; 66 u16 height_minus_1;
41 INSERT_PADDING_BYTES(10); 67 INSERT_PADDING_BYTES(10);
42 68
@@ -54,6 +80,56 @@ struct TICEntry {
54}; 80};
55static_assert(sizeof(TICEntry) == 0x20, "TICEntry has wrong size"); 81static_assert(sizeof(TICEntry) == 0x20, "TICEntry has wrong size");
56 82
83enum class WrapMode : u32 {
84 Wrap = 0,
85 Mirror = 1,
86 ClampToEdge = 2,
87 Border = 3,
88 ClampOGL = 4,
89 MirrorOnceClampToEdge = 5,
90 MirrorOnceBorder = 6,
91 MirrorOnceClampOGL = 7,
92};
93
94enum class TextureFilter : u32 {
95 Nearest = 1,
96 Linear = 2,
97};
98
99enum class TextureMipmapFilter : u32 {
100 None = 1,
101 Nearest = 2,
102 Linear = 3,
103};
104
105struct TSCEntry {
106 union {
107 BitField<0, 3, WrapMode> wrap_u;
108 BitField<3, 3, WrapMode> wrap_v;
109 BitField<6, 3, WrapMode> wrap_p;
110 BitField<9, 1, u32> depth_compare_enabled;
111 BitField<10, 3, u32> depth_compare_func;
112 };
113 union {
114 BitField<0, 2, TextureFilter> mag_filter;
115 BitField<4, 2, TextureFilter> min_filter;
116 BitField<6, 2, TextureMipmapFilter> mip_filter;
117 };
118 INSERT_PADDING_BYTES(8);
119 u32 border_color_r;
120 u32 border_color_g;
121 u32 border_color_b;
122 u32 border_color_a;
123};
124static_assert(sizeof(TSCEntry) == 0x20, "TSCEntry has wrong size");
125
126struct FullTextureInfo {
127 u32 index;
128 TICEntry tic;
129 TSCEntry tsc;
130 bool enabled;
131};
132
57/// Returns the number of bytes per pixel of the input texture format. 133/// Returns the number of bytes per pixel of the input texture format.
58u32 BytesPerPixel(TextureFormat format); 134u32 BytesPerPixel(TextureFormat format);
59 135