diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/core/arm/interpreter/armemu.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp index b9ac8b9ad..522f9a1dd 100644 --- a/src/core/arm/interpreter/armemu.cpp +++ b/src/core/arm/interpreter/armemu.cpp | |||
| @@ -6084,7 +6084,7 @@ L_stm_s_takeabort: | |||
| 6084 | break; | 6084 | break; |
| 6085 | } | 6085 | } |
| 6086 | 6086 | ||
| 6087 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF; | 6087 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF); |
| 6088 | if (Rm & 0x80) | 6088 | if (Rm & 0x80) |
| 6089 | Rm |= 0xffffff00; | 6089 | Rm |= 0xffffff00; |
| 6090 | 6090 | ||
| @@ -6129,7 +6129,7 @@ L_stm_s_takeabort: | |||
| 6129 | if (ror == -1) | 6129 | if (ror == -1) |
| 6130 | break; | 6130 | break; |
| 6131 | 6131 | ||
| 6132 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF; | 6132 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF); |
| 6133 | if (Rm & 0x8000) | 6133 | if (Rm & 0x8000) |
| 6134 | Rm |= 0xffff0000; | 6134 | Rm |= 0xffff0000; |
| 6135 | 6135 | ||
| @@ -6216,7 +6216,7 @@ L_stm_s_takeabort: | |||
| 6216 | break; | 6216 | break; |
| 6217 | } | 6217 | } |
| 6218 | 6218 | ||
| 6219 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF; | 6219 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF); |
| 6220 | 6220 | ||
| 6221 | if (BITS(16, 19) == 0xf) | 6221 | if (BITS(16, 19) == 0xf) |
| 6222 | /* UXTB */ | 6222 | /* UXTB */ |
| @@ -6260,7 +6260,7 @@ L_stm_s_takeabort: | |||
| 6260 | if (ror == -1) | 6260 | if (ror == -1) |
| 6261 | break; | 6261 | break; |
| 6262 | 6262 | ||
| 6263 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF; | 6263 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF); |
| 6264 | 6264 | ||
| 6265 | /* UXT */ | 6265 | /* UXT */ |
| 6266 | /* state->Reg[BITS (12, 15)] = Rm; */ | 6266 | /* state->Reg[BITS (12, 15)] = Rm; */ |