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-rw-r--r--src/core/arm/interpreter/armsupp.cpp2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/interpreter/armsupp.cpp
index 15c6f595b..1b078dc71 100644
--- a/src/core/arm/interpreter/armsupp.cpp
+++ b/src/core/arm/interpreter/armsupp.cpp
@@ -454,8 +454,6 @@ void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 c
454 } 454 }
455 else if (crn == 7 && opcode_1 == 0) 455 else if (crn == 7 && opcode_1 == 0)
456 { 456 {
457 LOG_WARNING(Core_ARM11, "Cache operations are not fully implemented.");
458
459 if (crm == 0 && opcode_2 == 4) 457 if (crm == 0 && opcode_2 == 4)
460 { 458 {
461 cpu->CP15[CP15_WAIT_FOR_INTERRUPT] = value; 459 cpu->CP15[CP15_WAIT_FOR_INTERRUPT] = value;