diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/core/arm/interpreter/armemu.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp index 07d205755..56040a4eb 100644 --- a/src/core/arm/interpreter/armemu.cpp +++ b/src/core/arm/interpreter/armemu.cpp | |||
| @@ -6109,7 +6109,7 @@ L_stm_s_takeabort: | |||
| 6109 | break; | 6109 | break; |
| 6110 | } | 6110 | } |
| 6111 | 6111 | ||
| 6112 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF; | 6112 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF); |
| 6113 | if (Rm & 0x80) | 6113 | if (Rm & 0x80) |
| 6114 | Rm |= 0xffffff00; | 6114 | Rm |= 0xffffff00; |
| 6115 | 6115 | ||
| @@ -6154,7 +6154,7 @@ L_stm_s_takeabort: | |||
| 6154 | if (ror == -1) | 6154 | if (ror == -1) |
| 6155 | break; | 6155 | break; |
| 6156 | 6156 | ||
| 6157 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF; | 6157 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF); |
| 6158 | if (Rm & 0x8000) | 6158 | if (Rm & 0x8000) |
| 6159 | Rm |= 0xffff0000; | 6159 | Rm |= 0xffff0000; |
| 6160 | 6160 | ||
| @@ -6250,7 +6250,7 @@ L_stm_s_takeabort: | |||
| 6250 | break; | 6250 | break; |
| 6251 | } | 6251 | } |
| 6252 | 6252 | ||
| 6253 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF; | 6253 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF); |
| 6254 | 6254 | ||
| 6255 | if (BITS(16, 19) == 0xf) | 6255 | if (BITS(16, 19) == 0xf) |
| 6256 | /* UXTB */ | 6256 | /* UXTB */ |
| @@ -6294,7 +6294,7 @@ L_stm_s_takeabort: | |||
| 6294 | if (ror == -1) | 6294 | if (ror == -1) |
| 6295 | break; | 6295 | break; |
| 6296 | 6296 | ||
| 6297 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF; | 6297 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF); |
| 6298 | 6298 | ||
| 6299 | /* UXT */ | 6299 | /* UXT */ |
| 6300 | /* state->Reg[BITS (12, 15)] = Rm; */ | 6300 | /* state->Reg[BITS (12, 15)] = Rm; */ |