diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/common/settings.h | 2 | ||||
| -rw-r--r-- | src/core/core.cpp | 8 | ||||
| -rw-r--r-- | src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp | 21 | ||||
| -rw-r--r-- | src/core/hle/service/nvdrv/devices/nvhost_gpu.h | 3 | ||||
| -rw-r--r-- | src/video_core/control/channel_state.cpp | 3 | ||||
| -rw-r--r-- | src/video_core/control/channel_state.h | 3 | ||||
| -rw-r--r-- | src/video_core/control/channel_state_cache.cpp | 2 | ||||
| -rw-r--r-- | src/video_core/control/channel_state_cache.h | 8 | ||||
| -rw-r--r-- | src/video_core/control/channel_state_cache.inc | 2 | ||||
| -rw-r--r-- | src/video_core/gpu.cpp | 8 | ||||
| -rw-r--r-- | src/video_core/gpu.h | 2 | ||||
| -rw-r--r-- | src/video_core/renderer_vulkan/vk_rasterizer.cpp | 29 |
12 files changed, 39 insertions, 52 deletions
diff --git a/src/common/settings.h b/src/common/settings.h index b2b071e7e..fa2d08da1 100644 --- a/src/common/settings.h +++ b/src/common/settings.h | |||
| @@ -435,8 +435,6 @@ struct Values { | |||
| 435 | linkage, false, "disable_shader_loop_safety_checks", Category::RendererDebug}; | 435 | linkage, false, "disable_shader_loop_safety_checks", Category::RendererDebug}; |
| 436 | Setting<bool> enable_renderdoc_hotkey{linkage, false, "renderdoc_hotkey", | 436 | Setting<bool> enable_renderdoc_hotkey{linkage, false, "renderdoc_hotkey", |
| 437 | Category::RendererDebug}; | 437 | Category::RendererDebug}; |
| 438 | // TODO: remove this once AMDVLK supports VK_EXT_depth_bias_control | ||
| 439 | bool renderer_amdvlk_depth_bias_workaround{}; | ||
| 440 | Setting<bool> disable_buffer_reorder{linkage, false, "disable_buffer_reorder", | 438 | Setting<bool> disable_buffer_reorder{linkage, false, "disable_buffer_reorder", |
| 441 | Category::RendererDebug}; | 439 | Category::RendererDebug}; |
| 442 | 440 | ||
diff --git a/src/core/core.cpp b/src/core/core.cpp index 9e8936728..dc515bc82 100644 --- a/src/core/core.cpp +++ b/src/core/core.cpp | |||
| @@ -425,11 +425,6 @@ struct System::Impl { | |||
| 425 | room_member->SendGameInfo(game_info); | 425 | room_member->SendGameInfo(game_info); |
| 426 | } | 426 | } |
| 427 | 427 | ||
| 428 | // Workarounds: | ||
| 429 | // Activate this in Super Smash Brothers Ultimate, it only affects AMD cards using AMDVLK | ||
| 430 | Settings::values.renderer_amdvlk_depth_bias_workaround = | ||
| 431 | params.program_id == 0x1006A800016E000ULL; | ||
| 432 | |||
| 433 | status = SystemResultStatus::Success; | 428 | status = SystemResultStatus::Success; |
| 434 | return status; | 429 | return status; |
| 435 | } | 430 | } |
| @@ -489,9 +484,6 @@ struct System::Impl { | |||
| 489 | room_member->SendGameInfo(game_info); | 484 | room_member->SendGameInfo(game_info); |
| 490 | } | 485 | } |
| 491 | 486 | ||
| 492 | // Workarounds | ||
| 493 | Settings::values.renderer_amdvlk_depth_bias_workaround = false; | ||
| 494 | |||
| 495 | LOG_DEBUG(Core, "Shutdown OK"); | 487 | LOG_DEBUG(Core, "Shutdown OK"); |
| 496 | } | 488 | } |
| 497 | 489 | ||
diff --git a/src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp b/src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp index bf12d69a5..efc9cca1c 100644 --- a/src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp +++ b/src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp | |||
| @@ -5,6 +5,7 @@ | |||
| 5 | #include "common/assert.h" | 5 | #include "common/assert.h" |
| 6 | #include "common/logging/log.h" | 6 | #include "common/logging/log.h" |
| 7 | #include "core/core.h" | 7 | #include "core/core.h" |
| 8 | #include "core/hle/kernel/k_process.h" | ||
| 8 | #include "core/hle/service/nvdrv/core/container.h" | 9 | #include "core/hle/service/nvdrv/core/container.h" |
| 9 | #include "core/hle/service/nvdrv/core/nvmap.h" | 10 | #include "core/hle/service/nvdrv/core/nvmap.h" |
| 10 | #include "core/hle/service/nvdrv/core/syncpoint_manager.h" | 11 | #include "core/hle/service/nvdrv/core/syncpoint_manager.h" |
| @@ -75,7 +76,7 @@ NvResult nvhost_gpu::Ioctl1(DeviceFD fd, Ioctl command, std::span<const u8> inpu | |||
| 75 | case 0xd: | 76 | case 0xd: |
| 76 | return WrapFixed(this, &nvhost_gpu::SetChannelPriority, input, output); | 77 | return WrapFixed(this, &nvhost_gpu::SetChannelPriority, input, output); |
| 77 | case 0x1a: | 78 | case 0x1a: |
| 78 | return WrapFixed(this, &nvhost_gpu::AllocGPFIFOEx2, input, output); | 79 | return WrapFixed(this, &nvhost_gpu::AllocGPFIFOEx2, input, output, fd); |
| 79 | case 0x1b: | 80 | case 0x1b: |
| 80 | return WrapFixedVariable(this, &nvhost_gpu::SubmitGPFIFOBase1, input, output, true); | 81 | return WrapFixedVariable(this, &nvhost_gpu::SubmitGPFIFOBase1, input, output, true); |
| 81 | case 0x1d: | 82 | case 0x1d: |
| @@ -120,8 +121,13 @@ NvResult nvhost_gpu::Ioctl3(DeviceFD fd, Ioctl command, std::span<const u8> inpu | |||
| 120 | return NvResult::NotImplemented; | 121 | return NvResult::NotImplemented; |
| 121 | } | 122 | } |
| 122 | 123 | ||
| 123 | void nvhost_gpu::OnOpen(NvCore::SessionId session_id, DeviceFD fd) {} | 124 | void nvhost_gpu::OnOpen(NvCore::SessionId session_id, DeviceFD fd) { |
| 124 | void nvhost_gpu::OnClose(DeviceFD fd) {} | 125 | sessions[fd] = session_id; |
| 126 | } | ||
| 127 | |||
| 128 | void nvhost_gpu::OnClose(DeviceFD fd) { | ||
| 129 | sessions.erase(fd); | ||
| 130 | } | ||
| 125 | 131 | ||
| 126 | NvResult nvhost_gpu::SetNVMAPfd(IoctlSetNvmapFD& params) { | 132 | NvResult nvhost_gpu::SetNVMAPfd(IoctlSetNvmapFD& params) { |
| 127 | LOG_DEBUG(Service_NVDRV, "called, fd={}", params.nvmap_fd); | 133 | LOG_DEBUG(Service_NVDRV, "called, fd={}", params.nvmap_fd); |
| @@ -161,7 +167,7 @@ NvResult nvhost_gpu::SetChannelPriority(IoctlChannelSetPriority& params) { | |||
| 161 | return NvResult::Success; | 167 | return NvResult::Success; |
| 162 | } | 168 | } |
| 163 | 169 | ||
| 164 | NvResult nvhost_gpu::AllocGPFIFOEx2(IoctlAllocGpfifoEx2& params) { | 170 | NvResult nvhost_gpu::AllocGPFIFOEx2(IoctlAllocGpfifoEx2& params, DeviceFD fd) { |
| 165 | LOG_WARNING(Service_NVDRV, | 171 | LOG_WARNING(Service_NVDRV, |
| 166 | "(STUBBED) called, num_entries={:X}, flags={:X}, unk0={:X}, " | 172 | "(STUBBED) called, num_entries={:X}, flags={:X}, unk0={:X}, " |
| 167 | "unk1={:X}, unk2={:X}, unk3={:X}", | 173 | "unk1={:X}, unk2={:X}, unk3={:X}", |
| @@ -173,7 +179,12 @@ NvResult nvhost_gpu::AllocGPFIFOEx2(IoctlAllocGpfifoEx2& params) { | |||
| 173 | return NvResult::AlreadyAllocated; | 179 | return NvResult::AlreadyAllocated; |
| 174 | } | 180 | } |
| 175 | 181 | ||
| 176 | system.GPU().InitChannel(*channel_state); | 182 | u64 program_id{}; |
| 183 | if (auto* const session = core.GetSession(sessions[fd]); session != nullptr) { | ||
| 184 | program_id = session->process->GetProgramId(); | ||
| 185 | } | ||
| 186 | |||
| 187 | system.GPU().InitChannel(*channel_state, program_id); | ||
| 177 | 188 | ||
| 178 | params.fence_out = syncpoint_manager.GetSyncpointFence(channel_syncpoint); | 189 | params.fence_out = syncpoint_manager.GetSyncpointFence(channel_syncpoint); |
| 179 | 190 | ||
diff --git a/src/core/hle/service/nvdrv/devices/nvhost_gpu.h b/src/core/hle/service/nvdrv/devices/nvhost_gpu.h index e34a978db..e0aeef953 100644 --- a/src/core/hle/service/nvdrv/devices/nvhost_gpu.h +++ b/src/core/hle/service/nvdrv/devices/nvhost_gpu.h | |||
| @@ -192,7 +192,7 @@ private: | |||
| 192 | NvResult ZCullBind(IoctlZCullBind& params); | 192 | NvResult ZCullBind(IoctlZCullBind& params); |
| 193 | NvResult SetErrorNotifier(IoctlSetErrorNotifier& params); | 193 | NvResult SetErrorNotifier(IoctlSetErrorNotifier& params); |
| 194 | NvResult SetChannelPriority(IoctlChannelSetPriority& params); | 194 | NvResult SetChannelPriority(IoctlChannelSetPriority& params); |
| 195 | NvResult AllocGPFIFOEx2(IoctlAllocGpfifoEx2& params); | 195 | NvResult AllocGPFIFOEx2(IoctlAllocGpfifoEx2& params, DeviceFD fd); |
| 196 | NvResult AllocateObjectContext(IoctlAllocObjCtx& params); | 196 | NvResult AllocateObjectContext(IoctlAllocObjCtx& params); |
| 197 | 197 | ||
| 198 | NvResult SubmitGPFIFOImpl(IoctlSubmitGpfifo& params, Tegra::CommandList&& entries); | 198 | NvResult SubmitGPFIFOImpl(IoctlSubmitGpfifo& params, Tegra::CommandList&& entries); |
| @@ -210,6 +210,7 @@ private: | |||
| 210 | NvCore::SyncpointManager& syncpoint_manager; | 210 | NvCore::SyncpointManager& syncpoint_manager; |
| 211 | NvCore::NvMap& nvmap; | 211 | NvCore::NvMap& nvmap; |
| 212 | std::shared_ptr<Tegra::Control::ChannelState> channel_state; | 212 | std::shared_ptr<Tegra::Control::ChannelState> channel_state; |
| 213 | std::unordered_map<DeviceFD, NvCore::SessionId> sessions; | ||
| 213 | u32 channel_syncpoint; | 214 | u32 channel_syncpoint; |
| 214 | std::mutex channel_mutex; | 215 | std::mutex channel_mutex; |
| 215 | 216 | ||
diff --git a/src/video_core/control/channel_state.cpp b/src/video_core/control/channel_state.cpp index 832025d75..2539997d5 100644 --- a/src/video_core/control/channel_state.cpp +++ b/src/video_core/control/channel_state.cpp | |||
| @@ -16,8 +16,9 @@ namespace Tegra::Control { | |||
| 16 | 16 | ||
| 17 | ChannelState::ChannelState(s32 bind_id_) : bind_id{bind_id_}, initialized{} {} | 17 | ChannelState::ChannelState(s32 bind_id_) : bind_id{bind_id_}, initialized{} {} |
| 18 | 18 | ||
| 19 | void ChannelState::Init(Core::System& system, GPU& gpu) { | 19 | void ChannelState::Init(Core::System& system, GPU& gpu, u64 program_id_) { |
| 20 | ASSERT(memory_manager); | 20 | ASSERT(memory_manager); |
| 21 | program_id = program_id_; | ||
| 21 | dma_pusher = std::make_unique<Tegra::DmaPusher>(system, gpu, *memory_manager, *this); | 22 | dma_pusher = std::make_unique<Tegra::DmaPusher>(system, gpu, *memory_manager, *this); |
| 22 | maxwell_3d = std::make_unique<Engines::Maxwell3D>(system, *memory_manager); | 23 | maxwell_3d = std::make_unique<Engines::Maxwell3D>(system, *memory_manager); |
| 23 | fermi_2d = std::make_unique<Engines::Fermi2D>(*memory_manager); | 24 | fermi_2d = std::make_unique<Engines::Fermi2D>(*memory_manager); |
diff --git a/src/video_core/control/channel_state.h b/src/video_core/control/channel_state.h index 3a7b9872c..b385f4939 100644 --- a/src/video_core/control/channel_state.h +++ b/src/video_core/control/channel_state.h | |||
| @@ -40,11 +40,12 @@ struct ChannelState { | |||
| 40 | ChannelState(ChannelState&& other) noexcept = default; | 40 | ChannelState(ChannelState&& other) noexcept = default; |
| 41 | ChannelState& operator=(ChannelState&& other) noexcept = default; | 41 | ChannelState& operator=(ChannelState&& other) noexcept = default; |
| 42 | 42 | ||
| 43 | void Init(Core::System& system, GPU& gpu); | 43 | void Init(Core::System& system, GPU& gpu, u64 program_id); |
| 44 | 44 | ||
| 45 | void BindRasterizer(VideoCore::RasterizerInterface* rasterizer); | 45 | void BindRasterizer(VideoCore::RasterizerInterface* rasterizer); |
| 46 | 46 | ||
| 47 | s32 bind_id = -1; | 47 | s32 bind_id = -1; |
| 48 | u64 program_id = 0; | ||
| 48 | /// 3D engine | 49 | /// 3D engine |
| 49 | std::unique_ptr<Engines::Maxwell3D> maxwell_3d; | 50 | std::unique_ptr<Engines::Maxwell3D> maxwell_3d; |
| 50 | /// 2D engine | 51 | /// 2D engine |
diff --git a/src/video_core/control/channel_state_cache.cpp b/src/video_core/control/channel_state_cache.cpp index 4ebeb6356..f8c6a762d 100644 --- a/src/video_core/control/channel_state_cache.cpp +++ b/src/video_core/control/channel_state_cache.cpp | |||
| @@ -7,7 +7,7 @@ namespace VideoCommon { | |||
| 7 | 7 | ||
| 8 | ChannelInfo::ChannelInfo(Tegra::Control::ChannelState& channel_state) | 8 | ChannelInfo::ChannelInfo(Tegra::Control::ChannelState& channel_state) |
| 9 | : maxwell3d{*channel_state.maxwell_3d}, kepler_compute{*channel_state.kepler_compute}, | 9 | : maxwell3d{*channel_state.maxwell_3d}, kepler_compute{*channel_state.kepler_compute}, |
| 10 | gpu_memory{*channel_state.memory_manager} {} | 10 | gpu_memory{*channel_state.memory_manager}, program_id{channel_state.program_id} {} |
| 11 | 11 | ||
| 12 | template class VideoCommon::ChannelSetupCaches<VideoCommon::ChannelInfo>; | 12 | template class VideoCommon::ChannelSetupCaches<VideoCommon::ChannelInfo>; |
| 13 | 13 | ||
diff --git a/src/video_core/control/channel_state_cache.h b/src/video_core/control/channel_state_cache.h index 1dbfda299..7480d60d1 100644 --- a/src/video_core/control/channel_state_cache.h +++ b/src/video_core/control/channel_state_cache.h | |||
| @@ -39,6 +39,7 @@ public: | |||
| 39 | Tegra::Engines::Maxwell3D& maxwell3d; | 39 | Tegra::Engines::Maxwell3D& maxwell3d; |
| 40 | Tegra::Engines::KeplerCompute& kepler_compute; | 40 | Tegra::Engines::KeplerCompute& kepler_compute; |
| 41 | Tegra::MemoryManager& gpu_memory; | 41 | Tegra::MemoryManager& gpu_memory; |
| 42 | u64 program_id; | ||
| 42 | }; | 43 | }; |
| 43 | 44 | ||
| 44 | template <class P> | 45 | template <class P> |
| @@ -77,9 +78,10 @@ protected: | |||
| 77 | P* channel_state; | 78 | P* channel_state; |
| 78 | size_t current_channel_id{UNSET_CHANNEL}; | 79 | size_t current_channel_id{UNSET_CHANNEL}; |
| 79 | size_t current_address_space{}; | 80 | size_t current_address_space{}; |
| 80 | Tegra::Engines::Maxwell3D* maxwell3d; | 81 | Tegra::Engines::Maxwell3D* maxwell3d{}; |
| 81 | Tegra::Engines::KeplerCompute* kepler_compute; | 82 | Tegra::Engines::KeplerCompute* kepler_compute{}; |
| 82 | Tegra::MemoryManager* gpu_memory; | 83 | Tegra::MemoryManager* gpu_memory{}; |
| 84 | u64 program_id{}; | ||
| 83 | 85 | ||
| 84 | std::deque<P> channel_storage; | 86 | std::deque<P> channel_storage; |
| 85 | std::deque<size_t> free_channel_ids; | 87 | std::deque<size_t> free_channel_ids; |
diff --git a/src/video_core/control/channel_state_cache.inc b/src/video_core/control/channel_state_cache.inc index 31f792ddd..d882d8222 100644 --- a/src/video_core/control/channel_state_cache.inc +++ b/src/video_core/control/channel_state_cache.inc | |||
| @@ -58,6 +58,7 @@ void ChannelSetupCaches<P>::BindToChannel(s32 id) { | |||
| 58 | maxwell3d = &channel_state->maxwell3d; | 58 | maxwell3d = &channel_state->maxwell3d; |
| 59 | kepler_compute = &channel_state->kepler_compute; | 59 | kepler_compute = &channel_state->kepler_compute; |
| 60 | gpu_memory = &channel_state->gpu_memory; | 60 | gpu_memory = &channel_state->gpu_memory; |
| 61 | program_id = channel_state->program_id; | ||
| 61 | current_address_space = gpu_memory->GetID(); | 62 | current_address_space = gpu_memory->GetID(); |
| 62 | } | 63 | } |
| 63 | 64 | ||
| @@ -76,6 +77,7 @@ void ChannelSetupCaches<P>::EraseChannel(s32 id) { | |||
| 76 | maxwell3d = nullptr; | 77 | maxwell3d = nullptr; |
| 77 | kepler_compute = nullptr; | 78 | kepler_compute = nullptr; |
| 78 | gpu_memory = nullptr; | 79 | gpu_memory = nullptr; |
| 80 | program_id = 0; | ||
| 79 | } else if (current_channel_id != UNSET_CHANNEL) { | 81 | } else if (current_channel_id != UNSET_CHANNEL) { |
| 80 | channel_state = &channel_storage[current_channel_id]; | 82 | channel_state = &channel_storage[current_channel_id]; |
| 81 | } | 83 | } |
diff --git a/src/video_core/gpu.cpp b/src/video_core/gpu.cpp index 8e663f2a8..6d0b32339 100644 --- a/src/video_core/gpu.cpp +++ b/src/video_core/gpu.cpp | |||
| @@ -67,8 +67,8 @@ struct GPU::Impl { | |||
| 67 | return CreateChannel(new_channel_id++); | 67 | return CreateChannel(new_channel_id++); |
| 68 | } | 68 | } |
| 69 | 69 | ||
| 70 | void InitChannel(Control::ChannelState& to_init) { | 70 | void InitChannel(Control::ChannelState& to_init, u64 program_id) { |
| 71 | to_init.Init(system, gpu); | 71 | to_init.Init(system, gpu, program_id); |
| 72 | to_init.BindRasterizer(rasterizer); | 72 | to_init.BindRasterizer(rasterizer); |
| 73 | rasterizer->InitializeChannel(to_init); | 73 | rasterizer->InitializeChannel(to_init); |
| 74 | } | 74 | } |
| @@ -412,8 +412,8 @@ std::shared_ptr<Control::ChannelState> GPU::AllocateChannel() { | |||
| 412 | return impl->AllocateChannel(); | 412 | return impl->AllocateChannel(); |
| 413 | } | 413 | } |
| 414 | 414 | ||
| 415 | void GPU::InitChannel(Control::ChannelState& to_init) { | 415 | void GPU::InitChannel(Control::ChannelState& to_init, u64 program_id) { |
| 416 | impl->InitChannel(to_init); | 416 | impl->InitChannel(to_init, program_id); |
| 417 | } | 417 | } |
| 418 | 418 | ||
| 419 | void GPU::BindChannel(s32 channel_id) { | 419 | void GPU::BindChannel(s32 channel_id) { |
diff --git a/src/video_core/gpu.h b/src/video_core/gpu.h index ad535512c..50014e51f 100644 --- a/src/video_core/gpu.h +++ b/src/video_core/gpu.h | |||
| @@ -149,7 +149,7 @@ public: | |||
| 149 | 149 | ||
| 150 | std::shared_ptr<Control::ChannelState> AllocateChannel(); | 150 | std::shared_ptr<Control::ChannelState> AllocateChannel(); |
| 151 | 151 | ||
| 152 | void InitChannel(Control::ChannelState& to_init); | 152 | void InitChannel(Control::ChannelState& to_init, u64 program_id); |
| 153 | 153 | ||
| 154 | void BindChannel(s32 channel_id); | 154 | void BindChannel(s32 channel_id); |
| 155 | 155 | ||
diff --git a/src/video_core/renderer_vulkan/vk_rasterizer.cpp b/src/video_core/renderer_vulkan/vk_rasterizer.cpp index 74f9f099e..84955bdc8 100644 --- a/src/video_core/renderer_vulkan/vk_rasterizer.cpp +++ b/src/video_core/renderer_vulkan/vk_rasterizer.cpp | |||
| @@ -1054,37 +1054,16 @@ void RasterizerVulkan::UpdateDepthBias(Tegra::Engines::Maxwell3D::Regs& regs) { | |||
| 1054 | regs.zeta.format == Tegra::DepthFormat::X8Z24_UNORM || | 1054 | regs.zeta.format == Tegra::DepthFormat::X8Z24_UNORM || |
| 1055 | regs.zeta.format == Tegra::DepthFormat::S8Z24_UNORM || | 1055 | regs.zeta.format == Tegra::DepthFormat::S8Z24_UNORM || |
| 1056 | regs.zeta.format == Tegra::DepthFormat::V8Z24_UNORM; | 1056 | regs.zeta.format == Tegra::DepthFormat::V8Z24_UNORM; |
| 1057 | bool force_unorm = ([&] { | 1057 | if (is_d24 && !device.SupportsD24DepthBuffer() && program_id == 0x1006A800016E000ULL) { |
| 1058 | if (!is_d24 || device.SupportsD24DepthBuffer()) { | 1058 | // Only activate this in Super Smash Brothers Ultimate |
| 1059 | return false; | ||
| 1060 | } | ||
| 1061 | if (device.IsExtDepthBiasControlSupported()) { | ||
| 1062 | return true; | ||
| 1063 | } | ||
| 1064 | if (!Settings::values.renderer_amdvlk_depth_bias_workaround) { | ||
| 1065 | return false; | ||
| 1066 | } | ||
| 1067 | // the base formulas can be obtained from here: | 1059 | // the base formulas can be obtained from here: |
| 1068 | // https://docs.microsoft.com/en-us/windows/win32/direct3d11/d3d10-graphics-programming-guide-output-merger-stage-depth-bias | 1060 | // https://docs.microsoft.com/en-us/windows/win32/direct3d11/d3d10-graphics-programming-guide-output-merger-stage-depth-bias |
| 1069 | const double rescale_factor = | 1061 | const double rescale_factor = |
| 1070 | static_cast<double>(1ULL << (32 - 24)) / (static_cast<double>(0x1.ep+127)); | 1062 | static_cast<double>(1ULL << (32 - 24)) / (static_cast<double>(0x1.ep+127)); |
| 1071 | units = static_cast<float>(static_cast<double>(units) * rescale_factor); | 1063 | units = static_cast<float>(static_cast<double>(units) * rescale_factor); |
| 1072 | return false; | 1064 | } |
| 1073 | })(); | ||
| 1074 | scheduler.Record([constant = units, clamp = regs.depth_bias_clamp, | 1065 | scheduler.Record([constant = units, clamp = regs.depth_bias_clamp, |
| 1075 | factor = regs.slope_scale_depth_bias, force_unorm, | 1066 | factor = regs.slope_scale_depth_bias](vk::CommandBuffer cmdbuf) { |
| 1076 | precise = device.HasExactDepthBiasControl()](vk::CommandBuffer cmdbuf) { | ||
| 1077 | if (force_unorm) { | ||
| 1078 | VkDepthBiasRepresentationInfoEXT info{ | ||
| 1079 | .sType = VK_STRUCTURE_TYPE_DEPTH_BIAS_REPRESENTATION_INFO_EXT, | ||
| 1080 | .pNext = nullptr, | ||
| 1081 | .depthBiasRepresentation = | ||
| 1082 | VK_DEPTH_BIAS_REPRESENTATION_LEAST_REPRESENTABLE_VALUE_FORCE_UNORM_EXT, | ||
| 1083 | .depthBiasExact = precise ? VK_TRUE : VK_FALSE, | ||
| 1084 | }; | ||
| 1085 | cmdbuf.SetDepthBias(constant, clamp, factor, &info); | ||
| 1086 | return; | ||
| 1087 | } | ||
| 1088 | cmdbuf.SetDepthBias(constant, clamp, factor); | 1067 | cmdbuf.SetDepthBias(constant, clamp, factor); |
| 1089 | }); | 1068 | }); |
| 1090 | } | 1069 | } |