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-rw-r--r--src/video_core/command_processor.cpp142
1 files changed, 0 insertions, 142 deletions
diff --git a/src/video_core/command_processor.cpp b/src/video_core/command_processor.cpp
deleted file mode 100644
index 8b9c548cc..000000000
--- a/src/video_core/command_processor.cpp
+++ /dev/null
@@ -1,142 +0,0 @@
1// Copyright 2018 yuzu Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#include <array>
6#include <cstddef>
7#include <memory>
8#include <utility>
9#include "common/assert.h"
10#include "common/logging/log.h"
11#include "common/microprofile.h"
12#include "common/vector_math.h"
13#include "core/memory.h"
14#include "core/tracer/recorder.h"
15#include "video_core/command_processor.h"
16#include "video_core/engines/fermi_2d.h"
17#include "video_core/engines/kepler_memory.h"
18#include "video_core/engines/maxwell_3d.h"
19#include "video_core/engines/maxwell_compute.h"
20#include "video_core/engines/maxwell_dma.h"
21#include "video_core/gpu.h"
22#include "video_core/renderer_base.h"
23#include "video_core/video_core.h"
24
25namespace Tegra {
26
27enum class BufferMethods {
28 BindObject = 0,
29 CountBufferMethods = 0x40,
30};
31
32MICROPROFILE_DEFINE(ProcessCommandLists, "GPU", "Execute command buffer", MP_RGB(128, 128, 192));
33
34void GPU::ProcessCommandLists(const std::vector<CommandListHeader>& commands) {
35 MICROPROFILE_SCOPE(ProcessCommandLists);
36
37 // On entering GPU code, assume all memory may be touched by the ARM core.
38 maxwell_3d->dirty_flags.OnMemoryWrite();
39
40 auto WriteReg = [this](u32 method, u32 subchannel, u32 value, u32 remaining_params) {
41 LOG_TRACE(HW_GPU,
42 "Processing method {:08X} on subchannel {} value "
43 "{:08X} remaining params {}",
44 method, subchannel, value, remaining_params);
45
46 ASSERT(subchannel < bound_engines.size());
47
48 if (method == static_cast<u32>(BufferMethods::BindObject)) {
49 // Bind the current subchannel to the desired engine id.
50 LOG_DEBUG(HW_GPU, "Binding subchannel {} to engine {}", subchannel, value);
51 bound_engines[subchannel] = static_cast<EngineID>(value);
52 return;
53 }
54
55 if (method < static_cast<u32>(BufferMethods::CountBufferMethods)) {
56 // TODO(Subv): Research and implement these methods.
57 LOG_ERROR(HW_GPU, "Special buffer methods other than Bind are not implemented");
58 return;
59 }
60
61 const EngineID engine = bound_engines[subchannel];
62
63 switch (engine) {
64 case EngineID::FERMI_TWOD_A:
65 fermi_2d->WriteReg(method, value);
66 break;
67 case EngineID::MAXWELL_B:
68 maxwell_3d->WriteReg(method, value, remaining_params);
69 break;
70 case EngineID::MAXWELL_COMPUTE_B:
71 maxwell_compute->WriteReg(method, value);
72 break;
73 case EngineID::MAXWELL_DMA_COPY_A:
74 maxwell_dma->WriteReg(method, value);
75 break;
76 case EngineID::KEPLER_INLINE_TO_MEMORY_B:
77 kepler_memory->WriteReg(method, value);
78 break;
79 default:
80 UNIMPLEMENTED_MSG("Unimplemented engine");
81 }
82 };
83
84 for (auto entry : commands) {
85 Tegra::GPUVAddr address = entry.Address();
86 u32 size = entry.sz;
87 const std::optional<VAddr> head_address = memory_manager->GpuToCpuAddress(address);
88 VAddr current_addr = *head_address;
89 while (current_addr < *head_address + size * sizeof(CommandHeader)) {
90 const CommandHeader header = {Memory::Read32(current_addr)};
91 current_addr += sizeof(u32);
92
93 switch (header.mode.Value()) {
94 case SubmissionMode::IncreasingOld:
95 case SubmissionMode::Increasing: {
96 // Increase the method value with each argument.
97 for (unsigned i = 0; i < header.arg_count; ++i) {
98 WriteReg(header.method + i, header.subchannel, Memory::Read32(current_addr),
99 header.arg_count - i - 1);
100 current_addr += sizeof(u32);
101 }
102 break;
103 }
104 case SubmissionMode::NonIncreasingOld:
105 case SubmissionMode::NonIncreasing: {
106 // Use the same method value for all arguments.
107 for (unsigned i = 0; i < header.arg_count; ++i) {
108 WriteReg(header.method, header.subchannel, Memory::Read32(current_addr),
109 header.arg_count - i - 1);
110 current_addr += sizeof(u32);
111 }
112 break;
113 }
114 case SubmissionMode::IncreaseOnce: {
115 ASSERT(header.arg_count.Value() >= 1);
116
117 // Use the original method for the first argument and then the next method for all
118 // other arguments.
119 WriteReg(header.method, header.subchannel, Memory::Read32(current_addr),
120 header.arg_count - 1);
121 current_addr += sizeof(u32);
122
123 for (unsigned i = 1; i < header.arg_count; ++i) {
124 WriteReg(header.method + 1, header.subchannel, Memory::Read32(current_addr),
125 header.arg_count - i - 1);
126 current_addr += sizeof(u32);
127 }
128 break;
129 }
130 case SubmissionMode::Inline: {
131 // The register value is stored in the bits 16-28 as an immediate
132 WriteReg(header.method, header.subchannel, header.inline_data, 0);
133 break;
134 }
135 default:
136 UNIMPLEMENTED();
137 }
138 }
139 }
140}
141
142} // namespace Tegra
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