diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 40 |
1 files changed, 33 insertions, 7 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index d0347566c..ffe9d17f9 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp | |||
| @@ -410,10 +410,21 @@ void LnSWoUB(ScaledRegisterPreIndexed)(arm_processor *cpu, unsigned int inst, un | |||
| 410 | } | 410 | } |
| 411 | break; | 411 | break; |
| 412 | case 2: | 412 | case 2: |
| 413 | DEBUG_MSG; | 413 | if (shift_imm == 0) { // ASR #32 |
| 414 | if (BIT(rm, 31) == 1) | ||
| 415 | index = 0xFFFFFFFF; | ||
| 416 | else | ||
| 417 | index = 0; | ||
| 418 | } else { | ||
| 419 | index = static_cast<int>(rm) >> shift_imm; | ||
| 420 | } | ||
| 414 | break; | 421 | break; |
| 415 | case 3: | 422 | case 3: |
| 416 | DEBUG_MSG; | 423 | if (shift_imm == 0) { |
| 424 | index = (cpu->CFlag << 31) | (rm >> 1); | ||
| 425 | } else { | ||
| 426 | index = ROTATE_RIGHT_32(rm, shift_imm); | ||
| 427 | } | ||
| 417 | break; | 428 | break; |
| 418 | } | 429 | } |
| 419 | 430 | ||
| @@ -449,10 +460,21 @@ void LnSWoUB(ScaledRegisterPostIndexed)(arm_processor *cpu, unsigned int inst, u | |||
| 449 | } | 460 | } |
| 450 | break; | 461 | break; |
| 451 | case 2: | 462 | case 2: |
| 452 | DEBUG_MSG; | 463 | if (shift_imm == 0) { // ASR #32 |
| 464 | if (BIT(rm, 31) == 1) | ||
| 465 | index = 0xFFFFFFFF; | ||
| 466 | else | ||
| 467 | index = 0; | ||
| 468 | } else { | ||
| 469 | index = static_cast<int>(rm) >> shift_imm; | ||
| 470 | } | ||
| 453 | break; | 471 | break; |
| 454 | case 3: | 472 | case 3: |
| 455 | DEBUG_MSG; | 473 | if (shift_imm == 0) { |
| 474 | index = (cpu->CFlag << 31) | (rm >> 1); | ||
| 475 | } else { | ||
| 476 | index = ROTATE_RIGHT_32(rm, shift_imm); | ||
| 477 | } | ||
| 456 | break; | 478 | break; |
| 457 | } | 479 | } |
| 458 | 480 | ||
| @@ -654,8 +676,8 @@ void LnSWoUB(ScaledRegisterOffset)(arm_processor *cpu, unsigned int inst, unsign | |||
| 654 | } | 676 | } |
| 655 | break; | 677 | break; |
| 656 | case 2: | 678 | case 2: |
| 657 | if (shift_imm == 0){ // ASR #32 | 679 | if (shift_imm == 0) { // ASR #32 |
| 658 | if (rm >> 31) | 680 | if (BIT(rm, 31) == 1) |
| 659 | index = 0xFFFFFFFF; | 681 | index = 0xFFFFFFFF; |
| 660 | else | 682 | else |
| 661 | index = 0; | 683 | index = 0; |
| @@ -664,7 +686,11 @@ void LnSWoUB(ScaledRegisterOffset)(arm_processor *cpu, unsigned int inst, unsign | |||
| 664 | } | 686 | } |
| 665 | break; | 687 | break; |
| 666 | case 3: | 688 | case 3: |
| 667 | DEBUG_MSG; | 689 | if (shift_imm == 0) { |
| 690 | index = (cpu->CFlag << 31) | (rm >> 1); | ||
| 691 | } else { | ||
| 692 | index = ROTATE_RIGHT_32(rm, shift_imm); | ||
| 693 | } | ||
| 668 | break; | 694 | break; |
| 669 | } | 695 | } |
| 670 | 696 | ||