summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_thumb.cpp14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.cpp b/src/core/arm/dyncom/arm_dyncom_thumb.cpp
index de70ca8ae..d5a698365 100644
--- a/src/core/arm/dyncom/arm_dyncom_thumb.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_thumb.cpp
@@ -48,7 +48,7 @@ tdstate thumb_translate (addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t
48 48
49 case 3: // ADD/SUB 49 case 3: // ADD/SUB
50 { 50 {
51 ARMword subset[4] = { 51 static const ARMword subset[4] = {
52 0xE0900000, // ADDS Rd,Rs,Rn 52 0xE0900000, // ADDS Rd,Rs,Rn
53 0xE0500000, // SUBS Rd,Rs,Rn 53 0xE0500000, // SUBS Rd,Rs,Rn
54 0xE2900000, // ADDS Rd,Rs,#imm3 54 0xE2900000, // ADDS Rd,Rs,#imm3
@@ -67,7 +67,7 @@ tdstate thumb_translate (addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t
67 case 6: // ADD 67 case 6: // ADD
68 case 7: // SUB 68 case 7: // SUB
69 { 69 {
70 ARMword subset[4] = { 70 static const ARMword subset[4] = {
71 0xE3B00000, // MOVS Rd,#imm8 71 0xE3B00000, // MOVS Rd,#imm8
72 0xE3500000, // CMP Rd,#imm8 72 0xE3500000, // CMP Rd,#imm8
73 0xE2900000, // ADDS Rd,Rd,#imm8 73 0xE2900000, // ADDS Rd,Rd,#imm8
@@ -95,7 +95,7 @@ tdstate thumb_translate (addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t
95 t_mul 95 t_mul
96 }; 96 };
97 97
98 struct { 98 static const struct {
99 ARMword opcode; 99 ARMword opcode;
100 otype type; 100 otype type;
101 } subset[16] = { 101 } subset[16] = {
@@ -205,7 +205,7 @@ tdstate thumb_translate (addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t
205 // merged into a single subset, saving on the following boolean: 205 // merged into a single subset, saving on the following boolean:
206 206
207 if ((tinstr & (1 << 9)) == 0) { 207 if ((tinstr & (1 << 9)) == 0) {
208 ARMword subset[4] = { 208 static const ARMword subset[4] = {
209 0xE7800000, // STR Rd,[Rb,Ro] 209 0xE7800000, // STR Rd,[Rb,Ro]
210 0xE7C00000, // STRB Rd,[Rb,Ro] 210 0xE7C00000, // STRB Rd,[Rb,Ro]
211 0xE7900000, // LDR Rd,[Rb,Ro] 211 0xE7900000, // LDR Rd,[Rb,Ro]
@@ -218,7 +218,7 @@ tdstate thumb_translate (addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t
218 |((tinstr & 0x01C0) >> 6); // Ro 218 |((tinstr & 0x01C0) >> 6); // Ro
219 219
220 } else { 220 } else {
221 ARMword subset[4] = { 221 static const ARMword subset[4] = {
222 0xE18000B0, // STRH Rd,[Rb,Ro] 222 0xE18000B0, // STRH Rd,[Rb,Ro]
223 0xE19000D0, // LDRSB Rd,[Rb,Ro] 223 0xE19000D0, // LDRSB Rd,[Rb,Ro]
224 0xE19000B0, // LDRH Rd,[Rb,Ro] 224 0xE19000B0, // LDRH Rd,[Rb,Ro]
@@ -236,7 +236,7 @@ tdstate thumb_translate (addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t
236 case 14: // STRB Rd,[Rb,#imm5] 236 case 14: // STRB Rd,[Rb,#imm5]
237 case 15: // LDRB Rd,[Rb,#imm5] 237 case 15: // LDRB Rd,[Rb,#imm5]
238 { 238 {
239 ARMword subset[4] = { 239 static const ARMword subset[4] = {
240 0xE5800000, // STR Rd,[Rb,#imm5] 240 0xE5800000, // STR Rd,[Rb,#imm5]
241 0xE5900000, // LDR Rd,[Rb,#imm5] 241 0xE5900000, // LDR Rd,[Rb,#imm5]
242 0xE5C00000, // STRB Rd,[Rb,#imm5] 242 0xE5C00000, // STRB Rd,[Rb,#imm5]
@@ -300,7 +300,7 @@ tdstate thumb_translate (addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t
300 } else if ((tinstr & 0x0F00) == 0x0e00) 300 } else if ((tinstr & 0x0F00) == 0x0e00)
301 *ainstr = 0xEF000000 | SWI_Breakpoint; 301 *ainstr = 0xEF000000 | SWI_Breakpoint;
302 else { 302 else {
303 ARMword subset[4] = { 303 static const ARMword subset[4] = {
304 0xE92D0000, // STMDB sp!,{rlist} 304 0xE92D0000, // STMDB sp!,{rlist}
305 0xE92D4000, // STMDB sp!,{rlist,lr} 305 0xE92D4000, // STMDB sp!,{rlist,lr}
306 0xE8BD0000, // LDMIA sp!,{rlist} 306 0xE8BD0000, // LDMIA sp!,{rlist}