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-rw-r--r--src/citra_qt/CMakeLists.txt6
-rw-r--r--src/citra_qt/debugger/callstack.cpp85
-rw-r--r--src/citra_qt/debugger/callstack.h28
-rw-r--r--src/citra_qt/debugger/callstack.ui39
-rw-r--r--src/citra_qt/debugger/disassembler.cpp272
-rw-r--r--src/citra_qt/debugger/disassembler.h76
-rw-r--r--src/citra_qt/debugger/disassembler.ui81
-rw-r--r--src/citra_qt/main.cpp38
-rw-r--r--src/citra_qt/main.h5
-rw-r--r--src/citra_qt/main.ui1
-rw-r--r--src/common/CMakeLists.txt2
-rw-r--r--src/common/symbols.cpp46
-rw-r--r--src/common/symbols.h30
-rw-r--r--src/core/CMakeLists.txt4
-rw-r--r--src/core/arm/disassembler/arm_disasm.cpp1344
-rw-r--r--src/core/arm/disassembler/arm_disasm.h238
-rw-r--r--src/core/arm/disassembler/load_symbol_map.cpp31
-rw-r--r--src/core/arm/disassembler/load_symbol_map.h13
-rw-r--r--src/core/arm/dyncom/arm_dyncom_dec.cpp2
-rw-r--r--src/core/arm/dyncom/arm_dyncom_dec.h2
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp15
-rw-r--r--src/core/hle/svc.cpp10
-rw-r--r--src/core/loader/elf.cpp32
23 files changed, 11 insertions, 2389 deletions
diff --git a/src/citra_qt/CMakeLists.txt b/src/citra_qt/CMakeLists.txt
index 3e6106f0a..4e837668e 100644
--- a/src/citra_qt/CMakeLists.txt
+++ b/src/citra_qt/CMakeLists.txt
@@ -11,8 +11,6 @@ set(SRCS
11 configuration/configure_graphics.cpp 11 configuration/configure_graphics.cpp
12 configuration/configure_input.cpp 12 configuration/configure_input.cpp
13 configuration/configure_system.cpp 13 configuration/configure_system.cpp
14 debugger/callstack.cpp
15 debugger/disassembler.cpp
16 debugger/graphics/graphics.cpp 14 debugger/graphics/graphics.cpp
17 debugger/graphics/graphics_breakpoint_observer.cpp 15 debugger/graphics/graphics_breakpoint_observer.cpp
18 debugger/graphics/graphics_breakpoints.cpp 16 debugger/graphics/graphics_breakpoints.cpp
@@ -43,8 +41,6 @@ set(HEADERS
43 configuration/configure_graphics.h 41 configuration/configure_graphics.h
44 configuration/configure_input.h 42 configuration/configure_input.h
45 configuration/configure_system.h 43 configuration/configure_system.h
46 debugger/callstack.h
47 debugger/disassembler.h
48 debugger/graphics/graphics.h 44 debugger/graphics/graphics.h
49 debugger/graphics/graphics_breakpoint_observer.h 45 debugger/graphics/graphics_breakpoint_observer.h
50 debugger/graphics/graphics_breakpoints.h 46 debugger/graphics/graphics_breakpoints.h
@@ -74,8 +70,6 @@ set(UIS
74 configuration/configure_graphics.ui 70 configuration/configure_graphics.ui
75 configuration/configure_input.ui 71 configuration/configure_input.ui
76 configuration/configure_system.ui 72 configuration/configure_system.ui
77 debugger/callstack.ui
78 debugger/disassembler.ui
79 debugger/registers.ui 73 debugger/registers.ui
80 hotkeys.ui 74 hotkeys.ui
81 main.ui 75 main.ui
diff --git a/src/citra_qt/debugger/callstack.cpp b/src/citra_qt/debugger/callstack.cpp
deleted file mode 100644
index 08d2e7a22..000000000
--- a/src/citra_qt/debugger/callstack.cpp
+++ /dev/null
@@ -1,85 +0,0 @@
1// Copyright 2014 Citra Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#include <QStandardItemModel>
6#include "citra_qt/debugger/callstack.h"
7#include "common/common_types.h"
8#include "common/symbols.h"
9#include "core/arm/arm_interface.h"
10#include "core/arm/disassembler/arm_disasm.h"
11#include "core/core.h"
12#include "core/memory.h"
13
14CallstackWidget::CallstackWidget(QWidget* parent) : QDockWidget(parent) {
15 ui.setupUi(this);
16
17 callstack_model = new QStandardItemModel(this);
18 callstack_model->setColumnCount(4);
19 callstack_model->setHeaderData(0, Qt::Horizontal, "Stack Pointer");
20 callstack_model->setHeaderData(2, Qt::Horizontal, "Return Address");
21 callstack_model->setHeaderData(1, Qt::Horizontal, "Call Address");
22 callstack_model->setHeaderData(3, Qt::Horizontal, "Function");
23 ui.treeView->setModel(callstack_model);
24}
25
26void CallstackWidget::OnDebugModeEntered() {
27 // Stack pointer
28 const u32 sp = Core::CPU().GetReg(13);
29
30 Clear();
31
32 int counter = 0;
33 for (u32 addr = 0x10000000; addr >= sp; addr -= 4) {
34 if (!Memory::IsValidVirtualAddress(addr))
35 break;
36
37 const u32 ret_addr = Memory::Read32(addr);
38 const u32 call_addr = ret_addr - 4; // get call address???
39
40 if (!Memory::IsValidVirtualAddress(call_addr))
41 break;
42
43 /* TODO (mattvail) clean me, move to debugger interface */
44 u32 insn = Memory::Read32(call_addr);
45 if (ARM_Disasm::Decode(insn) == OP_BL) {
46 std::string name;
47 // ripped from disasm
48 u32 i_offset = insn & 0xffffff;
49 // Sign-extend the 24-bit offset
50 if ((i_offset >> 23) & 1)
51 i_offset |= 0xff000000;
52
53 // Pre-compute the left-shift and the prefetch offset
54 i_offset <<= 2;
55 i_offset += 8;
56 const u32 func_addr = call_addr + i_offset;
57
58 callstack_model->setItem(
59 counter, 0, new QStandardItem(QString("0x%1").arg(addr, 8, 16, QLatin1Char('0'))));
60 callstack_model->setItem(counter, 1, new QStandardItem(QString("0x%1").arg(
61 ret_addr, 8, 16, QLatin1Char('0'))));
62 callstack_model->setItem(counter, 2, new QStandardItem(QString("0x%1").arg(
63 call_addr, 8, 16, QLatin1Char('0'))));
64
65 name = Symbols::HasSymbol(func_addr) ? Symbols::GetSymbol(func_addr).name : "unknown";
66 callstack_model->setItem(
67 counter, 3, new QStandardItem(
68 QString("%1_%2")
69 .arg(QString::fromStdString(name))
70 .arg(QString("0x%1").arg(func_addr, 8, 16, QLatin1Char('0')))));
71
72 counter++;
73 }
74 }
75}
76
77void CallstackWidget::OnDebugModeLeft() {}
78
79void CallstackWidget::Clear() {
80 for (int row = 0; row < callstack_model->rowCount(); row++) {
81 for (int column = 0; column < callstack_model->columnCount(); column++) {
82 callstack_model->setItem(row, column, new QStandardItem());
83 }
84 }
85}
diff --git a/src/citra_qt/debugger/callstack.h b/src/citra_qt/debugger/callstack.h
deleted file mode 100644
index f04ab9c7e..000000000
--- a/src/citra_qt/debugger/callstack.h
+++ /dev/null
@@ -1,28 +0,0 @@
1// Copyright 2014 Citra Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#pragma once
6
7#include <QDockWidget>
8#include "ui_callstack.h"
9
10class QStandardItemModel;
11
12class CallstackWidget : public QDockWidget {
13 Q_OBJECT
14
15public:
16 explicit CallstackWidget(QWidget* parent = nullptr);
17
18public slots:
19 void OnDebugModeEntered();
20 void OnDebugModeLeft();
21
22private:
23 Ui::CallStack ui;
24 QStandardItemModel* callstack_model;
25
26 /// Clears the callstack widget while keeping the column widths the same
27 void Clear();
28};
diff --git a/src/citra_qt/debugger/callstack.ui b/src/citra_qt/debugger/callstack.ui
deleted file mode 100644
index 248ea3dd7..000000000
--- a/src/citra_qt/debugger/callstack.ui
+++ /dev/null
@@ -1,39 +0,0 @@
1<?xml version="1.0" encoding="UTF-8"?>
2<ui version="4.0">
3 <class>CallStack</class>
4 <widget class="QDockWidget" name="CallStack">
5 <property name="geometry">
6 <rect>
7 <x>0</x>
8 <y>0</y>
9 <width>400</width>
10 <height>300</height>
11 </rect>
12 </property>
13 <property name="windowTitle">
14 <string>Call Stack</string>
15 </property>
16 <widget class="QWidget" name="dockWidgetContents">
17 <layout class="QVBoxLayout" name="verticalLayout">
18 <item>
19 <widget class="QTreeView" name="treeView">
20 <property name="editTriggers">
21 <set>QAbstractItemView::NoEditTriggers</set>
22 </property>
23 <property name="alternatingRowColors">
24 <bool>true</bool>
25 </property>
26 <property name="rootIsDecorated">
27 <bool>false</bool>
28 </property>
29 <property name="itemsExpandable">
30 <bool>false</bool>
31 </property>
32 </widget>
33 </item>
34 </layout>
35 </widget>
36 </widget>
37 <resources/>
38 <connections/>
39</ui>
diff --git a/src/citra_qt/debugger/disassembler.cpp b/src/citra_qt/debugger/disassembler.cpp
deleted file mode 100644
index e9c8ad858..000000000
--- a/src/citra_qt/debugger/disassembler.cpp
+++ /dev/null
@@ -1,272 +0,0 @@
1// Copyright 2014 Citra Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#include <QShortcut>
6#include "citra_qt/bootmanager.h"
7#include "citra_qt/debugger/disassembler.h"
8#include "citra_qt/hotkeys.h"
9#include "citra_qt/util/util.h"
10#include "common/break_points.h"
11#include "common/symbols.h"
12#include "core/arm/arm_interface.h"
13#include "core/arm/disassembler/arm_disasm.h"
14#include "core/core.h"
15#include "core/memory.h"
16
17DisassemblerModel::DisassemblerModel(QObject* parent)
18 : QAbstractListModel(parent), base_address(0), code_size(0), program_counter(0),
19 selection(QModelIndex()) {}
20
21int DisassemblerModel::columnCount(const QModelIndex& parent) const {
22 return 3;
23}
24
25int DisassemblerModel::rowCount(const QModelIndex& parent) const {
26 return code_size;
27}
28
29QVariant DisassemblerModel::data(const QModelIndex& index, int role) const {
30 switch (role) {
31 case Qt::DisplayRole: {
32 u32 address = base_address + index.row() * 4;
33 u32 instr = Memory::Read32(address);
34 std::string disassembly = ARM_Disasm::Disassemble(address, instr);
35
36 if (index.column() == 0) {
37 return QString("0x%1").arg((uint)(address), 8, 16, QLatin1Char('0'));
38 } else if (index.column() == 1) {
39 return QString::fromStdString(disassembly);
40 } else if (index.column() == 2) {
41 if (Symbols::HasSymbol(address)) {
42 TSymbol symbol = Symbols::GetSymbol(address);
43 return QString("%1 - Size:%2")
44 .arg(QString::fromStdString(symbol.name))
45 .arg(symbol.size / 4); // divide by 4 to get instruction count
46 } else if (ARM_Disasm::Decode(instr) == OP_BL) {
47 u32 offset = instr & 0xFFFFFF;
48
49 // Sign-extend the 24-bit offset
50 if ((offset >> 23) & 1)
51 offset |= 0xFF000000;
52
53 // Pre-compute the left-shift and the prefetch offset
54 offset <<= 2;
55 offset += 8;
56
57 TSymbol symbol = Symbols::GetSymbol(address + offset);
58 return QString(" --> %1").arg(QString::fromStdString(symbol.name));
59 }
60 }
61
62 break;
63 }
64
65 case Qt::BackgroundRole: {
66 unsigned int address = base_address + 4 * index.row();
67
68 if (breakpoints.IsAddressBreakPoint(address))
69 return QBrush(QColor(0xFF, 0xC0, 0xC0));
70 else if (address == program_counter)
71 return QBrush(QColor(0xC0, 0xC0, 0xFF));
72
73 break;
74 }
75
76 case Qt::FontRole: {
77 if (index.column() == 0 || index.column() == 1) { // 2 is the symbols column
78 return GetMonospaceFont();
79 }
80 break;
81 }
82
83 default:
84 break;
85 }
86
87 return QVariant();
88}
89
90QModelIndex DisassemblerModel::IndexFromAbsoluteAddress(unsigned int address) const {
91 return index((address - base_address) / 4, 0);
92}
93
94const BreakPoints& DisassemblerModel::GetBreakPoints() const {
95 return breakpoints;
96}
97
98void DisassemblerModel::ParseFromAddress(unsigned int address) {
99
100 // NOTE: A too large value causes lagging when scrolling the disassembly
101 const unsigned int chunk_size = 1000 * 500;
102
103 // If we haven't loaded anything yet, initialize base address to the parameter address
104 if (code_size == 0)
105 base_address = address;
106
107 // If the new area is already loaded, just continue
108 if (base_address + code_size > address + chunk_size && base_address <= address)
109 return;
110
111 // Insert rows before currently loaded data
112 if (base_address > address) {
113 unsigned int num_rows = (address - base_address) / 4;
114
115 beginInsertRows(QModelIndex(), 0, num_rows);
116 code_size += num_rows;
117 base_address = address;
118
119 endInsertRows();
120 }
121
122 // Insert rows after currently loaded data
123 if (base_address + code_size < address + chunk_size) {
124 unsigned int num_rows = (base_address + chunk_size - code_size - address) / 4;
125
126 beginInsertRows(QModelIndex(), 0, num_rows);
127 code_size += num_rows;
128 endInsertRows();
129 }
130
131 SetNextInstruction(address);
132}
133
134void DisassemblerModel::OnSelectionChanged(const QModelIndex& new_selection) {
135 selection = new_selection;
136}
137
138void DisassemblerModel::OnSetOrUnsetBreakpoint() {
139 if (!selection.isValid())
140 return;
141
142 unsigned int address = base_address + selection.row() * 4;
143
144 if (breakpoints.IsAddressBreakPoint(address)) {
145 breakpoints.Remove(address);
146 } else {
147 breakpoints.Add(address);
148 }
149
150 emit dataChanged(selection, selection);
151}
152
153void DisassemblerModel::SetNextInstruction(unsigned int address) {
154 QModelIndex cur_index = IndexFromAbsoluteAddress(program_counter);
155 QModelIndex prev_index = IndexFromAbsoluteAddress(address);
156
157 program_counter = address;
158
159 emit dataChanged(cur_index, cur_index);
160 emit dataChanged(prev_index, prev_index);
161}
162
163DisassemblerWidget::DisassemblerWidget(QWidget* parent, EmuThread* emu_thread)
164 : QDockWidget(parent), base_addr(0), emu_thread(emu_thread) {
165
166 disasm_ui.setupUi(this);
167
168 RegisterHotkey("Disassembler", "Start/Stop", QKeySequence(Qt::Key_F5), Qt::ApplicationShortcut);
169 RegisterHotkey("Disassembler", "Step", QKeySequence(Qt::Key_F10), Qt::ApplicationShortcut);
170 RegisterHotkey("Disassembler", "Step into", QKeySequence(Qt::Key_F11), Qt::ApplicationShortcut);
171 RegisterHotkey("Disassembler", "Set Breakpoint", QKeySequence(Qt::Key_F9),
172 Qt::ApplicationShortcut);
173
174 connect(disasm_ui.button_step, SIGNAL(clicked()), this, SLOT(OnStep()));
175 connect(disasm_ui.button_pause, SIGNAL(clicked()), this, SLOT(OnPause()));
176 connect(disasm_ui.button_continue, SIGNAL(clicked()), this, SLOT(OnContinue()));
177
178 connect(GetHotkey("Disassembler", "Start/Stop", this), SIGNAL(activated()), this,
179 SLOT(OnToggleStartStop()));
180 connect(GetHotkey("Disassembler", "Step", this), SIGNAL(activated()), this, SLOT(OnStep()));
181 connect(GetHotkey("Disassembler", "Step into", this), SIGNAL(activated()), this,
182 SLOT(OnStepInto()));
183
184 setEnabled(false);
185}
186
187void DisassemblerWidget::Init() {
188 model->ParseFromAddress(Core::CPU().GetPC());
189
190 disasm_ui.treeView->resizeColumnToContents(0);
191 disasm_ui.treeView->resizeColumnToContents(1);
192 disasm_ui.treeView->resizeColumnToContents(2);
193
194 QModelIndex model_index = model->IndexFromAbsoluteAddress(Core::CPU().GetPC());
195 disasm_ui.treeView->scrollTo(model_index);
196 disasm_ui.treeView->selectionModel()->setCurrentIndex(
197 model_index, QItemSelectionModel::SelectCurrent | QItemSelectionModel::Rows);
198}
199
200void DisassemblerWidget::OnContinue() {
201 emu_thread->SetRunning(true);
202}
203
204void DisassemblerWidget::OnStep() {
205 OnStepInto(); // change later
206}
207
208void DisassemblerWidget::OnStepInto() {
209 emu_thread->SetRunning(false);
210 emu_thread->ExecStep();
211}
212
213void DisassemblerWidget::OnPause() {
214 emu_thread->SetRunning(false);
215
216 // TODO: By now, the CPU might not have actually stopped...
217 if (Core::System::GetInstance().IsPoweredOn()) {
218 model->SetNextInstruction(Core::CPU().GetPC());
219 }
220}
221
222void DisassemblerWidget::OnToggleStartStop() {
223 emu_thread->SetRunning(!emu_thread->IsRunning());
224}
225
226void DisassemblerWidget::OnDebugModeEntered() {
227 u32 next_instr = Core::CPU().GetPC();
228
229 if (model->GetBreakPoints().IsAddressBreakPoint(next_instr))
230 emu_thread->SetRunning(false);
231
232 model->SetNextInstruction(next_instr);
233
234 QModelIndex model_index = model->IndexFromAbsoluteAddress(next_instr);
235 disasm_ui.treeView->scrollTo(model_index);
236 disasm_ui.treeView->selectionModel()->setCurrentIndex(
237 model_index, QItemSelectionModel::SelectCurrent | QItemSelectionModel::Rows);
238}
239
240void DisassemblerWidget::OnDebugModeLeft() {}
241
242int DisassemblerWidget::SelectedRow() {
243 QModelIndex index = disasm_ui.treeView->selectionModel()->currentIndex();
244 if (!index.isValid())
245 return -1;
246
247 return disasm_ui.treeView->selectionModel()->currentIndex().row();
248}
249
250void DisassemblerWidget::OnEmulationStarting(EmuThread* emu_thread) {
251 this->emu_thread = emu_thread;
252
253 model = new DisassemblerModel(this);
254 disasm_ui.treeView->setModel(model);
255
256 connect(disasm_ui.treeView->selectionModel(),
257 SIGNAL(currentChanged(const QModelIndex&, const QModelIndex&)), model,
258 SLOT(OnSelectionChanged(const QModelIndex&)));
259 connect(disasm_ui.button_breakpoint, SIGNAL(clicked()), model, SLOT(OnSetOrUnsetBreakpoint()));
260 connect(GetHotkey("Disassembler", "Set Breakpoint", this), SIGNAL(activated()), model,
261 SLOT(OnSetOrUnsetBreakpoint()));
262
263 Init();
264 setEnabled(true);
265}
266
267void DisassemblerWidget::OnEmulationStopping() {
268 disasm_ui.treeView->setModel(nullptr);
269 delete model;
270 emu_thread = nullptr;
271 setEnabled(false);
272}
diff --git a/src/citra_qt/debugger/disassembler.h b/src/citra_qt/debugger/disassembler.h
deleted file mode 100644
index a6e59515c..000000000
--- a/src/citra_qt/debugger/disassembler.h
+++ /dev/null
@@ -1,76 +0,0 @@
1// Copyright 2014 Citra Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#pragma once
6
7#include <QAbstractListModel>
8#include <QDockWidget>
9#include "common/break_points.h"
10#include "common/common_types.h"
11#include "ui_disassembler.h"
12
13class QAction;
14class EmuThread;
15
16class DisassemblerModel : public QAbstractListModel {
17 Q_OBJECT
18
19public:
20 explicit DisassemblerModel(QObject* parent);
21
22 int columnCount(const QModelIndex& parent = QModelIndex()) const override;
23 int rowCount(const QModelIndex& parent = QModelIndex()) const override;
24 QVariant data(const QModelIndex& index, int role = Qt::DisplayRole) const override;
25
26 QModelIndex IndexFromAbsoluteAddress(unsigned int address) const;
27 const BreakPoints& GetBreakPoints() const;
28
29public slots:
30 void ParseFromAddress(unsigned int address);
31 void OnSelectionChanged(const QModelIndex&);
32 void OnSetOrUnsetBreakpoint();
33 void SetNextInstruction(unsigned int address);
34
35private:
36 unsigned int base_address;
37 unsigned int code_size;
38 unsigned int program_counter;
39
40 QModelIndex selection;
41 BreakPoints breakpoints;
42};
43
44class DisassemblerWidget : public QDockWidget {
45 Q_OBJECT
46
47public:
48 DisassemblerWidget(QWidget* parent, EmuThread* emu_thread);
49
50 void Init();
51
52public slots:
53 void OnContinue();
54 void OnStep();
55 void OnStepInto();
56 void OnPause();
57 void OnToggleStartStop();
58
59 void OnDebugModeEntered();
60 void OnDebugModeLeft();
61
62 void OnEmulationStarting(EmuThread* emu_thread);
63 void OnEmulationStopping();
64
65private:
66 // returns -1 if no row is selected
67 int SelectedRow();
68
69 Ui::DockWidget disasm_ui;
70
71 DisassemblerModel* model;
72
73 u32 base_addr;
74
75 EmuThread* emu_thread;
76};
diff --git a/src/citra_qt/debugger/disassembler.ui b/src/citra_qt/debugger/disassembler.ui
deleted file mode 100644
index 5ca6dc5d2..000000000
--- a/src/citra_qt/debugger/disassembler.ui
+++ /dev/null
@@ -1,81 +0,0 @@
1<?xml version="1.0" encoding="UTF-8"?>
2<ui version="4.0">
3 <class>DockWidget</class>
4 <widget class="QDockWidget" name="DockWidget">
5 <property name="geometry">
6 <rect>
7 <x>0</x>
8 <y>0</y>
9 <width>430</width>
10 <height>401</height>
11 </rect>
12 </property>
13 <property name="windowTitle">
14 <string>Disassembly</string>
15 </property>
16 <widget class="QWidget" name="dockWidgetContents">
17 <layout class="QVBoxLayout" name="verticalLayout">
18 <item>
19 <layout class="QHBoxLayout" name="horizontalLayout">
20 <item>
21 <widget class="QPushButton" name="button_step">
22 <property name="text">
23 <string>Step</string>
24 </property>
25 </widget>
26 </item>
27 <item>
28 <widget class="QPushButton" name="button_pause">
29 <property name="text">
30 <string>Pause</string>
31 </property>
32 </widget>
33 </item>
34 <item>
35 <widget class="QPushButton" name="button_continue">
36 <property name="text">
37 <string>Continue</string>
38 </property>
39 </widget>
40 </item>
41 <item>
42 <widget class="QPushButton" name="pushButton">
43 <property name="text">
44 <string>Step Into</string>
45 </property>
46 </widget>
47 </item>
48 <item>
49 <widget class="QPushButton" name="button_breakpoint">
50 <property name="text">
51 <string>Set Breakpoint</string>
52 </property>
53 </widget>
54 </item>
55 </layout>
56 </item>
57 <item>
58 <widget class="QTreeView" name="treeView">
59 <property name="alternatingRowColors">
60 <bool>true</bool>
61 </property>
62 <property name="indentation">
63 <number>20</number>
64 </property>
65 <property name="rootIsDecorated">
66 <bool>false</bool>
67 </property>
68 <property name="uniformRowHeights">
69 <bool>true</bool>
70 </property>
71 <attribute name="headerVisible">
72 <bool>false</bool>
73 </attribute>
74 </widget>
75 </item>
76 </layout>
77 </widget>
78 </widget>
79 <resources/>
80 <connections/>
81</ui>
diff --git a/src/citra_qt/main.cpp b/src/citra_qt/main.cpp
index ea66cc425..d7fad555f 100644
--- a/src/citra_qt/main.cpp
+++ b/src/citra_qt/main.cpp
@@ -16,8 +16,6 @@
16#include "citra_qt/bootmanager.h" 16#include "citra_qt/bootmanager.h"
17#include "citra_qt/configuration/config.h" 17#include "citra_qt/configuration/config.h"
18#include "citra_qt/configuration/configure_dialog.h" 18#include "citra_qt/configuration/configure_dialog.h"
19#include "citra_qt/debugger/callstack.h"
20#include "citra_qt/debugger/disassembler.h"
21#include "citra_qt/debugger/graphics/graphics.h" 19#include "citra_qt/debugger/graphics/graphics.h"
22#include "citra_qt/debugger/graphics/graphics_breakpoints.h" 20#include "citra_qt/debugger/graphics/graphics_breakpoints.h"
23#include "citra_qt/debugger/graphics/graphics_cmdlists.h" 21#include "citra_qt/debugger/graphics/graphics_cmdlists.h"
@@ -40,7 +38,6 @@
40#include "common/scm_rev.h" 38#include "common/scm_rev.h"
41#include "common/scope_exit.h" 39#include "common/scope_exit.h"
42#include "common/string_util.h" 40#include "common/string_util.h"
43#include "core/arm/disassembler/load_symbol_map.h"
44#include "core/core.h" 41#include "core/core.h"
45#include "core/file_sys/archive_source_sd_savedata.h" 42#include "core/file_sys/archive_source_sd_savedata.h"
46#include "core/gdbstub/gdbstub.h" 43#include "core/gdbstub/gdbstub.h"
@@ -130,15 +127,6 @@ void GMainWindow::InitializeDebugWidgets() {
130 debug_menu->addAction(microProfileDialog->toggleViewAction()); 127 debug_menu->addAction(microProfileDialog->toggleViewAction());
131#endif 128#endif
132 129
133 disasmWidget = new DisassemblerWidget(this, emu_thread.get());
134 addDockWidget(Qt::BottomDockWidgetArea, disasmWidget);
135 disasmWidget->hide();
136 debug_menu->addAction(disasmWidget->toggleViewAction());
137 connect(this, &GMainWindow::EmulationStarting, disasmWidget,
138 &DisassemblerWidget::OnEmulationStarting);
139 connect(this, &GMainWindow::EmulationStopping, disasmWidget,
140 &DisassemblerWidget::OnEmulationStopping);
141
142 registersWidget = new RegistersWidget(this); 130 registersWidget = new RegistersWidget(this);
143 addDockWidget(Qt::RightDockWidgetArea, registersWidget); 131 addDockWidget(Qt::RightDockWidgetArea, registersWidget);
144 registersWidget->hide(); 132 registersWidget->hide();
@@ -148,11 +136,6 @@ void GMainWindow::InitializeDebugWidgets() {
148 connect(this, &GMainWindow::EmulationStopping, registersWidget, 136 connect(this, &GMainWindow::EmulationStopping, registersWidget,
149 &RegistersWidget::OnEmulationStopping); 137 &RegistersWidget::OnEmulationStopping);
150 138
151 callstackWidget = new CallstackWidget(this);
152 addDockWidget(Qt::RightDockWidgetArea, callstackWidget);
153 callstackWidget->hide();
154 debug_menu->addAction(callstackWidget->toggleViewAction());
155
156 graphicsWidget = new GPUCommandStreamWidget(this); 139 graphicsWidget = new GPUCommandStreamWidget(this);
157 addDockWidget(Qt::RightDockWidgetArea, graphicsWidget); 140 addDockWidget(Qt::RightDockWidgetArea, graphicsWidget);
158 graphicsWidget->hide(); 141 graphicsWidget->hide();
@@ -269,8 +252,6 @@ void GMainWindow::ConnectWidgetEvents() {
269void GMainWindow::ConnectMenuEvents() { 252void GMainWindow::ConnectMenuEvents() {
270 // File 253 // File
271 connect(ui.action_Load_File, &QAction::triggered, this, &GMainWindow::OnMenuLoadFile); 254 connect(ui.action_Load_File, &QAction::triggered, this, &GMainWindow::OnMenuLoadFile);
272 connect(ui.action_Load_Symbol_Map, &QAction::triggered, this,
273 &GMainWindow::OnMenuLoadSymbolMap);
274 connect(ui.action_Select_Game_List_Root, &QAction::triggered, this, 255 connect(ui.action_Select_Game_List_Root, &QAction::triggered, this,
275 &GMainWindow::OnMenuSelectGameListRoot); 256 &GMainWindow::OnMenuSelectGameListRoot);
276 connect(ui.action_Exit, &QAction::triggered, this, &QMainWindow::close); 257 connect(ui.action_Exit, &QAction::triggered, this, &QMainWindow::close);
@@ -391,26 +372,17 @@ void GMainWindow::BootGame(const QString& filename) {
391 connect(render_window, SIGNAL(Closed()), this, SLOT(OnStopGame())); 372 connect(render_window, SIGNAL(Closed()), this, SLOT(OnStopGame()));
392 // BlockingQueuedConnection is important here, it makes sure we've finished refreshing our views 373 // BlockingQueuedConnection is important here, it makes sure we've finished refreshing our views
393 // before the CPU continues 374 // before the CPU continues
394 connect(emu_thread.get(), SIGNAL(DebugModeEntered()), disasmWidget, SLOT(OnDebugModeEntered()),
395 Qt::BlockingQueuedConnection);
396 connect(emu_thread.get(), SIGNAL(DebugModeEntered()), registersWidget, 375 connect(emu_thread.get(), SIGNAL(DebugModeEntered()), registersWidget,
397 SLOT(OnDebugModeEntered()), Qt::BlockingQueuedConnection); 376 SLOT(OnDebugModeEntered()), Qt::BlockingQueuedConnection);
398 connect(emu_thread.get(), SIGNAL(DebugModeEntered()), callstackWidget,
399 SLOT(OnDebugModeEntered()), Qt::BlockingQueuedConnection);
400 connect(emu_thread.get(), SIGNAL(DebugModeEntered()), waitTreeWidget, 377 connect(emu_thread.get(), SIGNAL(DebugModeEntered()), waitTreeWidget,
401 SLOT(OnDebugModeEntered()), Qt::BlockingQueuedConnection); 378 SLOT(OnDebugModeEntered()), Qt::BlockingQueuedConnection);
402 connect(emu_thread.get(), SIGNAL(DebugModeLeft()), disasmWidget, SLOT(OnDebugModeLeft()),
403 Qt::BlockingQueuedConnection);
404 connect(emu_thread.get(), SIGNAL(DebugModeLeft()), registersWidget, SLOT(OnDebugModeLeft()), 379 connect(emu_thread.get(), SIGNAL(DebugModeLeft()), registersWidget, SLOT(OnDebugModeLeft()),
405 Qt::BlockingQueuedConnection); 380 Qt::BlockingQueuedConnection);
406 connect(emu_thread.get(), SIGNAL(DebugModeLeft()), callstackWidget, SLOT(OnDebugModeLeft()),
407 Qt::BlockingQueuedConnection);
408 connect(emu_thread.get(), SIGNAL(DebugModeLeft()), waitTreeWidget, SLOT(OnDebugModeLeft()), 381 connect(emu_thread.get(), SIGNAL(DebugModeLeft()), waitTreeWidget, SLOT(OnDebugModeLeft()),
409 Qt::BlockingQueuedConnection); 382 Qt::BlockingQueuedConnection);
410 383
411 // Update the GUI 384 // Update the GUI
412 registersWidget->OnDebugModeEntered(); 385 registersWidget->OnDebugModeEntered();
413 callstackWidget->OnDebugModeEntered();
414 if (ui.action_Single_Window_Mode->isChecked()) { 386 if (ui.action_Single_Window_Mode->isChecked()) {
415 game_list->hide(); 387 game_list->hide();
416 } 388 }
@@ -531,16 +503,6 @@ void GMainWindow::OnMenuLoadFile() {
531 } 503 }
532} 504}
533 505
534void GMainWindow::OnMenuLoadSymbolMap() {
535 QString filename = QFileDialog::getOpenFileName(
536 this, tr("Load Symbol Map"), UISettings::values.symbols_path, tr("Symbol Map (*.*)"));
537 if (!filename.isEmpty()) {
538 UISettings::values.symbols_path = QFileInfo(filename).path();
539
540 LoadSymbolMap(filename.toStdString());
541 }
542}
543
544void GMainWindow::OnMenuSelectGameListRoot() { 506void GMainWindow::OnMenuSelectGameListRoot() {
545 QString dir_path = QFileDialog::getExistingDirectory(this, tr("Select Directory")); 507 QString dir_path = QFileDialog::getExistingDirectory(this, tr("Select Directory"));
546 if (!dir_path.isEmpty()) { 508 if (!dir_path.isEmpty()) {
diff --git a/src/citra_qt/main.h b/src/citra_qt/main.h
index 2f398eb7b..cb2e87cbd 100644
--- a/src/citra_qt/main.h
+++ b/src/citra_qt/main.h
@@ -10,9 +10,7 @@
10#include <QTimer> 10#include <QTimer>
11#include "ui_main.h" 11#include "ui_main.h"
12 12
13class CallstackWidget;
14class Config; 13class Config;
15class DisassemblerWidget;
16class EmuThread; 14class EmuThread;
17class GameList; 15class GameList;
18class GImageInfo; 16class GImageInfo;
@@ -118,7 +116,6 @@ private slots:
118 void OnGameListLoadFile(QString game_path); 116 void OnGameListLoadFile(QString game_path);
119 void OnGameListOpenSaveFolder(u64 program_id); 117 void OnGameListOpenSaveFolder(u64 program_id);
120 void OnMenuLoadFile(); 118 void OnMenuLoadFile();
121 void OnMenuLoadSymbolMap();
122 /// Called whenever a user selects the "File->Select Game List Root" menu item 119 /// Called whenever a user selects the "File->Select Game List Root" menu item
123 void OnMenuSelectGameListRoot(); 120 void OnMenuSelectGameListRoot();
124 void OnMenuRecentFile(); 121 void OnMenuRecentFile();
@@ -152,9 +149,7 @@ private:
152 // Debugger panes 149 // Debugger panes
153 ProfilerWidget* profilerWidget; 150 ProfilerWidget* profilerWidget;
154 MicroProfileDialog* microProfileDialog; 151 MicroProfileDialog* microProfileDialog;
155 DisassemblerWidget* disasmWidget;
156 RegistersWidget* registersWidget; 152 RegistersWidget* registersWidget;
157 CallstackWidget* callstackWidget;
158 GPUCommandStreamWidget* graphicsWidget; 153 GPUCommandStreamWidget* graphicsWidget;
159 GPUCommandListWidget* graphicsCommandsWidget; 154 GPUCommandListWidget* graphicsCommandsWidget;
160 GraphicsBreakPointsWidget* graphicsBreakpointsWidget; 155 GraphicsBreakPointsWidget* graphicsBreakpointsWidget;
diff --git a/src/citra_qt/main.ui b/src/citra_qt/main.ui
index f64b878f0..b13d578f5 100644
--- a/src/citra_qt/main.ui
+++ b/src/citra_qt/main.ui
@@ -58,7 +58,6 @@
58 </property> 58 </property>
59 </widget> 59 </widget>
60 <addaction name="action_Load_File"/> 60 <addaction name="action_Load_File"/>
61 <addaction name="action_Load_Symbol_Map"/>
62 <addaction name="separator"/> 61 <addaction name="separator"/>
63 <addaction name="action_Select_Game_List_Root"/> 62 <addaction name="action_Select_Game_List_Root"/>
64 <addaction name="menu_recent_files"/> 63 <addaction name="menu_recent_files"/>
diff --git a/src/common/CMakeLists.txt b/src/common/CMakeLists.txt
index 13277a5c2..4b30185f1 100644
--- a/src/common/CMakeLists.txt
+++ b/src/common/CMakeLists.txt
@@ -38,7 +38,6 @@ set(SRCS
38 param_package.cpp 38 param_package.cpp
39 scm_rev.cpp 39 scm_rev.cpp
40 string_util.cpp 40 string_util.cpp
41 symbols.cpp
42 thread.cpp 41 thread.cpp
43 timer.cpp 42 timer.cpp
44 ) 43 )
@@ -74,7 +73,6 @@ set(HEADERS
74 scope_exit.h 73 scope_exit.h
75 string_util.h 74 string_util.h
76 swap.h 75 swap.h
77 symbols.h
78 synchronized_wrapper.h 76 synchronized_wrapper.h
79 thread.h 77 thread.h
80 thread_queue_list.h 78 thread_queue_list.h
diff --git a/src/common/symbols.cpp b/src/common/symbols.cpp
deleted file mode 100644
index c4d16af85..000000000
--- a/src/common/symbols.cpp
+++ /dev/null
@@ -1,46 +0,0 @@
1// Copyright 2014 Citra Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#include "common/symbols.h"
6
7TSymbolsMap g_symbols;
8
9namespace Symbols {
10bool HasSymbol(u32 address) {
11 return g_symbols.find(address) != g_symbols.end();
12}
13
14void Add(u32 address, const std::string& name, u32 size, u32 type) {
15 if (!HasSymbol(address)) {
16 TSymbol symbol;
17 symbol.address = address;
18 symbol.name = name;
19 symbol.size = size;
20 symbol.type = type;
21
22 g_symbols.emplace(address, symbol);
23 }
24}
25
26TSymbol GetSymbol(u32 address) {
27 const auto iter = g_symbols.find(address);
28
29 if (iter != g_symbols.end())
30 return iter->second;
31
32 return {};
33}
34
35const std::string GetName(u32 address) {
36 return GetSymbol(address).name;
37}
38
39void Remove(u32 address) {
40 g_symbols.erase(address);
41}
42
43void Clear() {
44 g_symbols.clear();
45}
46}
diff --git a/src/common/symbols.h b/src/common/symbols.h
deleted file mode 100644
index f5a48e05a..000000000
--- a/src/common/symbols.h
+++ /dev/null
@@ -1,30 +0,0 @@
1// Copyright 2014 Citra Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#pragma once
6
7#include <map>
8#include <string>
9#include <utility>
10#include "common/common_types.h"
11
12struct TSymbol {
13 u32 address = 0;
14 std::string name;
15 u32 size = 0;
16 u32 type = 0;
17};
18
19typedef std::map<u32, TSymbol> TSymbolsMap;
20typedef std::pair<u32, TSymbol> TSymbolsPair;
21
22namespace Symbols {
23bool HasSymbol(u32 address);
24
25void Add(u32 address, const std::string& name, u32 size, u32 type);
26TSymbol GetSymbol(u32 address);
27const std::string GetName(u32 address);
28void Remove(u32 address);
29void Clear();
30}
diff --git a/src/core/CMakeLists.txt b/src/core/CMakeLists.txt
index a2866fdd8..e404063f0 100644
--- a/src/core/CMakeLists.txt
+++ b/src/core/CMakeLists.txt
@@ -1,6 +1,4 @@
1set(SRCS 1set(SRCS
2 arm/disassembler/arm_disasm.cpp
3 arm/disassembler/load_symbol_map.cpp
4 arm/dynarmic/arm_dynarmic.cpp 2 arm/dynarmic/arm_dynarmic.cpp
5 arm/dynarmic/arm_dynarmic_cp15.cpp 3 arm/dynarmic/arm_dynarmic_cp15.cpp
6 arm/dyncom/arm_dyncom.cpp 4 arm/dyncom/arm_dyncom.cpp
@@ -179,8 +177,6 @@ set(SRCS
179 177
180set(HEADERS 178set(HEADERS
181 arm/arm_interface.h 179 arm/arm_interface.h
182 arm/disassembler/arm_disasm.h
183 arm/disassembler/load_symbol_map.h
184 arm/dynarmic/arm_dynarmic.h 180 arm/dynarmic/arm_dynarmic.h
185 arm/dynarmic/arm_dynarmic_cp15.h 181 arm/dynarmic/arm_dynarmic_cp15.h
186 arm/dyncom/arm_dyncom.h 182 arm/dyncom/arm_dyncom.h
diff --git a/src/core/arm/disassembler/arm_disasm.cpp b/src/core/arm/disassembler/arm_disasm.cpp
deleted file mode 100644
index 05d6ed1fb..000000000
--- a/src/core/arm/disassembler/arm_disasm.cpp
+++ /dev/null
@@ -1,1344 +0,0 @@
1// Copyright 2006 The Android Open Source Project
2
3#include <string>
4#include <unordered_set>
5#include "common/common_types.h"
6#include "common/string_util.h"
7#include "core/arm/disassembler/arm_disasm.h"
8#include "core/arm/skyeye_common/armsupp.h"
9
10static const char* cond_names[] = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
11 "hi", "ls", "ge", "lt", "gt", "le", "", "RESERVED"};
12
13static const char* opcode_names[] = {
14 "invalid", "undefined", "adc", "add", "and", "b", "bl", "bic",
15 "bkpt", "blx", "bx", "cdp", "clrex", "clz", "cmn", "cmp",
16 "eor", "ldc", "ldm", "ldr", "ldrb", "ldrbt", "ldrex", "ldrexb",
17 "ldrexd", "ldrexh", "ldrh", "ldrsb", "ldrsh", "ldrt", "mcr", "mla",
18 "mov", "mrc", "mrs", "msr", "mul", "mvn", "nop", "orr",
19 "pkh", "pld", "qadd16", "qadd8", "qasx", "qsax", "qsub16", "qsub8",
20 "rev", "rev16", "revsh", "rsb", "rsc", "sadd16", "sadd8", "sasx",
21 "sbc", "sel", "sev", "shadd16", "shadd8", "shasx", "shsax", "shsub16",
22 "shsub8", "smlad", "smlal", "smlald", "smlsd", "smlsld", "smmla", "smmls",
23 "smmul", "smuad", "smull", "smusd", "ssat", "ssat16", "ssax", "ssub16",
24 "ssub8", "stc", "stm", "str", "strb", "strbt", "strex", "strexb",
25 "strexd", "strexh", "strh", "strt", "sub", "swi", "swp", "swpb",
26 "sxtab", "sxtab16", "sxtah", "sxtb", "sxtb16", "sxth", "teq", "tst",
27 "uadd16", "uadd8", "uasx", "uhadd16", "uhadd8", "uhasx", "uhsax", "uhsub16",
28 "uhsub8", "umlal", "umull", "uqadd16", "uqadd8", "uqasx", "uqsax", "uqsub16",
29 "uqsub8", "usad8", "usada8", "usat", "usat16", "usax", "usub16", "usub8",
30 "uxtab", "uxtab16", "uxtah", "uxtb", "uxtb16", "uxth", "wfe", "wfi",
31 "yield",
32
33 "undefined", "adc", "add", "and", "asr", "b", "bic", "bkpt",
34 "bl", "blx", "bx", "cmn", "cmp", "eor", "ldmia", "ldr",
35 "ldrb", "ldrh", "ldrsb", "ldrsh", "lsl", "lsr", "mov", "mul",
36 "mvn", "neg", "orr", "pop", "push", "ror", "sbc", "stmia",
37 "str", "strb", "strh", "sub", "swi", "tst",
38
39 nullptr};
40
41// Indexed by the shift type (bits 6-5)
42static const char* shift_names[] = {"LSL", "LSR", "ASR", "ROR"};
43
44static const char* cond_to_str(u32 cond) {
45 return cond_names[cond];
46}
47
48std::string ARM_Disasm::Disassemble(u32 addr, u32 insn) {
49 Opcode opcode = Decode(insn);
50 switch (opcode) {
51 case OP_INVALID:
52 return "Invalid";
53 case OP_UNDEFINED:
54 return "Undefined";
55 case OP_ADC:
56 case OP_ADD:
57 case OP_AND:
58 case OP_BIC:
59 case OP_CMN:
60 case OP_CMP:
61 case OP_EOR:
62 case OP_MOV:
63 case OP_MVN:
64 case OP_ORR:
65 case OP_RSB:
66 case OP_RSC:
67 case OP_SBC:
68 case OP_SUB:
69 case OP_TEQ:
70 case OP_TST:
71 return DisassembleALU(opcode, insn);
72 case OP_B:
73 case OP_BL:
74 return DisassembleBranch(addr, opcode, insn);
75 case OP_BKPT:
76 return DisassembleBKPT(insn);
77 case OP_BLX:
78 // not supported yet
79 break;
80 case OP_BX:
81 return DisassembleBX(insn);
82 case OP_CDP:
83 return "cdp";
84 case OP_CLREX:
85 return "clrex";
86 case OP_CLZ:
87 return DisassembleCLZ(insn);
88 case OP_LDC:
89 return "ldc";
90 case OP_LDM:
91 case OP_STM:
92 return DisassembleMemblock(opcode, insn);
93 case OP_LDR:
94 case OP_LDRB:
95 case OP_LDRBT:
96 case OP_LDRT:
97 case OP_STR:
98 case OP_STRB:
99 case OP_STRBT:
100 case OP_STRT:
101 return DisassembleMem(insn);
102 case OP_LDREX:
103 case OP_LDREXB:
104 case OP_LDREXD:
105 case OP_LDREXH:
106 case OP_STREX:
107 case OP_STREXB:
108 case OP_STREXD:
109 case OP_STREXH:
110 return DisassembleREX(opcode, insn);
111 case OP_LDRH:
112 case OP_LDRSB:
113 case OP_LDRSH:
114 case OP_STRH:
115 return DisassembleMemHalf(insn);
116 case OP_MCR:
117 case OP_MRC:
118 return DisassembleMCR(opcode, insn);
119 case OP_MLA:
120 return DisassembleMLA(opcode, insn);
121 case OP_MRS:
122 return DisassembleMRS(insn);
123 case OP_MSR:
124 return DisassembleMSR(insn);
125 case OP_MUL:
126 return DisassembleMUL(opcode, insn);
127 case OP_NOP:
128 case OP_SEV:
129 case OP_WFE:
130 case OP_WFI:
131 case OP_YIELD:
132 return DisassembleNoOperands(opcode, insn);
133 case OP_PKH:
134 return DisassemblePKH(insn);
135 case OP_PLD:
136 return DisassemblePLD(insn);
137 case OP_QADD16:
138 case OP_QADD8:
139 case OP_QASX:
140 case OP_QSAX:
141 case OP_QSUB16:
142 case OP_QSUB8:
143 case OP_SADD16:
144 case OP_SADD8:
145 case OP_SASX:
146 case OP_SHADD16:
147 case OP_SHADD8:
148 case OP_SHASX:
149 case OP_SHSAX:
150 case OP_SHSUB16:
151 case OP_SHSUB8:
152 case OP_SSAX:
153 case OP_SSUB16:
154 case OP_SSUB8:
155 case OP_UADD16:
156 case OP_UADD8:
157 case OP_UASX:
158 case OP_UHADD16:
159 case OP_UHADD8:
160 case OP_UHASX:
161 case OP_UHSAX:
162 case OP_UHSUB16:
163 case OP_UHSUB8:
164 case OP_UQADD16:
165 case OP_UQADD8:
166 case OP_UQASX:
167 case OP_UQSAX:
168 case OP_UQSUB16:
169 case OP_UQSUB8:
170 case OP_USAX:
171 case OP_USUB16:
172 case OP_USUB8:
173 return DisassembleParallelAddSub(opcode, insn);
174 case OP_REV:
175 case OP_REV16:
176 case OP_REVSH:
177 return DisassembleREV(opcode, insn);
178 case OP_SEL:
179 return DisassembleSEL(insn);
180 case OP_SMLAD:
181 case OP_SMLALD:
182 case OP_SMLSD:
183 case OP_SMLSLD:
184 case OP_SMMLA:
185 case OP_SMMLS:
186 case OP_SMMUL:
187 case OP_SMUAD:
188 case OP_SMUSD:
189 case OP_USAD8:
190 case OP_USADA8:
191 return DisassembleMediaMulDiv(opcode, insn);
192 case OP_SSAT:
193 case OP_SSAT16:
194 case OP_USAT:
195 case OP_USAT16:
196 return DisassembleSAT(opcode, insn);
197 case OP_STC:
198 return "stc";
199 case OP_SWI:
200 return DisassembleSWI(insn);
201 case OP_SWP:
202 case OP_SWPB:
203 return DisassembleSWP(opcode, insn);
204 case OP_SXTAB:
205 case OP_SXTAB16:
206 case OP_SXTAH:
207 case OP_SXTB:
208 case OP_SXTB16:
209 case OP_SXTH:
210 case OP_UXTAB:
211 case OP_UXTAB16:
212 case OP_UXTAH:
213 case OP_UXTB:
214 case OP_UXTB16:
215 case OP_UXTH:
216 return DisassembleXT(opcode, insn);
217 case OP_UMLAL:
218 case OP_UMULL:
219 case OP_SMLAL:
220 case OP_SMULL:
221 return DisassembleUMLAL(opcode, insn);
222 default:
223 return "Error";
224 }
225 return nullptr;
226}
227
228std::string ARM_Disasm::DisassembleALU(Opcode opcode, u32 insn) {
229 static const u8 kNoOperand1 = 1;
230 static const u8 kNoDest = 2;
231 static const u8 kNoSbit = 4;
232
233 std::string rn_str;
234 std::string rd_str;
235
236 u8 flags = 0;
237 u8 cond = (insn >> 28) & 0xf;
238 u8 is_immed = (insn >> 25) & 0x1;
239 u8 bit_s = (insn >> 20) & 1;
240 u8 rn = (insn >> 16) & 0xf;
241 u8 rd = (insn >> 12) & 0xf;
242 u8 immed = insn & 0xff;
243
244 const char* opname = opcode_names[opcode];
245 switch (opcode) {
246 case OP_CMN:
247 case OP_CMP:
248 case OP_TEQ:
249 case OP_TST:
250 flags = kNoDest | kNoSbit;
251 break;
252 case OP_MOV:
253 case OP_MVN:
254 flags = kNoOperand1;
255 break;
256 default:
257 break;
258 }
259
260 // The "mov" instruction ignores the first operand (rn).
261 rn_str[0] = 0;
262 if ((flags & kNoOperand1) == 0) {
263 rn_str = Common::StringFromFormat("r%d, ", rn);
264 }
265
266 // The following instructions do not write the result register (rd):
267 // tst, teq, cmp, cmn.
268 rd_str[0] = 0;
269 if ((flags & kNoDest) == 0) {
270 rd_str = Common::StringFromFormat("r%d, ", rd);
271 }
272
273 const char* sbit_str = "";
274 if (bit_s && !(flags & kNoSbit))
275 sbit_str = "s";
276
277 if (is_immed) {
278 return Common::StringFromFormat("%s%s%s\t%s%s#%u ; 0x%x", opname, cond_to_str(cond),
279 sbit_str, rd_str.c_str(), rn_str.c_str(), immed, immed);
280 }
281
282 u8 shift_is_reg = (insn >> 4) & 1;
283 u8 rotate = (insn >> 8) & 0xf;
284 u8 rm = insn & 0xf;
285 u8 shift_type = (insn >> 5) & 0x3;
286 u8 rs = (insn >> 8) & 0xf;
287 u8 shift_amount = (insn >> 7) & 0x1f;
288 u32 rotated_val = immed;
289 u8 rotate2 = rotate << 1;
290 rotated_val = (rotated_val >> rotate2) | (rotated_val << (32 - rotate2));
291
292 if (!shift_is_reg && shift_type == 0 && shift_amount == 0) {
293 return Common::StringFromFormat("%s%s%s\t%s%sr%d", opname, cond_to_str(cond), sbit_str,
294 rd_str.c_str(), rn_str.c_str(), rm);
295 }
296
297 const char* shift_name = shift_names[shift_type];
298 if (shift_is_reg) {
299 return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s r%d", opname, cond_to_str(cond),
300 sbit_str, rd_str.c_str(), rn_str.c_str(), rm, shift_name,
301 rs);
302 }
303 if (shift_amount == 0) {
304 if (shift_type == 3) {
305 return Common::StringFromFormat("%s%s%s\t%s%sr%d, RRX", opname, cond_to_str(cond),
306 sbit_str, rd_str.c_str(), rn_str.c_str(), rm);
307 }
308 shift_amount = 32;
309 }
310 return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s #%u", opname, cond_to_str(cond), sbit_str,
311 rd_str.c_str(), rn_str.c_str(), rm, shift_name, shift_amount);
312}
313
314std::string ARM_Disasm::DisassembleBranch(u32 addr, Opcode opcode, u32 insn) {
315 u8 cond = (insn >> 28) & 0xf;
316 u32 offset = insn & 0xffffff;
317 // Sign-extend the 24-bit offset
318 if ((offset >> 23) & 1)
319 offset |= 0xff000000;
320
321 // Pre-compute the left-shift and the prefetch offset
322 offset <<= 2;
323 offset += 8;
324 addr += offset;
325 const char* opname = opcode_names[opcode];
326 return Common::StringFromFormat("%s%s\t0x%x", opname, cond_to_str(cond), addr);
327}
328
329std::string ARM_Disasm::DisassembleBX(u32 insn) {
330 u8 cond = (insn >> 28) & 0xf;
331 u8 rn = insn & 0xf;
332 return Common::StringFromFormat("bx%s\tr%d", cond_to_str(cond), rn);
333}
334
335std::string ARM_Disasm::DisassembleBKPT(u32 insn) {
336 u8 cond = (insn >> 28) & 0xf;
337 u32 immed = (((insn >> 8) & 0xfff) << 4) | (insn & 0xf);
338 return Common::StringFromFormat("bkpt%s\t#%d", cond_to_str(cond), immed);
339}
340
341std::string ARM_Disasm::DisassembleCLZ(u32 insn) {
342 u8 cond = (insn >> 28) & 0xf;
343 u8 rd = (insn >> 12) & 0xf;
344 u8 rm = insn & 0xf;
345 return Common::StringFromFormat("clz%s\tr%d, r%d", cond_to_str(cond), rd, rm);
346}
347
348std::string ARM_Disasm::DisassembleMediaMulDiv(Opcode opcode, u32 insn) {
349 u32 cond = BITS(insn, 28, 31);
350 u32 rd = BITS(insn, 16, 19);
351 u32 ra = BITS(insn, 12, 15);
352 u32 rm = BITS(insn, 8, 11);
353 u32 m = BIT(insn, 5);
354 u32 rn = BITS(insn, 0, 3);
355
356 std::string cross = "";
357 if (m) {
358 if (opcode == OP_SMMLA || opcode == OP_SMMUL || opcode == OP_SMMLS)
359 cross = "r";
360 else
361 cross = "x";
362 }
363
364 std::string ext_reg = "";
365 std::unordered_set<Opcode, std::hash<int>> with_ext_reg = {OP_SMLAD, OP_SMLSD, OP_SMMLA,
366 OP_SMMLS, OP_USADA8};
367 if (with_ext_reg.find(opcode) != with_ext_reg.end())
368 ext_reg = Common::StringFromFormat(", r%u", ra);
369
370 std::string rd_low = "";
371 if (opcode == OP_SMLALD || opcode == OP_SMLSLD)
372 rd_low = Common::StringFromFormat("r%u, ", ra);
373
374 return Common::StringFromFormat("%s%s%s\t%sr%u, r%u, r%u%s", opcode_names[opcode],
375 cross.c_str(), cond_to_str(cond), rd_low.c_str(), rd, rn, rm,
376 ext_reg.c_str());
377}
378
379std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, u32 insn) {
380 std::string tmp_list;
381
382 u8 cond = (insn >> 28) & 0xf;
383 u8 write_back = (insn >> 21) & 0x1;
384 u8 bit_s = (insn >> 22) & 0x1;
385 u8 is_up = (insn >> 23) & 0x1;
386 u8 is_pre = (insn >> 24) & 0x1;
387 u8 rn = (insn >> 16) & 0xf;
388 u16 reg_list = insn & 0xffff;
389
390 const char* opname = opcode_names[opcode];
391
392 const char* bang = "";
393 if (write_back)
394 bang = "!";
395
396 const char* carret = "";
397 if (bit_s)
398 carret = "^";
399
400 const char* comma = "";
401 tmp_list[0] = 0;
402 for (int ii = 0; ii < 16; ++ii) {
403 if (reg_list & (1 << ii)) {
404 tmp_list += Common::StringFromFormat("%sr%d", comma, ii);
405 comma = ",";
406 }
407 }
408
409 const char* addr_mode = "";
410 if (is_pre) {
411 if (is_up) {
412 addr_mode = "ib";
413 } else {
414 addr_mode = "db";
415 }
416 } else {
417 if (is_up) {
418 addr_mode = "ia";
419 } else {
420 addr_mode = "da";
421 }
422 }
423
424 return Common::StringFromFormat("%s%s%s\tr%d%s, {%s}%s", opname, cond_to_str(cond), addr_mode,
425 rn, bang, tmp_list.c_str(), carret);
426}
427
428std::string ARM_Disasm::DisassembleMem(u32 insn) {
429 u8 cond = (insn >> 28) & 0xf;
430 u8 is_reg = (insn >> 25) & 0x1;
431 u8 is_load = (insn >> 20) & 0x1;
432 u8 write_back = (insn >> 21) & 0x1;
433 u8 is_byte = (insn >> 22) & 0x1;
434 u8 is_up = (insn >> 23) & 0x1;
435 u8 is_pre = (insn >> 24) & 0x1;
436 u8 rn = (insn >> 16) & 0xf;
437 u8 rd = (insn >> 12) & 0xf;
438 u16 offset = insn & 0xfff;
439
440 const char* opname = "ldr";
441 if (!is_load)
442 opname = "str";
443
444 const char* bang = "";
445 if (write_back)
446 bang = "!";
447
448 const char* minus = "";
449 if (is_up == 0)
450 minus = "-";
451
452 const char* byte = "";
453 if (is_byte)
454 byte = "b";
455
456 if (is_reg == 0) {
457 if (is_pre) {
458 if (offset == 0) {
459 return Common::StringFromFormat("%s%s%s\tr%d, [r%d]", opname, cond_to_str(cond),
460 byte, rd, rn);
461 } else {
462 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s", opname,
463 cond_to_str(cond), byte, rd, rn, minus, offset,
464 bang);
465 }
466 } else {
467 const char* transfer = "";
468 if (write_back)
469 transfer = "t";
470
471 return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], #%s%u", opname,
472 cond_to_str(cond), byte, transfer, rd, rn, minus,
473 offset);
474 }
475 }
476
477 u8 rm = insn & 0xf;
478 u8 shift_type = (insn >> 5) & 0x3;
479 u8 shift_amount = (insn >> 7) & 0x1f;
480
481 const char* shift_name = shift_names[shift_type];
482
483 if (is_pre) {
484 if (shift_amount == 0) {
485 if (shift_type == 0) {
486 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s", opname,
487 cond_to_str(cond), byte, rd, rn, minus, rm, bang);
488 }
489 if (shift_type == 3) {
490 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, RRX]%s", opname,
491 cond_to_str(cond), byte, rd, rn, minus, rm, bang);
492 }
493 shift_amount = 32;
494 }
495 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, %s #%u]%s", opname,
496 cond_to_str(cond), byte, rd, rn, minus, rm, shift_name,
497 shift_amount, bang);
498 }
499
500 const char* transfer = "";
501 if (write_back)
502 transfer = "t";
503
504 if (shift_amount == 0) {
505 if (shift_type == 0) {
506 return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d", opname,
507 cond_to_str(cond), byte, transfer, rd, rn, minus, rm);
508 }
509 if (shift_type == 3) {
510 return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, RRX", opname,
511 cond_to_str(cond), byte, transfer, rd, rn, minus, rm);
512 }
513 shift_amount = 32;
514 }
515
516 return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, %s #%u", opname,
517 cond_to_str(cond), byte, transfer, rd, rn, minus, rm,
518 shift_name, shift_amount);
519}
520
521std::string ARM_Disasm::DisassembleMemHalf(u32 insn) {
522 u8 cond = (insn >> 28) & 0xf;
523 u8 is_load = (insn >> 20) & 0x1;
524 u8 write_back = (insn >> 21) & 0x1;
525 u8 is_immed = (insn >> 22) & 0x1;
526 u8 is_up = (insn >> 23) & 0x1;
527 u8 is_pre = (insn >> 24) & 0x1;
528 u8 rn = (insn >> 16) & 0xf;
529 u8 rd = (insn >> 12) & 0xf;
530 u8 bits_65 = (insn >> 5) & 0x3;
531 u8 rm = insn & 0xf;
532 u8 offset = (((insn >> 8) & 0xf) << 4) | (insn & 0xf);
533
534 const char* opname = "ldr";
535 if (is_load == 0)
536 opname = "str";
537
538 const char* width = "";
539 if (bits_65 == 1)
540 width = "h";
541 else if (bits_65 == 2)
542 width = "sb";
543 else
544 width = "sh";
545
546 const char* bang = "";
547 if (write_back)
548 bang = "!";
549 const char* minus = "";
550 if (is_up == 0)
551 minus = "-";
552
553 if (is_immed) {
554 if (is_pre) {
555 if (offset == 0) {
556 return Common::StringFromFormat("%s%s%s\tr%d, [r%d]", opname, cond_to_str(cond),
557 width, rd, rn);
558 } else {
559 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s", opname,
560 cond_to_str(cond), width, rd, rn, minus, offset,
561 bang);
562 }
563 } else {
564 return Common::StringFromFormat("%s%s%s\tr%d, [r%d], #%s%u", opname, cond_to_str(cond),
565 width, rd, rn, minus, offset);
566 }
567 }
568
569 if (is_pre) {
570 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s", opname, cond_to_str(cond),
571 width, rd, rn, minus, rm, bang);
572 } else {
573 return Common::StringFromFormat("%s%s%s\tr%d, [r%d], %sr%d", opname, cond_to_str(cond),
574 width, rd, rn, minus, rm);
575 }
576}
577
578std::string ARM_Disasm::DisassembleMCR(Opcode opcode, u32 insn) {
579 u8 cond = (insn >> 28) & 0xf;
580 u8 crn = (insn >> 16) & 0xf;
581 u8 crd = (insn >> 12) & 0xf;
582 u8 cpnum = (insn >> 8) & 0xf;
583 u8 opcode2 = (insn >> 5) & 0x7;
584 u8 crm = insn & 0xf;
585
586 const char* opname = opcode_names[opcode];
587 return Common::StringFromFormat("%s%s\t%d, 0, r%d, cr%d, cr%d, {%d}", opname, cond_to_str(cond),
588 cpnum, crd, crn, crm, opcode2);
589}
590
591std::string ARM_Disasm::DisassembleMLA(Opcode opcode, u32 insn) {
592 u8 cond = (insn >> 28) & 0xf;
593 u8 rd = (insn >> 16) & 0xf;
594 u8 rn = (insn >> 12) & 0xf;
595 u8 rs = (insn >> 8) & 0xf;
596 u8 rm = insn & 0xf;
597 u8 bit_s = (insn >> 20) & 1;
598
599 const char* opname = opcode_names[opcode];
600 return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d", opname, cond_to_str(cond),
601 bit_s ? "s" : "", rd, rm, rs, rn);
602}
603
604std::string ARM_Disasm::DisassembleUMLAL(Opcode opcode, u32 insn) {
605 u8 cond = (insn >> 28) & 0xf;
606 u8 rdhi = (insn >> 16) & 0xf;
607 u8 rdlo = (insn >> 12) & 0xf;
608 u8 rs = (insn >> 8) & 0xf;
609 u8 rm = insn & 0xf;
610 u8 bit_s = (insn >> 20) & 1;
611
612 const char* opname = opcode_names[opcode];
613 return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d", opname, cond_to_str(cond),
614 bit_s ? "s" : "", rdlo, rdhi, rm, rs);
615}
616
617std::string ARM_Disasm::DisassembleMUL(Opcode opcode, u32 insn) {
618 u8 cond = (insn >> 28) & 0xf;
619 u8 rd = (insn >> 16) & 0xf;
620 u8 rs = (insn >> 8) & 0xf;
621 u8 rm = insn & 0xf;
622 u8 bit_s = (insn >> 20) & 1;
623
624 const char* opname = opcode_names[opcode];
625 return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d", opname, cond_to_str(cond),
626 bit_s ? "s" : "", rd, rm, rs);
627}
628
629std::string ARM_Disasm::DisassembleMRS(u32 insn) {
630 u8 cond = (insn >> 28) & 0xf;
631 u8 rd = (insn >> 12) & 0xf;
632 u8 ps = (insn >> 22) & 1;
633
634 return Common::StringFromFormat("mrs%s\tr%d, %s", cond_to_str(cond), rd, ps ? "spsr" : "cpsr");
635}
636
637std::string ARM_Disasm::DisassembleMSR(u32 insn) {
638 char flags[8];
639 int flag_index = 0;
640 u8 cond = (insn >> 28) & 0xf;
641 u8 is_immed = (insn >> 25) & 0x1;
642 u8 pd = (insn >> 22) & 1;
643 u8 mask = (insn >> 16) & 0xf;
644
645 if (mask & 1)
646 flags[flag_index++] = 'c';
647 if (mask & 2)
648 flags[flag_index++] = 'x';
649 if (mask & 4)
650 flags[flag_index++] = 's';
651 if (mask & 8)
652 flags[flag_index++] = 'f';
653 flags[flag_index] = 0;
654
655 if (is_immed) {
656 u32 immed = insn & 0xff;
657 u8 rotate = (insn >> 8) & 0xf;
658 u8 rotate2 = rotate << 1;
659 u32 rotated_val = (immed >> rotate2) | (immed << (32 - rotate2));
660 return Common::StringFromFormat("msr%s\t%s_%s, #0x%x", cond_to_str(cond),
661 pd ? "spsr" : "cpsr", flags, rotated_val);
662 }
663
664 u8 rm = insn & 0xf;
665
666 return Common::StringFromFormat("msr%s\t%s_%s, r%d", cond_to_str(cond), pd ? "spsr" : "cpsr",
667 flags, rm);
668}
669
670std::string ARM_Disasm::DisassembleNoOperands(Opcode opcode, u32 insn) {
671 u32 cond = BITS(insn, 28, 31);
672 return Common::StringFromFormat("%s%s", opcode_names[opcode], cond_to_str(cond));
673}
674
675std::string ARM_Disasm::DisassembleParallelAddSub(Opcode opcode, u32 insn) {
676 u32 cond = BITS(insn, 28, 31);
677 u32 rn = BITS(insn, 16, 19);
678 u32 rd = BITS(insn, 12, 15);
679 u32 rm = BITS(insn, 0, 3);
680
681 return Common::StringFromFormat("%s%s\tr%u, r%u, r%u", opcode_names[opcode], cond_to_str(cond),
682 rd, rn, rm);
683}
684
685std::string ARM_Disasm::DisassemblePKH(u32 insn) {
686 u32 cond = BITS(insn, 28, 31);
687 u32 rn = BITS(insn, 16, 19);
688 u32 rd = BITS(insn, 12, 15);
689 u32 imm5 = BITS(insn, 7, 11);
690 u32 tb = BIT(insn, 6);
691 u32 rm = BITS(insn, 0, 3);
692
693 std::string suffix = tb ? "tb" : "bt";
694 std::string shift = "";
695
696 if (tb && imm5 == 0)
697 imm5 = 32;
698
699 if (imm5 > 0) {
700 shift = tb ? ", ASR" : ", LSL";
701 shift += " #" + std::to_string(imm5);
702 }
703
704 return Common::StringFromFormat("pkh%s%s\tr%u, r%u, r%u%s", suffix.c_str(), cond_to_str(cond),
705 rd, rn, rm, shift.c_str());
706}
707
708std::string ARM_Disasm::DisassemblePLD(u32 insn) {
709 u8 is_reg = (insn >> 25) & 0x1;
710 u8 is_up = (insn >> 23) & 0x1;
711 u8 rn = (insn >> 16) & 0xf;
712
713 const char* minus = "";
714 if (is_up == 0)
715 minus = "-";
716
717 if (is_reg) {
718 u8 rm = insn & 0xf;
719 return Common::StringFromFormat("pld\t[r%d, %sr%d]", rn, minus, rm);
720 }
721
722 u16 offset = insn & 0xfff;
723 if (offset == 0) {
724 return Common::StringFromFormat("pld\t[r%d]", rn);
725 } else {
726 return Common::StringFromFormat("pld\t[r%d, #%s%u]", rn, minus, offset);
727 }
728}
729
730std::string ARM_Disasm::DisassembleREV(Opcode opcode, u32 insn) {
731 u32 cond = BITS(insn, 28, 31);
732 u32 rd = BITS(insn, 12, 15);
733 u32 rm = BITS(insn, 0, 3);
734
735 return Common::StringFromFormat("%s%s\tr%u, r%u", opcode_names[opcode], cond_to_str(cond), rd,
736 rm);
737}
738
739std::string ARM_Disasm::DisassembleREX(Opcode opcode, u32 insn) {
740 u32 rn = BITS(insn, 16, 19);
741 u32 rd = BITS(insn, 12, 15);
742 u32 rt = BITS(insn, 0, 3);
743 u32 cond = BITS(insn, 28, 31);
744
745 switch (opcode) {
746 case OP_STREX:
747 case OP_STREXB:
748 case OP_STREXH:
749 return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opcode_names[opcode],
750 cond_to_str(cond), rd, rt, rn);
751 case OP_STREXD:
752 return Common::StringFromFormat("%s%s\tr%d, r%d, r%d, [r%d]", opcode_names[opcode],
753 cond_to_str(cond), rd, rt, rt + 1, rn);
754
755 // for LDREX instructions, rd corresponds to Rt from reference manual
756 case OP_LDREX:
757 case OP_LDREXB:
758 case OP_LDREXH:
759 return Common::StringFromFormat("%s%s\tr%d, [r%d]", opcode_names[opcode], cond_to_str(cond),
760 rd, rn);
761 case OP_LDREXD:
762 return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opcode_names[opcode],
763 cond_to_str(cond), rd, rd + 1, rn);
764 default:
765 return opcode_names[OP_UNDEFINED];
766 }
767}
768
769std::string ARM_Disasm::DisassembleSAT(Opcode opcode, u32 insn) {
770 u32 cond = BITS(insn, 28, 31);
771 u32 sat_imm = BITS(insn, 16, 20);
772 u32 rd = BITS(insn, 12, 15);
773 u32 imm5 = BITS(insn, 7, 11);
774 u32 sh = BIT(insn, 6);
775 u32 rn = BITS(insn, 0, 3);
776
777 std::string shift_part = "";
778 bool opcode_has_shift = (opcode == OP_SSAT) || (opcode == OP_USAT);
779 if (opcode_has_shift && !(sh == 0 && imm5 == 0)) {
780 if (sh == 0)
781 shift_part += ", LSL #";
782 else
783 shift_part += ", ASR #";
784
785 if (imm5 == 0)
786 imm5 = 32;
787 shift_part += std::to_string(imm5);
788 }
789
790 if (opcode == OP_SSAT || opcode == OP_SSAT16)
791 sat_imm++;
792
793 return Common::StringFromFormat("%s%s\tr%u, #%u, r%u%s", opcode_names[opcode],
794 cond_to_str(cond), rd, sat_imm, rn, shift_part.c_str());
795}
796
797std::string ARM_Disasm::DisassembleSEL(u32 insn) {
798 u32 cond = BITS(insn, 28, 31);
799 u32 rn = BITS(insn, 16, 19);
800 u32 rd = BITS(insn, 12, 15);
801 u32 rm = BITS(insn, 0, 3);
802
803 return Common::StringFromFormat("%s%s\tr%u, r%u, r%u", opcode_names[OP_SEL], cond_to_str(cond),
804 rd, rn, rm);
805}
806
807std::string ARM_Disasm::DisassembleSWI(u32 insn) {
808 u8 cond = (insn >> 28) & 0xf;
809 u32 sysnum = insn & 0x00ffffff;
810
811 return Common::StringFromFormat("swi%s 0x%x", cond_to_str(cond), sysnum);
812}
813
814std::string ARM_Disasm::DisassembleSWP(Opcode opcode, u32 insn) {
815 u8 cond = (insn >> 28) & 0xf;
816 u8 rn = (insn >> 16) & 0xf;
817 u8 rd = (insn >> 12) & 0xf;
818 u8 rm = insn & 0xf;
819
820 const char* opname = opcode_names[opcode];
821 return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opname, cond_to_str(cond), rd, rm, rn);
822}
823
824std::string ARM_Disasm::DisassembleXT(Opcode opcode, u32 insn) {
825 u32 cond = BITS(insn, 28, 31);
826 u32 rn = BITS(insn, 16, 19);
827 u32 rd = BITS(insn, 12, 15);
828 u32 rotate = BITS(insn, 10, 11);
829 u32 rm = BITS(insn, 0, 3);
830
831 std::string rn_part = "";
832 static std::unordered_set<Opcode, std::hash<int>> extend_with_add = {
833 OP_SXTAB, OP_SXTAB16, OP_SXTAH, OP_UXTAB, OP_UXTAB16, OP_UXTAH};
834 if (extend_with_add.find(opcode) != extend_with_add.end())
835 rn_part = ", r" + std::to_string(rn);
836
837 std::string rotate_part = "";
838 if (rotate != 0)
839 rotate_part = ", ROR #" + std::to_string(rotate << 3);
840
841 return Common::StringFromFormat("%s%s\tr%u%s, r%u%s", opcode_names[opcode], cond_to_str(cond),
842 rd, rn_part.c_str(), rm, rotate_part.c_str());
843}
844
845Opcode ARM_Disasm::Decode(u32 insn) {
846 u32 bits27_26 = (insn >> 26) & 0x3;
847 switch (bits27_26) {
848 case 0x0:
849 return Decode00(insn);
850 case 0x1:
851 return Decode01(insn);
852 case 0x2:
853 return Decode10(insn);
854 case 0x3:
855 return Decode11(insn);
856 }
857 return OP_INVALID;
858}
859
860Opcode ARM_Disasm::Decode00(u32 insn) {
861 u8 bit25 = (insn >> 25) & 0x1;
862 u8 bit4 = (insn >> 4) & 0x1;
863 if (bit25 == 0 && bit4 == 1) {
864 if ((insn & 0x0ffffff0) == 0x012fff10) {
865 // Bx instruction
866 return OP_BX;
867 }
868 if ((insn & 0x0ff000f0) == 0x01600010) {
869 // Clz instruction
870 return OP_CLZ;
871 }
872 if ((insn & 0xfff000f0) == 0xe1200070) {
873 // Bkpt instruction
874 return OP_BKPT;
875 }
876 u32 bits7_4 = (insn >> 4) & 0xf;
877 if (bits7_4 == 0x9) {
878 u32 bit24 = BIT(insn, 24);
879 if (bit24) {
880 return DecodeSyncPrimitive(insn);
881 }
882 // One of the multiply instructions
883 return DecodeMUL(insn);
884 }
885
886 u8 bit7 = (insn >> 7) & 0x1;
887 if (bit7 == 1) {
888 // One of the load/store halfword/byte instructions
889 return DecodeLDRH(insn);
890 }
891 }
892
893 u32 op1 = BITS(insn, 20, 24);
894 if (bit25 && (op1 == 0x12 || op1 == 0x16)) {
895 // One of the MSR (immediate) and hints instructions
896 return DecodeMSRImmAndHints(insn);
897 }
898
899 // One of the data processing instructions
900 return DecodeALU(insn);
901}
902
903Opcode ARM_Disasm::Decode01(u32 insn) {
904 u8 is_reg = (insn >> 25) & 0x1;
905 u8 bit4 = (insn >> 4) & 0x1;
906 if (is_reg == 1 && bit4 == 1)
907 return DecodeMedia(insn);
908 u8 is_load = (insn >> 20) & 0x1;
909 u8 is_byte = (insn >> 22) & 0x1;
910 if ((insn & 0xfd70f000) == 0xf550f000) {
911 // Pre-load
912 return OP_PLD;
913 }
914 if (insn == 0xf57ff01f) {
915 // Clear-Exclusive
916 return OP_CLREX;
917 }
918 if (is_load) {
919 if (is_byte) {
920 // Load byte
921 return OP_LDRB;
922 }
923 // Load word
924 return OP_LDR;
925 }
926 if (is_byte) {
927 // Store byte
928 return OP_STRB;
929 }
930 // Store word
931 return OP_STR;
932}
933
934Opcode ARM_Disasm::Decode10(u32 insn) {
935 u8 bit25 = (insn >> 25) & 0x1;
936 if (bit25 == 0) {
937 // LDM/STM
938 u8 is_load = (insn >> 20) & 0x1;
939 if (is_load)
940 return OP_LDM;
941 return OP_STM;
942 }
943
944 // Branch with link
945 if ((insn >> 24) & 1)
946 return OP_BL;
947
948 return OP_B;
949}
950
951Opcode ARM_Disasm::Decode11(u32 insn) {
952 u8 bit25 = (insn >> 25) & 0x1;
953 if (bit25 == 0) {
954 // LDC, SDC
955 u8 is_load = (insn >> 20) & 0x1;
956 if (is_load) {
957 // LDC
958 return OP_LDC;
959 }
960 // STC
961 return OP_STC;
962 }
963
964 u8 bit24 = (insn >> 24) & 0x1;
965 if (bit24 == 0x1) {
966 // SWI
967 return OP_SWI;
968 }
969
970 u8 bit4 = (insn >> 4) & 0x1;
971 u8 cpnum = (insn >> 8) & 0xf;
972
973 if (cpnum == 15) {
974 // Special case for coprocessor 15
975 u8 opcode = (insn >> 21) & 0x7;
976 if (bit4 == 0 || opcode != 0) {
977 // This is an unexpected bit pattern. Create an undefined
978 // instruction in case this is ever executed.
979 return OP_UNDEFINED;
980 }
981
982 // MRC, MCR
983 u8 is_mrc = (insn >> 20) & 0x1;
984 if (is_mrc)
985 return OP_MRC;
986 return OP_MCR;
987 }
988
989 if (bit4 == 0) {
990 // CDP
991 return OP_CDP;
992 }
993 // MRC, MCR
994 u8 is_mrc = (insn >> 20) & 0x1;
995 if (is_mrc)
996 return OP_MRC;
997 return OP_MCR;
998}
999
1000Opcode ARM_Disasm::DecodeSyncPrimitive(u32 insn) {
1001 u32 op = BITS(insn, 20, 23);
1002 u32 bit22 = BIT(insn, 22);
1003 switch (op) {
1004 case 0x0:
1005 if (bit22)
1006 return OP_SWPB;
1007 return OP_SWP;
1008 case 0x8:
1009 return OP_STREX;
1010 case 0x9:
1011 return OP_LDREX;
1012 case 0xA:
1013 return OP_STREXD;
1014 case 0xB:
1015 return OP_LDREXD;
1016 case 0xC:
1017 return OP_STREXB;
1018 case 0xD:
1019 return OP_LDREXB;
1020 case 0xE:
1021 return OP_STREXH;
1022 case 0xF:
1023 return OP_LDREXH;
1024 default:
1025 return OP_UNDEFINED;
1026 }
1027}
1028
1029Opcode ARM_Disasm::DecodeParallelAddSub(u32 insn) {
1030 u32 op1 = BITS(insn, 20, 21);
1031 u32 op2 = BITS(insn, 5, 7);
1032 u32 is_unsigned = BIT(insn, 22);
1033
1034 if (op1 == 0x0 || op2 == 0x5 || op2 == 0x6)
1035 return OP_UNDEFINED;
1036
1037 // change op1 range from [1, 3] to range [0, 2]
1038 op1--;
1039
1040 // change op2 range from [0, 4] U {7} to range [0, 5]
1041 if (op2 == 0x7)
1042 op2 = 0x5;
1043
1044 static std::vector<Opcode> opcodes = {
1045 // op1 = 0
1046 OP_SADD16, OP_UADD16, OP_SASX, OP_UASX, OP_SSAX, OP_USAX, OP_SSUB16, OP_USUB16, OP_SADD8,
1047 OP_UADD8, OP_SSUB8, OP_USUB8,
1048 // op1 = 1
1049 OP_QADD16, OP_UQADD16, OP_QASX, OP_UQASX, OP_QSAX, OP_UQSAX, OP_QSUB16, OP_UQSUB16,
1050 OP_QADD8, OP_UQADD8, OP_QSUB8, OP_UQSUB8,
1051 // op1 = 2
1052 OP_SHADD16, OP_UHADD16, OP_SHASX, OP_UHASX, OP_SHSAX, OP_UHSAX, OP_SHSUB16, OP_UHSUB16,
1053 OP_SHADD8, OP_UHADD8, OP_SHSUB8, OP_UHSUB8};
1054
1055 u32 opcode_index = op1 * 12 + op2 * 2 + is_unsigned;
1056 return opcodes[opcode_index];
1057}
1058
1059Opcode ARM_Disasm::DecodePackingSaturationReversal(u32 insn) {
1060 u32 op1 = BITS(insn, 20, 22);
1061 u32 a = BITS(insn, 16, 19);
1062 u32 op2 = BITS(insn, 5, 7);
1063
1064 switch (op1) {
1065 case 0x0:
1066 if (BIT(op2, 0) == 0)
1067 return OP_PKH;
1068 if (op2 == 0x3 && a != 0xf)
1069 return OP_SXTAB16;
1070 if (op2 == 0x3 && a == 0xf)
1071 return OP_SXTB16;
1072 if (op2 == 0x5)
1073 return OP_SEL;
1074 break;
1075 case 0x2:
1076 if (BIT(op2, 0) == 0)
1077 return OP_SSAT;
1078 if (op2 == 0x1)
1079 return OP_SSAT16;
1080 if (op2 == 0x3 && a != 0xf)
1081 return OP_SXTAB;
1082 if (op2 == 0x3 && a == 0xf)
1083 return OP_SXTB;
1084 break;
1085 case 0x3:
1086 if (op2 == 0x1)
1087 return OP_REV;
1088 if (BIT(op2, 0) == 0)
1089 return OP_SSAT;
1090 if (op2 == 0x3 && a != 0xf)
1091 return OP_SXTAH;
1092 if (op2 == 0x3 && a == 0xf)
1093 return OP_SXTH;
1094 if (op2 == 0x5)
1095 return OP_REV16;
1096 break;
1097 case 0x4:
1098 if (op2 == 0x3 && a != 0xf)
1099 return OP_UXTAB16;
1100 if (op2 == 0x3 && a == 0xf)
1101 return OP_UXTB16;
1102 break;
1103 case 0x6:
1104 if (BIT(op2, 0) == 0)
1105 return OP_USAT;
1106 if (op2 == 0x1)
1107 return OP_USAT16;
1108 if (op2 == 0x3 && a != 0xf)
1109 return OP_UXTAB;
1110 if (op2 == 0x3 && a == 0xf)
1111 return OP_UXTB;
1112 break;
1113 case 0x7:
1114 if (BIT(op2, 0) == 0)
1115 return OP_USAT;
1116 if (op2 == 0x3 && a != 0xf)
1117 return OP_UXTAH;
1118 if (op2 == 0x3 && a == 0xf)
1119 return OP_UXTH;
1120 if (op2 == 0x5)
1121 return OP_REVSH;
1122 break;
1123 default:
1124 break;
1125 }
1126
1127 return OP_UNDEFINED;
1128}
1129
1130Opcode ARM_Disasm::DecodeMUL(u32 insn) {
1131 u8 bit24 = (insn >> 24) & 0x1;
1132 if (bit24 != 0) {
1133 // This is an unexpected bit pattern. Create an undefined
1134 // instruction in case this is ever executed.
1135 return OP_UNDEFINED;
1136 }
1137 u8 bit23 = (insn >> 23) & 0x1;
1138 u8 bit22_U = (insn >> 22) & 0x1;
1139 u8 bit21_A = (insn >> 21) & 0x1;
1140 if (bit23 == 0) {
1141 // 32-bit multiply
1142 if (bit22_U != 0) {
1143 // This is an unexpected bit pattern. Create an undefined
1144 // instruction in case this is ever executed.
1145 return OP_UNDEFINED;
1146 }
1147 if (bit21_A == 0)
1148 return OP_MUL;
1149 return OP_MLA;
1150 }
1151 // 64-bit multiply
1152 if (bit22_U == 0) {
1153 // Unsigned multiply long
1154 if (bit21_A == 0)
1155 return OP_UMULL;
1156 return OP_UMLAL;
1157 }
1158 // Signed multiply long
1159 if (bit21_A == 0)
1160 return OP_SMULL;
1161 return OP_SMLAL;
1162}
1163
1164Opcode ARM_Disasm::DecodeMSRImmAndHints(u32 insn) {
1165 u32 op = BIT(insn, 22);
1166 u32 op1 = BITS(insn, 16, 19);
1167 u32 op2 = BITS(insn, 0, 7);
1168
1169 if (op == 0 && op1 == 0) {
1170 switch (op2) {
1171 case 0x0:
1172 return OP_NOP;
1173 case 0x1:
1174 return OP_YIELD;
1175 case 0x2:
1176 return OP_WFE;
1177 case 0x3:
1178 return OP_WFI;
1179 case 0x4:
1180 return OP_SEV;
1181 default:
1182 return OP_UNDEFINED;
1183 }
1184 }
1185
1186 return OP_MSR;
1187}
1188
1189Opcode ARM_Disasm::DecodeMediaMulDiv(u32 insn) {
1190 u32 op1 = BITS(insn, 20, 22);
1191 u32 op2_h = BITS(insn, 6, 7);
1192 u32 a = BITS(insn, 12, 15);
1193
1194 switch (op1) {
1195 case 0x0:
1196 if (op2_h == 0x0) {
1197 if (a != 0xf)
1198 return OP_SMLAD;
1199 else
1200 return OP_SMUAD;
1201 } else if (op2_h == 0x1) {
1202 if (a != 0xf)
1203 return OP_SMLSD;
1204 else
1205 return OP_SMUSD;
1206 }
1207 break;
1208 case 0x4:
1209 if (op2_h == 0x0)
1210 return OP_SMLALD;
1211 else if (op2_h == 0x1)
1212 return OP_SMLSLD;
1213 break;
1214 case 0x5:
1215 if (op2_h == 0x0) {
1216 if (a != 0xf)
1217 return OP_SMMLA;
1218 else
1219 return OP_SMMUL;
1220 } else if (op2_h == 0x3) {
1221 return OP_SMMLS;
1222 }
1223 break;
1224 default:
1225 break;
1226 }
1227
1228 return OP_UNDEFINED;
1229}
1230
1231Opcode ARM_Disasm::DecodeMedia(u32 insn) {
1232 u32 op1 = BITS(insn, 20, 24);
1233 u32 rd = BITS(insn, 12, 15);
1234 u32 op2 = BITS(insn, 5, 7);
1235
1236 switch (BITS(op1, 3, 4)) {
1237 case 0x0:
1238 // unsigned and signed parallel addition and subtraction
1239 return DecodeParallelAddSub(insn);
1240 case 0x1:
1241 // Packing, unpacking, saturation, and reversal
1242 return DecodePackingSaturationReversal(insn);
1243 case 0x2:
1244 // Signed multiply, signed and unsigned divide
1245 return DecodeMediaMulDiv(insn);
1246 case 0x3:
1247 if (op2 == 0 && rd == 0xf)
1248 return OP_USAD8;
1249 if (op2 == 0 && rd != 0xf)
1250 return OP_USADA8;
1251 break;
1252 default:
1253 break;
1254 }
1255
1256 return OP_UNDEFINED;
1257}
1258
1259Opcode ARM_Disasm::DecodeLDRH(u32 insn) {
1260 u8 is_load = (insn >> 20) & 0x1;
1261 u8 bits_65 = (insn >> 5) & 0x3;
1262 if (is_load) {
1263 if (bits_65 == 0x1) {
1264 // Load unsigned halfword
1265 return OP_LDRH;
1266 } else if (bits_65 == 0x2) {
1267 // Load signed byte
1268 return OP_LDRSB;
1269 }
1270 // Signed halfword
1271 if (bits_65 != 0x3) {
1272 // This is an unexpected bit pattern. Create an undefined
1273 // instruction in case this is ever executed.
1274 return OP_UNDEFINED;
1275 }
1276 // Load signed halfword
1277 return OP_LDRSH;
1278 }
1279 // Store halfword
1280 if (bits_65 != 0x1) {
1281 // This is an unexpected bit pattern. Create an undefined
1282 // instruction in case this is ever executed.
1283 return OP_UNDEFINED;
1284 }
1285 // Store halfword
1286 return OP_STRH;
1287}
1288
1289Opcode ARM_Disasm::DecodeALU(u32 insn) {
1290 u8 is_immed = (insn >> 25) & 0x1;
1291 u8 opcode = (insn >> 21) & 0xf;
1292 u8 bit_s = (insn >> 20) & 1;
1293 u8 shift_is_reg = (insn >> 4) & 1;
1294 u8 bit7 = (insn >> 7) & 1;
1295 if (!is_immed && shift_is_reg && (bit7 != 0)) {
1296 // This is an unexpected bit pattern. Create an undefined
1297 // instruction in case this is ever executed.
1298 return OP_UNDEFINED;
1299 }
1300 switch (opcode) {
1301 case 0x0:
1302 return OP_AND;
1303 case 0x1:
1304 return OP_EOR;
1305 case 0x2:
1306 return OP_SUB;
1307 case 0x3:
1308 return OP_RSB;
1309 case 0x4:
1310 return OP_ADD;
1311 case 0x5:
1312 return OP_ADC;
1313 case 0x6:
1314 return OP_SBC;
1315 case 0x7:
1316 return OP_RSC;
1317 case 0x8:
1318 if (bit_s)
1319 return OP_TST;
1320 return OP_MRS;
1321 case 0x9:
1322 if (bit_s)
1323 return OP_TEQ;
1324 return OP_MSR;
1325 case 0xa:
1326 if (bit_s)
1327 return OP_CMP;
1328 return OP_MRS;
1329 case 0xb:
1330 if (bit_s)
1331 return OP_CMN;
1332 return OP_MSR;
1333 case 0xc:
1334 return OP_ORR;
1335 case 0xd:
1336 return OP_MOV;
1337 case 0xe:
1338 return OP_BIC;
1339 case 0xf:
1340 return OP_MVN;
1341 }
1342 // Unreachable
1343 return OP_INVALID;
1344}
diff --git a/src/core/arm/disassembler/arm_disasm.h b/src/core/arm/disassembler/arm_disasm.h
deleted file mode 100644
index 300e228ed..000000000
--- a/src/core/arm/disassembler/arm_disasm.h
+++ /dev/null
@@ -1,238 +0,0 @@
1// Copyright 2006 The Android Open Source Project
2
3#pragma once
4
5#include <string>
6#include "common/common_types.h"
7
8// Note: this list of opcodes must match the list used to initialize
9// the opflags[] array in opcode.cpp.
10enum Opcode {
11 OP_INVALID,
12 OP_UNDEFINED,
13 OP_ADC,
14 OP_ADD,
15 OP_AND,
16 OP_B,
17 OP_BL,
18 OP_BIC,
19 OP_BKPT,
20 OP_BLX,
21 OP_BX,
22 OP_CDP,
23 OP_CLREX,
24 OP_CLZ,
25 OP_CMN,
26 OP_CMP,
27 OP_EOR,
28 OP_LDC,
29 OP_LDM,
30 OP_LDR,
31 OP_LDRB,
32 OP_LDRBT,
33 OP_LDREX,
34 OP_LDREXB,
35 OP_LDREXD,
36 OP_LDREXH,
37 OP_LDRH,
38 OP_LDRSB,
39 OP_LDRSH,
40 OP_LDRT,
41 OP_MCR,
42 OP_MLA,
43 OP_MOV,
44 OP_MRC,
45 OP_MRS,
46 OP_MSR,
47 OP_MUL,
48 OP_MVN,
49 OP_NOP,
50 OP_ORR,
51 OP_PKH,
52 OP_PLD,
53 OP_QADD16,
54 OP_QADD8,
55 OP_QASX,
56 OP_QSAX,
57 OP_QSUB16,
58 OP_QSUB8,
59 OP_REV,
60 OP_REV16,
61 OP_REVSH,
62 OP_RSB,
63 OP_RSC,
64 OP_SADD16,
65 OP_SADD8,
66 OP_SASX,
67 OP_SBC,
68 OP_SEL,
69 OP_SEV,
70 OP_SHADD16,
71 OP_SHADD8,
72 OP_SHASX,
73 OP_SHSAX,
74 OP_SHSUB16,
75 OP_SHSUB8,
76 OP_SMLAD,
77 OP_SMLAL,
78 OP_SMLALD,
79 OP_SMLSD,
80 OP_SMLSLD,
81 OP_SMMLA,
82 OP_SMMLS,
83 OP_SMMUL,
84 OP_SMUAD,
85 OP_SMULL,
86 OP_SMUSD,
87 OP_SSAT,
88 OP_SSAT16,
89 OP_SSAX,
90 OP_SSUB16,
91 OP_SSUB8,
92 OP_STC,
93 OP_STM,
94 OP_STR,
95 OP_STRB,
96 OP_STRBT,
97 OP_STREX,
98 OP_STREXB,
99 OP_STREXD,
100 OP_STREXH,
101 OP_STRH,
102 OP_STRT,
103 OP_SUB,
104 OP_SWI,
105 OP_SWP,
106 OP_SWPB,
107 OP_SXTAB,
108 OP_SXTAB16,
109 OP_SXTAH,
110 OP_SXTB,
111 OP_SXTB16,
112 OP_SXTH,
113 OP_TEQ,
114 OP_TST,
115 OP_UADD16,
116 OP_UADD8,
117 OP_UASX,
118 OP_UHADD16,
119 OP_UHADD8,
120 OP_UHASX,
121 OP_UHSAX,
122 OP_UHSUB16,
123 OP_UHSUB8,
124 OP_UMLAL,
125 OP_UMULL,
126 OP_UQADD16,
127 OP_UQADD8,
128 OP_UQASX,
129 OP_UQSAX,
130 OP_UQSUB16,
131 OP_UQSUB8,
132 OP_USAD8,
133 OP_USADA8,
134 OP_USAT,
135 OP_USAT16,
136 OP_USAX,
137 OP_USUB16,
138 OP_USUB8,
139 OP_UXTAB,
140 OP_UXTAB16,
141 OP_UXTAH,
142 OP_UXTB,
143 OP_UXTB16,
144 OP_UXTH,
145 OP_WFE,
146 OP_WFI,
147 OP_YIELD,
148
149 // Define thumb opcodes
150 OP_THUMB_UNDEFINED,
151 OP_THUMB_ADC,
152 OP_THUMB_ADD,
153 OP_THUMB_AND,
154 OP_THUMB_ASR,
155 OP_THUMB_B,
156 OP_THUMB_BIC,
157 OP_THUMB_BKPT,
158 OP_THUMB_BL,
159 OP_THUMB_BLX,
160 OP_THUMB_BX,
161 OP_THUMB_CMN,
162 OP_THUMB_CMP,
163 OP_THUMB_EOR,
164 OP_THUMB_LDMIA,
165 OP_THUMB_LDR,
166 OP_THUMB_LDRB,
167 OP_THUMB_LDRH,
168 OP_THUMB_LDRSB,
169 OP_THUMB_LDRSH,
170 OP_THUMB_LSL,
171 OP_THUMB_LSR,
172 OP_THUMB_MOV,
173 OP_THUMB_MUL,
174 OP_THUMB_MVN,
175 OP_THUMB_NEG,
176 OP_THUMB_ORR,
177 OP_THUMB_POP,
178 OP_THUMB_PUSH,
179 OP_THUMB_ROR,
180 OP_THUMB_SBC,
181 OP_THUMB_STMIA,
182 OP_THUMB_STR,
183 OP_THUMB_STRB,
184 OP_THUMB_STRH,
185 OP_THUMB_SUB,
186 OP_THUMB_SWI,
187 OP_THUMB_TST,
188
189 OP_END // must be last
190};
191
192class ARM_Disasm {
193public:
194 static std::string Disassemble(u32 addr, u32 insn);
195 static Opcode Decode(u32 insn);
196
197private:
198 static Opcode Decode00(u32 insn);
199 static Opcode Decode01(u32 insn);
200 static Opcode Decode10(u32 insn);
201 static Opcode Decode11(u32 insn);
202 static Opcode DecodeSyncPrimitive(u32 insn);
203 static Opcode DecodeParallelAddSub(u32 insn);
204 static Opcode DecodePackingSaturationReversal(u32 insn);
205 static Opcode DecodeMUL(u32 insn);
206 static Opcode DecodeMSRImmAndHints(u32 insn);
207 static Opcode DecodeMediaMulDiv(u32 insn);
208 static Opcode DecodeMedia(u32 insn);
209 static Opcode DecodeLDRH(u32 insn);
210 static Opcode DecodeALU(u32 insn);
211
212 static std::string DisassembleALU(Opcode opcode, u32 insn);
213 static std::string DisassembleBranch(u32 addr, Opcode opcode, u32 insn);
214 static std::string DisassembleBX(u32 insn);
215 static std::string DisassembleBKPT(u32 insn);
216 static std::string DisassembleCLZ(u32 insn);
217 static std::string DisassembleMediaMulDiv(Opcode opcode, u32 insn);
218 static std::string DisassembleMemblock(Opcode opcode, u32 insn);
219 static std::string DisassembleMem(u32 insn);
220 static std::string DisassembleMemHalf(u32 insn);
221 static std::string DisassembleMCR(Opcode opcode, u32 insn);
222 static std::string DisassembleMLA(Opcode opcode, u32 insn);
223 static std::string DisassembleUMLAL(Opcode opcode, u32 insn);
224 static std::string DisassembleMUL(Opcode opcode, u32 insn);
225 static std::string DisassembleMRS(u32 insn);
226 static std::string DisassembleMSR(u32 insn);
227 static std::string DisassembleNoOperands(Opcode opcode, u32 insn);
228 static std::string DisassembleParallelAddSub(Opcode opcode, u32 insn);
229 static std::string DisassemblePKH(u32 insn);
230 static std::string DisassemblePLD(u32 insn);
231 static std::string DisassembleREV(Opcode opcode, u32 insn);
232 static std::string DisassembleREX(Opcode opcode, u32 insn);
233 static std::string DisassembleSAT(Opcode opcode, u32 insn);
234 static std::string DisassembleSEL(u32 insn);
235 static std::string DisassembleSWI(u32 insn);
236 static std::string DisassembleSWP(Opcode opcode, u32 insn);
237 static std::string DisassembleXT(Opcode opcode, u32 insn);
238};
diff --git a/src/core/arm/disassembler/load_symbol_map.cpp b/src/core/arm/disassembler/load_symbol_map.cpp
deleted file mode 100644
index 6863c103a..000000000
--- a/src/core/arm/disassembler/load_symbol_map.cpp
+++ /dev/null
@@ -1,31 +0,0 @@
1// Copyright 2014 Citra Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#include <sstream>
6#include <string>
7#include <vector>
8#include "common/file_util.h"
9#include "common/symbols.h"
10#include "core/arm/disassembler/load_symbol_map.h"
11
12/*
13 * Loads a symbol map file for use with the disassembler
14 * @param filename String filename path of symbol map file
15 */
16void LoadSymbolMap(std::string filename) {
17 std::ifstream infile(filename);
18
19 std::string address_str, function_name, line;
20 u32 size;
21
22 while (std::getline(infile, line)) {
23 std::istringstream iss(line);
24 if (!(iss >> address_str >> size >> function_name)) {
25 break; // Error parsing
26 }
27 u32 address = std::stoul(address_str, nullptr, 16);
28
29 Symbols::Add(address, function_name, size, 2);
30 }
31}
diff --git a/src/core/arm/disassembler/load_symbol_map.h b/src/core/arm/disassembler/load_symbol_map.h
deleted file mode 100644
index d28c551c3..000000000
--- a/src/core/arm/disassembler/load_symbol_map.h
+++ /dev/null
@@ -1,13 +0,0 @@
1// Copyright 2014 Citra Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#pragma once
6
7#include <string>
8
9/*
10 * Loads a symbol map file for use with the disassembler
11 * @param filename String filename path of symbol map file
12 */
13void LoadSymbolMap(std::string filename);
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp
index 64dcaae08..dcfcd6561 100644
--- a/src/core/arm/dyncom/arm_dyncom_dec.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp
@@ -415,7 +415,7 @@ const InstructionSetEncodingItem arm_exclusion_code[] = {
415}; 415};
416// clang-format on 416// clang-format on
417 417
418ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx) { 418ARMDecodeStatus DecodeARMInstruction(u32 instr, int* idx) {
419 int n = 0; 419 int n = 0;
420 int base = 0; 420 int base = 0;
421 int instr_slots = sizeof(arm_instruction) / sizeof(InstructionSetEncodingItem); 421 int instr_slots = sizeof(arm_instruction) / sizeof(InstructionSetEncodingItem);
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.h b/src/core/arm/dyncom/arm_dyncom_dec.h
index 2fb7ac37c..1dcf7ecd1 100644
--- a/src/core/arm/dyncom/arm_dyncom_dec.h
+++ b/src/core/arm/dyncom/arm_dyncom_dec.h
@@ -8,7 +8,7 @@
8 8
9enum class ARMDecodeStatus { SUCCESS, FAILURE }; 9enum class ARMDecodeStatus { SUCCESS, FAILURE };
10 10
11ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx); 11ARMDecodeStatus DecodeARMInstruction(u32 instr, int* idx);
12 12
13struct InstructionSetEncodingItem { 13struct InstructionSetEncodingItem {
14 const char* name; 14 const char* name;
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 273bc8167..f4fbb8d04 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -5,11 +5,11 @@
5#define CITRA_IGNORE_EXIT(x) 5#define CITRA_IGNORE_EXIT(x)
6 6
7#include <algorithm> 7#include <algorithm>
8#include <cinttypes>
8#include <cstdio> 9#include <cstdio>
9#include "common/common_types.h" 10#include "common/common_types.h"
10#include "common/logging/log.h" 11#include "common/logging/log.h"
11#include "common/microprofile.h" 12#include "common/microprofile.h"
12#include "core/arm/disassembler/arm_disasm.h"
13#include "core/arm/dyncom/arm_dyncom_dec.h" 13#include "core/arm/dyncom/arm_dyncom_dec.h"
14#include "core/arm/dyncom/arm_dyncom_interpreter.h" 14#include "core/arm/dyncom/arm_dyncom_interpreter.h"
15#include "core/arm/dyncom/arm_dyncom_run.h" 15#include "core/arm/dyncom/arm_dyncom_run.h"
@@ -808,8 +808,8 @@ MICROPROFILE_DEFINE(DynCom_Decode, "DynCom", "Decode", MP_RGB(255, 64, 64));
808 808
809static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, const u32 phys_addr, 809static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, const u32 phys_addr,
810 ARM_INST_PTR& inst_base) { 810 ARM_INST_PTR& inst_base) {
811 unsigned int inst_size = 4; 811 u32 inst_size = 4;
812 unsigned int inst = Memory::Read32(phys_addr & 0xFFFFFFFC); 812 u32 inst = Memory::Read32(phys_addr & 0xFFFFFFFC);
813 813
814 // If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM 814 // If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM
815 // instruction 815 // instruction
@@ -827,11 +827,10 @@ static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, cons
827 827
828 int idx; 828 int idx;
829 if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) { 829 if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) {
830 std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst); 830 LOG_ERROR(Core_ARM11, "Decode failure.\tPC: [0x%08" PRIX32 "]\tInstruction: %08" PRIX32,
831 LOG_ERROR(Core_ARM11, "Decode failure.\tPC : [0x%x]\tInstruction : %s [%x]", phys_addr, 831 phys_addr, inst);
832 disasm.c_str(), inst); 832 LOG_ERROR(Core_ARM11, "cpsr=0x%" PRIX32 ", cpu->TFlag=%d, r15=0x%08" PRIX32, cpu->Cpsr,
833 LOG_ERROR(Core_ARM11, "cpsr=0x%x, cpu->TFlag=%d, r15=0x%x", cpu->Cpsr, cpu->TFlag, 833 cpu->TFlag, cpu->Reg[15]);
834 cpu->Reg[15]);
835 CITRA_IGNORE_EXIT(-1); 834 CITRA_IGNORE_EXIT(-1);
836 } 835 }
837 inst_base = arm_instruction_trans[idx](inst, idx); 836 inst_base = arm_instruction_trans[idx](inst, idx);
diff --git a/src/core/hle/svc.cpp b/src/core/hle/svc.cpp
index 2db823c61..8538cfc9d 100644
--- a/src/core/hle/svc.cpp
+++ b/src/core/hle/svc.cpp
@@ -2,12 +2,12 @@
2// Licensed under GPLv2 or any later version 2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included. 3// Refer to the license.txt file included.
4 4
5#include <cinttypes>
5#include <map> 6#include <map>
6#include "common/logging/log.h" 7#include "common/logging/log.h"
7#include "common/microprofile.h" 8#include "common/microprofile.h"
8#include "common/scope_exit.h" 9#include "common/scope_exit.h"
9#include "common/string_util.h" 10#include "common/string_util.h"
10#include "common/symbols.h"
11#include "core/arm/arm_interface.h" 11#include "core/arm/arm_interface.h"
12#include "core/core_timing.h" 12#include "core/core_timing.h"
13#include "core/hle/function_wrappers.h" 13#include "core/hle/function_wrappers.h"
@@ -524,13 +524,7 @@ static ResultCode CreateThread(Kernel::Handle* out_handle, s32 priority, u32 ent
524 u32 stack_top, s32 processor_id) { 524 u32 stack_top, s32 processor_id) {
525 using Kernel::Thread; 525 using Kernel::Thread;
526 526
527 std::string name; 527 std::string name = Common::StringFromFormat("unknown-%08" PRIX32, entry_point);
528 if (Symbols::HasSymbol(entry_point)) {
529 TSymbol symbol = Symbols::GetSymbol(entry_point);
530 name = symbol.name;
531 } else {
532 name = Common::StringFromFormat("unknown-%08x", entry_point);
533 }
534 528
535 if (priority > THREADPRIO_LOWEST) { 529 if (priority > THREADPRIO_LOWEST) {
536 return ResultCode(ErrorDescription::OutOfRange, ErrorModule::OS, 530 return ResultCode(ErrorDescription::OutOfRange, ErrorModule::OS,
diff --git a/src/core/loader/elf.cpp b/src/core/loader/elf.cpp
index 8eb5200ab..cfcde9167 100644
--- a/src/core/loader/elf.cpp
+++ b/src/core/loader/elf.cpp
@@ -8,7 +8,6 @@
8#include "common/common_types.h" 8#include "common/common_types.h"
9#include "common/file_util.h" 9#include "common/file_util.h"
10#include "common/logging/log.h" 10#include "common/logging/log.h"
11#include "common/symbols.h"
12#include "core/hle/kernel/process.h" 11#include "core/hle/kernel/process.h"
13#include "core/hle/kernel/resource_limit.h" 12#include "core/hle/kernel/resource_limit.h"
14#include "core/loader/elf.h" 13#include "core/loader/elf.h"
@@ -210,7 +209,6 @@ public:
210 return (u32)(header->e_flags); 209 return (u32)(header->e_flags);
211 } 210 }
212 SharedPtr<CodeSet> LoadInto(u32 vaddr); 211 SharedPtr<CodeSet> LoadInto(u32 vaddr);
213 bool LoadSymbols();
214 212
215 int GetNumSegments() const { 213 int GetNumSegments() const {
216 return (int)(header->e_phnum); 214 return (int)(header->e_phnum);
@@ -258,8 +256,6 @@ ElfReader::ElfReader(void* ptr) {
258 sections = (Elf32_Shdr*)(base + header->e_shoff); 256 sections = (Elf32_Shdr*)(base + header->e_shoff);
259 257
260 entryPoint = header->e_entry; 258 entryPoint = header->e_entry;
261
262 LoadSymbols();
263} 259}
264 260
265const char* ElfReader::GetSectionName(int section) const { 261const char* ElfReader::GetSectionName(int section) const {
@@ -362,34 +358,6 @@ SectionID ElfReader::GetSectionByName(const char* name, int firstSection) const
362 return -1; 358 return -1;
363} 359}
364 360
365bool ElfReader::LoadSymbols() {
366 bool hasSymbols = false;
367 SectionID sec = GetSectionByName(".symtab");
368 if (sec != -1) {
369 int stringSection = sections[sec].sh_link;
370 const char* stringBase = reinterpret_cast<const char*>(GetSectionDataPtr(stringSection));
371
372 // We have a symbol table!
373 const Elf32_Sym* symtab = reinterpret_cast<const Elf32_Sym*>(GetSectionDataPtr(sec));
374 unsigned int numSymbols = sections[sec].sh_size / sizeof(Elf32_Sym);
375 for (unsigned sym = 0; sym < numSymbols; sym++) {
376 int size = symtab[sym].st_size;
377 if (size == 0)
378 continue;
379
380 int type = symtab[sym].st_info & 0xF;
381
382 const char* name = stringBase + symtab[sym].st_name;
383
384 Symbols::Add(symtab[sym].st_value, name, size, type);
385
386 hasSymbols = true;
387 }
388 }
389
390 return hasSymbols;
391}
392
393//////////////////////////////////////////////////////////////////////////////////////////////////// 361////////////////////////////////////////////////////////////////////////////////////////////////////
394// Loader namespace 362// Loader namespace
395 363
HIC SVNT DRACONES