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-rw-r--r--src/core/arm/interpreter/armemu.cpp18
1 files changed, 12 insertions, 6 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index 71cae3db0..de178a890 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -3103,12 +3103,18 @@ mainswitch:
3103 state->Reg[idest] = (state->Reg[rfis] & 0xFFFF) | ((state->Reg[rlast] << ishi) & 0xFFFF0000); 3103 state->Reg[idest] = (state->Reg[rfis] & 0xFFFF) | ((state->Reg[rlast] << ishi) & 0xFFFF0000);
3104 break; 3104 break;
3105 } else if ((instr & 0x70) == 0x50) { //pkhtb 3105 } else if ((instr & 0x70) == 0x50) { //pkhtb
3106 u8 idest = BITS(12, 15); 3106 const u8 rd_idx = BITS(12, 15);
3107 u8 rfis = BITS(16, 19); 3107 const u8 rn_idx = BITS(16, 19);
3108 u8 rlast = BITS(0, 3); 3108 const u8 rm_idx = BITS(0, 3);
3109 u8 ishi = BITS(7, 11); 3109 const u8 imm5 = BITS(7, 11);
3110 if (ishi == 0)ishi = 0x20; 3110
3111 state->Reg[idest] = (((int)(state->Reg[rlast]) >> (int)(ishi))& 0xFFFF) | ((state->Reg[rfis]) & 0xFFFF0000); 3111 ARMword val;
3112 if (imm5 >= 32)
3113 val = (state->Reg[rm_idx] >> 31);
3114 else
3115 val = (state->Reg[rm_idx] >> imm5);
3116
3117 state->Reg[rd_idx] = (val & 0xFFFF) | ((state->Reg[rn_idx]) & 0xFFFF0000);
3112 break; 3118 break;
3113 } else if (BIT (4)) { 3119 } else if (BIT (4)) {
3114#ifdef MODE32 3120#ifdef MODE32