diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 24 | ||||
| -rw-r--r-- | src/video_core/renderer_opengl/gl_shader_decompiler.cpp | 61 |
2 files changed, 84 insertions, 1 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 625ecdfcd..96b745db8 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h | |||
| @@ -213,6 +213,18 @@ enum class XmadMode : u64 { | |||
| 213 | CBcc = 4, | 213 | CBcc = 4, |
| 214 | }; | 214 | }; |
| 215 | 215 | ||
| 216 | enum class IAdd3Mode : u64 { | ||
| 217 | None = 0, | ||
| 218 | RightShift = 1, | ||
| 219 | LeftShift = 2, | ||
| 220 | }; | ||
| 221 | |||
| 222 | enum class IAdd3Height : u64 { | ||
| 223 | None = 0, | ||
| 224 | LowerHalfWord = 1, | ||
| 225 | UpperHalfWord = 2, | ||
| 226 | }; | ||
| 227 | |||
| 216 | enum class FlowCondition : u64 { | 228 | enum class FlowCondition : u64 { |
| 217 | Always = 0xF, | 229 | Always = 0xF, |
| 218 | Fcsm_Tr = 0x1C, // TODO(bunnei): What is this used for? | 230 | Fcsm_Tr = 0x1C, // TODO(bunnei): What is this used for? |
| @@ -339,6 +351,16 @@ union Instruction { | |||
| 339 | } imnmx; | 351 | } imnmx; |
| 340 | 352 | ||
| 341 | union { | 353 | union { |
| 354 | BitField<31, 2, IAdd3Height> height_c; | ||
| 355 | BitField<33, 2, IAdd3Height> height_b; | ||
| 356 | BitField<35, 2, IAdd3Height> height_a; | ||
| 357 | BitField<37, 2, IAdd3Mode> mode; | ||
| 358 | BitField<49, 1, u64> neg_c; | ||
| 359 | BitField<50, 1, u64> neg_b; | ||
| 360 | BitField<51, 1, u64> neg_a; | ||
| 361 | } iadd3; | ||
| 362 | |||
| 363 | union { | ||
| 342 | BitField<54, 1, u64> saturate; | 364 | BitField<54, 1, u64> saturate; |
| 343 | BitField<56, 1, u64> negate_a; | 365 | BitField<56, 1, u64> negate_a; |
| 344 | } iadd32i; | 366 | } iadd32i; |
| @@ -636,7 +658,7 @@ public: | |||
| 636 | IADD_C, | 658 | IADD_C, |
| 637 | IADD_R, | 659 | IADD_R, |
| 638 | IADD_IMM, | 660 | IADD_IMM, |
| 639 | IADD3_C, | 661 | IADD3_C, // Add 3 Integers |
| 640 | IADD3_R, | 662 | IADD3_R, |
| 641 | IADD3_IMM, | 663 | IADD3_IMM, |
| 642 | IADD32I, | 664 | IADD32I, |
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp index 94e318966..7e5ebfe24 100644 --- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp +++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp | |||
| @@ -1287,6 +1287,67 @@ private: | |||
| 1287 | instr.alu.saturate_d); | 1287 | instr.alu.saturate_d); |
| 1288 | break; | 1288 | break; |
| 1289 | } | 1289 | } |
| 1290 | case OpCode::Id::IADD3_C: | ||
| 1291 | case OpCode::Id::IADD3_R: | ||
| 1292 | case OpCode::Id::IADD3_IMM: { | ||
| 1293 | std::string op_c = regs.GetRegisterAsInteger(instr.gpr39); | ||
| 1294 | |||
| 1295 | auto apply_height = [](auto height, auto& oprand) { | ||
| 1296 | switch (height) { | ||
| 1297 | case Tegra::Shader::IAdd3Height::None: | ||
| 1298 | break; | ||
| 1299 | case Tegra::Shader::IAdd3Height::LowerHalfWord: | ||
| 1300 | oprand = "((" + oprand + ") & 0xFFFF)"; | ||
| 1301 | break; | ||
| 1302 | case Tegra::Shader::IAdd3Height::UpperHalfWord: | ||
| 1303 | oprand = "((" + oprand + ") >> 16)"; | ||
| 1304 | break; | ||
| 1305 | default: | ||
| 1306 | LOG_CRITICAL(HW_GPU, "Unhandled IADD3 height: {}", | ||
| 1307 | static_cast<u32>(height.Value())); | ||
| 1308 | UNREACHABLE(); | ||
| 1309 | } | ||
| 1310 | }; | ||
| 1311 | |||
| 1312 | if (opcode->GetId() == OpCode::Id::IADD3_R) { | ||
| 1313 | apply_height(instr.iadd3.height_a, op_a); | ||
| 1314 | apply_height(instr.iadd3.height_b, op_b); | ||
| 1315 | apply_height(instr.iadd3.height_c, op_c); | ||
| 1316 | } | ||
| 1317 | |||
| 1318 | if (instr.iadd3.neg_a) | ||
| 1319 | op_a = "-(" + op_a + ')'; | ||
| 1320 | |||
| 1321 | if (instr.iadd3.neg_b) | ||
| 1322 | op_b = "-(" + op_b + ')'; | ||
| 1323 | |||
| 1324 | if (instr.iadd3.neg_c) | ||
| 1325 | op_c = "-(" + op_c + ')'; | ||
| 1326 | |||
| 1327 | std::string result; | ||
| 1328 | if (opcode->GetId() == OpCode::Id::IADD3_R) { | ||
| 1329 | switch (instr.iadd3.mode) { | ||
| 1330 | case Tegra::Shader::IAdd3Mode::RightShift: | ||
| 1331 | // TODO(tech4me): According to | ||
| 1332 | // https://envytools.readthedocs.io/en/latest/hw/graph/maxwell/cuda/int.html?highlight=iadd3 | ||
| 1333 | // The addition between op_a and op_b should be done in uint33, more | ||
| 1334 | // investigation required | ||
| 1335 | result = "(((" + op_a + " + " + op_b + ") >> 16) + " + op_c + ')'; | ||
| 1336 | break; | ||
| 1337 | case Tegra::Shader::IAdd3Mode::LeftShift: | ||
| 1338 | result = "(((" + op_a + " + " + op_b + ") << 16) + " + op_c + ')'; | ||
| 1339 | break; | ||
| 1340 | default: | ||
| 1341 | result = '(' + op_a + " + " + op_b + " + " + op_c + ')'; | ||
| 1342 | break; | ||
| 1343 | } | ||
| 1344 | } else { | ||
| 1345 | result = '(' + op_a + " + " + op_b + " + " + op_c + ')'; | ||
| 1346 | } | ||
| 1347 | |||
| 1348 | regs.SetRegisterToInteger(instr.gpr0, true, 0, result, 1, 1); | ||
| 1349 | break; | ||
| 1350 | } | ||
| 1290 | case OpCode::Id::ISCADD_C: | 1351 | case OpCode::Id::ISCADD_C: |
| 1291 | case OpCode::Id::ISCADD_R: | 1352 | case OpCode::Id::ISCADD_R: |
| 1292 | case OpCode::Id::ISCADD_IMM: { | 1353 | case OpCode::Id::ISCADD_IMM: { |