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-rw-r--r--src/video_core/engines/shader_bytecode.h30
-rw-r--r--src/video_core/shader/decode/texture.cpp32
-rw-r--r--src/video_core/shader/shader_ir.h4
3 files changed, 55 insertions, 11 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index d3d05a866..8f6bc76eb 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -1238,6 +1238,32 @@ union Instruction {
1238 } tld4; 1238 } tld4;
1239 1239
1240 union { 1240 union {
1241 BitField<35, 1, u64> ndv_flag;
1242 BitField<49, 1, u64> nodep_flag;
1243 BitField<50, 1, u64> dc_flag;
1244 BitField<33, 2, u64> info;
1245 BitField<37, 2, u64> component;
1246
1247 bool UsesMiscMode(TextureMiscMode mode) const {
1248 switch (mode) {
1249 case TextureMiscMode::NDV:
1250 return ndv_flag != 0;
1251 case TextureMiscMode::NODEP:
1252 return nodep_flag != 0;
1253 case TextureMiscMode::DC:
1254 return dc_flag != 0;
1255 case TextureMiscMode::AOFFI:
1256 return info == 1;
1257 case TextureMiscMode::PTP:
1258 return info == 2;
1259 default:
1260 break;
1261 }
1262 return false;
1263 }
1264 } tld4_b;
1265
1266 union {
1241 BitField<49, 1, u64> nodep_flag; 1267 BitField<49, 1, u64> nodep_flag;
1242 BitField<50, 1, u64> dc_flag; 1268 BitField<50, 1, u64> dc_flag;
1243 BitField<51, 1, u64> aoffi_flag; 1269 BitField<51, 1, u64> aoffi_flag;
@@ -1590,7 +1616,8 @@ public:
1590 TEXS, // Texture Fetch with scalar/non-vec4 source/destinations 1616 TEXS, // Texture Fetch with scalar/non-vec4 source/destinations
1591 TLD, // Texture Load 1617 TLD, // Texture Load
1592 TLDS, // Texture Load with scalar/non-vec4 source/destinations 1618 TLDS, // Texture Load with scalar/non-vec4 source/destinations
1593 TLD4, // Texture Load 4 1619 TLD4, // Texture Gather 4
1620 TLD4_B, // Texture Gather 4 Bindless
1594 TLD4S, // Texture Load 4 with scalar / non - vec4 source / destinations 1621 TLD4S, // Texture Load 4 with scalar / non - vec4 source / destinations
1595 TMML_B, // Texture Mip Map Level 1622 TMML_B, // Texture Mip Map Level
1596 TMML, // Texture Mip Map Level 1623 TMML, // Texture Mip Map Level
@@ -1881,6 +1908,7 @@ private:
1881 INST("11011100--11----", Id::TLD, Type::Texture, "TLD"), 1908 INST("11011100--11----", Id::TLD, Type::Texture, "TLD"),
1882 INST("1101-01---------", Id::TLDS, Type::Texture, "TLDS"), 1909 INST("1101-01---------", Id::TLDS, Type::Texture, "TLDS"),
1883 INST("110010----111---", Id::TLD4, Type::Texture, "TLD4"), 1910 INST("110010----111---", Id::TLD4, Type::Texture, "TLD4"),
1911 INST("1101111011111---", Id::TLD4_B, Type::Texture, "TLD4_B"),
1884 INST("1101111100------", Id::TLD4S, Type::Texture, "TLD4S"), 1912 INST("1101111100------", Id::TLD4S, Type::Texture, "TLD4S"),
1885 INST("110111110110----", Id::TMML_B, Type::Texture, "TMML_B"), 1913 INST("110111110110----", Id::TMML_B, Type::Texture, "TMML_B"),
1886 INST("1101111101011---", Id::TMML, Type::Texture, "TMML"), 1914 INST("1101111101011---", Id::TMML, Type::Texture, "TMML"),
diff --git a/src/video_core/shader/decode/texture.cpp b/src/video_core/shader/decode/texture.cpp
index d61e656b7..0599ef34f 100644
--- a/src/video_core/shader/decode/texture.cpp
+++ b/src/video_core/shader/decode/texture.cpp
@@ -96,6 +96,10 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
96 } 96 }
97 break; 97 break;
98 } 98 }
99 case OpCode::Id::TLD4_B: {
100 is_bindless = true;
101 [[fallthrough]];
102 }
99 case OpCode::Id::TLD4: { 103 case OpCode::Id::TLD4: {
100 ASSERT(instr.tld4.array == 0); 104 ASSERT(instr.tld4.array == 0);
101 UNIMPLEMENTED_IF_MSG(instr.tld4.UsesMiscMode(TextureMiscMode::NDV), 105 UNIMPLEMENTED_IF_MSG(instr.tld4.UsesMiscMode(TextureMiscMode::NDV),
@@ -108,11 +112,14 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
108 } 112 }
109 113
110 const auto texture_type = instr.tld4.texture_type.Value(); 114 const auto texture_type = instr.tld4.texture_type.Value();
111 const bool depth_compare = instr.tld4.UsesMiscMode(TextureMiscMode::DC); 115 const bool depth_compare = is_bindless ? instr.tld4_b.UsesMiscMode(TextureMiscMode::DC)
116 : instr.tld4.UsesMiscMode(TextureMiscMode::DC);
112 const bool is_array = instr.tld4.array != 0; 117 const bool is_array = instr.tld4.array != 0;
113 const bool is_aoffi = instr.tld4.UsesMiscMode(TextureMiscMode::AOFFI); 118 const bool is_aoffi = is_bindless ? instr.tld4_b.UsesMiscMode(TextureMiscMode::AOFFI)
119 : instr.tld4.UsesMiscMode(TextureMiscMode::AOFFI);
114 WriteTexInstructionFloat( 120 WriteTexInstructionFloat(
115 bb, instr, GetTld4Code(instr, texture_type, depth_compare, is_array, is_aoffi)); 121 bb, instr,
122 GetTld4Code(instr, texture_type, depth_compare, is_array, is_aoffi, is_bindless), true);
116 break; 123 break;
117 } 124 }
118 case OpCode::Id::TLD4S: { 125 case OpCode::Id::TLD4S: {
@@ -359,10 +366,11 @@ const Sampler& ShaderIR::GetBindlessSampler(const Tegra::Shader::Register& reg,
359 return *used_samplers.emplace(entry).first; 366 return *used_samplers.emplace(entry).first;
360} 367}
361 368
362void ShaderIR::WriteTexInstructionFloat(NodeBlock& bb, Instruction instr, const Node4& components) { 369void ShaderIR::WriteTexInstructionFloat(NodeBlock& bb, Instruction instr, const Node4& components,
370 bool is_tld4) {
363 u32 dest_elem = 0; 371 u32 dest_elem = 0;
364 for (u32 elem = 0; elem < 4; ++elem) { 372 for (u32 elem = 0; elem < 4; ++elem) {
365 if (!instr.tex.IsComponentEnabled(elem)) { 373 if (!is_tld4 && !instr.tex.IsComponentEnabled(elem)) {
366 // Skip disabled components 374 // Skip disabled components
367 continue; 375 continue;
368 } 376 }
@@ -583,7 +591,7 @@ Node4 ShaderIR::GetTexsCode(Instruction instr, TextureType texture_type,
583} 591}
584 592
585Node4 ShaderIR::GetTld4Code(Instruction instr, TextureType texture_type, bool depth_compare, 593Node4 ShaderIR::GetTld4Code(Instruction instr, TextureType texture_type, bool depth_compare,
586 bool is_array, bool is_aoffi) { 594 bool is_array, bool is_aoffi, bool is_bindless) {
587 const std::size_t coord_count = GetCoordCount(texture_type); 595 const std::size_t coord_count = GetCoordCount(texture_type);
588 596
589 // If enabled arrays index is always stored in the gpr8 field 597 // If enabled arrays index is always stored in the gpr8 field
@@ -597,6 +605,12 @@ Node4 ShaderIR::GetTld4Code(Instruction instr, TextureType texture_type, bool de
597 } 605 }
598 606
599 u64 parameter_register = instr.gpr20.Value(); 607 u64 parameter_register = instr.gpr20.Value();
608
609 const auto& sampler =
610 is_bindless
611 ? GetBindlessSampler(parameter_register++, {{texture_type, is_array, depth_compare}})
612 : GetSampler(instr.sampler, {{texture_type, is_array, depth_compare}});
613
600 std::vector<Node> aoffi; 614 std::vector<Node> aoffi;
601 if (is_aoffi) { 615 if (is_aoffi) {
602 aoffi = GetAoffiCoordinates(GetRegister(parameter_register++), coord_count, true); 616 aoffi = GetAoffiCoordinates(GetRegister(parameter_register++), coord_count, true);
@@ -607,12 +621,14 @@ Node4 ShaderIR::GetTld4Code(Instruction instr, TextureType texture_type, bool de
607 dc = GetRegister(parameter_register++); 621 dc = GetRegister(parameter_register++);
608 } 622 }
609 623
610 const auto& sampler = GetSampler(instr.sampler, {{texture_type, is_array, depth_compare}}); 624 const Node component = is_bindless ? Immediate(static_cast<u32>(instr.tld4_b.component))
625 : Immediate(static_cast<u32>(instr.tld4.component));
611 626
612 Node4 values; 627 Node4 values;
613 for (u32 element = 0; element < values.size(); ++element) { 628 for (u32 element = 0; element < values.size(); ++element) {
614 auto coords_copy = coords; 629 auto coords_copy = coords;
615 MetaTexture meta{sampler, GetRegister(array_register), dc, aoffi, {}, {}, {}, element}; 630 MetaTexture meta{sampler, GetRegister(array_register), dc, aoffi, {}, {}, component,
631 element};
616 values[element] = Operation(OperationCode::TextureGather, meta, std::move(coords_copy)); 632 values[element] = Operation(OperationCode::TextureGather, meta, std::move(coords_copy));
617 } 633 }
618 634
diff --git a/src/video_core/shader/shader_ir.h b/src/video_core/shader/shader_ir.h
index 1fd44bde1..7582999a5 100644
--- a/src/video_core/shader/shader_ir.h
+++ b/src/video_core/shader/shader_ir.h
@@ -326,7 +326,7 @@ private:
326 Node BitfieldInsert(Node base, Node insert, u32 offset, u32 bits); 326 Node BitfieldInsert(Node base, Node insert, u32 offset, u32 bits);
327 327
328 void WriteTexInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr, 328 void WriteTexInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr,
329 const Node4& components); 329 const Node4& components, bool is_tld4 = false);
330 330
331 void WriteTexsInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr, 331 void WriteTexsInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr,
332 const Node4& components, bool ignore_mask = false); 332 const Node4& components, bool ignore_mask = false);
@@ -343,7 +343,7 @@ private:
343 bool is_array); 343 bool is_array);
344 344
345 Node4 GetTld4Code(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type, 345 Node4 GetTld4Code(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
346 bool depth_compare, bool is_array, bool is_aoffi); 346 bool depth_compare, bool is_array, bool is_aoffi, bool is_bindless);
347 347
348 Node4 GetTldCode(Tegra::Shader::Instruction instr); 348 Node4 GetTldCode(Tegra::Shader::Instruction instr);
349 349