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-rw-r--r--src/citra_qt/debugger/disassembler.cpp3
-rw-r--r--src/core/CMakeLists.txt7
-rw-r--r--src/core/arm/dyncom/arm_dyncom.cpp13
-rw-r--r--src/core/arm/dyncom/arm_dyncom.h2
-rw-r--r--src/core/arm/dyncom/arm_dyncom_dec.cpp4
-rw-r--r--src/core/arm/dyncom/arm_dyncom_dec.h4
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp12
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.h2
-rw-r--r--src/core/arm/dyncom/arm_dyncom_run.cpp2
-rw-r--r--src/core/arm/dyncom/arm_dyncom_run.h2
-rw-r--r--src/core/arm/dyncom/arm_dyncom_thumb.cpp23
-rw-r--r--src/core/arm/dyncom/arm_dyncom_thumb.h2
-rw-r--r--src/core/arm/skyeye_common/armdefs.h318
-rw-r--r--src/core/arm/skyeye_common/arminit.cpp (renamed from src/core/arm/interpreter/arminit.cpp)34
-rw-r--r--src/core/arm/skyeye_common/armmmu.h3
-rw-r--r--src/core/arm/skyeye_common/armstate.h215
-rw-r--r--src/core/arm/skyeye_common/armsupp.cpp (renamed from src/core/arm/interpreter/armsupp.cpp)9
-rw-r--r--src/core/arm/skyeye_common/armsupp.h40
-rw-r--r--src/core/arm/skyeye_common/vfp/vfp.cpp12
-rw-r--r--src/core/arm/skyeye_common/vfp/vfp.h10
-rw-r--r--src/core/arm/skyeye_common/vfp/vfp_helper.h4
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpdouble.cpp12
-rw-r--r--src/core/hle/kernel/thread.cpp2
23 files changed, 320 insertions, 415 deletions
diff --git a/src/citra_qt/debugger/disassembler.cpp b/src/citra_qt/debugger/disassembler.cpp
index b41c40a0e..1e5ef5299 100644
--- a/src/citra_qt/debugger/disassembler.cpp
+++ b/src/citra_qt/debugger/disassembler.cpp
@@ -15,7 +15,6 @@
15#include "common/break_points.h" 15#include "common/break_points.h"
16#include "common/symbols.h" 16#include "common/symbols.h"
17#include "core/arm/arm_interface.h" 17#include "core/arm/arm_interface.h"
18#include "core/arm/skyeye_common/armdefs.h"
19#include "core/arm/disassembler/arm_disasm.h" 18#include "core/arm/disassembler/arm_disasm.h"
20 19
21 20
@@ -219,7 +218,7 @@ void DisassemblerWidget::OnToggleStartStop() {
219} 218}
220 219
221void DisassemblerWidget::OnDebugModeEntered() { 220void DisassemblerWidget::OnDebugModeEntered() {
222 ARMword next_instr = Core::g_app_core->GetPC(); 221 u32 next_instr = Core::g_app_core->GetPC();
223 222
224 if (model->GetBreakPoints().IsAddressBreakPoint(next_instr)) 223 if (model->GetBreakPoints().IsAddressBreakPoint(next_instr))
225 emu_thread->SetRunning(false); 224 emu_thread->SetRunning(false);
diff --git a/src/core/CMakeLists.txt b/src/core/CMakeLists.txt
index 8267ee586..ba9af2a1f 100644
--- a/src/core/CMakeLists.txt
+++ b/src/core/CMakeLists.txt
@@ -6,8 +6,8 @@ set(SRCS
6 arm/dyncom/arm_dyncom_interpreter.cpp 6 arm/dyncom/arm_dyncom_interpreter.cpp
7 arm/dyncom/arm_dyncom_run.cpp 7 arm/dyncom/arm_dyncom_run.cpp
8 arm/dyncom/arm_dyncom_thumb.cpp 8 arm/dyncom/arm_dyncom_thumb.cpp
9 arm/interpreter/arminit.cpp 9 arm/skyeye_common/arminit.cpp
10 arm/interpreter/armsupp.cpp 10 arm/skyeye_common/armsupp.cpp
11 arm/skyeye_common/vfp/vfp.cpp 11 arm/skyeye_common/vfp/vfp.cpp
12 arm/skyeye_common/vfp/vfpdouble.cpp 12 arm/skyeye_common/vfp/vfpdouble.cpp
13 arm/skyeye_common/vfp/vfpinstr.cpp 13 arm/skyeye_common/vfp/vfpinstr.cpp
@@ -132,8 +132,9 @@ set(HEADERS
132 arm/dyncom/arm_dyncom_run.h 132 arm/dyncom/arm_dyncom_run.h
133 arm/dyncom/arm_dyncom_thumb.h 133 arm/dyncom/arm_dyncom_thumb.h
134 arm/skyeye_common/arm_regformat.h 134 arm/skyeye_common/arm_regformat.h
135 arm/skyeye_common/armdefs.h 135 arm/skyeye_common/armstate.h
136 arm/skyeye_common/armmmu.h 136 arm/skyeye_common/armmmu.h
137 arm/skyeye_common/armsupp.h
137 arm/skyeye_common/vfp/asm_vfp.h 138 arm/skyeye_common/vfp/asm_vfp.h
138 arm/skyeye_common/vfp/vfp.h 139 arm/skyeye_common/vfp/vfp.h
139 arm/skyeye_common/vfp/vfp_helper.h 140 arm/skyeye_common/vfp/vfp_helper.h
diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp
index 529c4ac70..a51a3acf8 100644
--- a/src/core/arm/dyncom/arm_dyncom.cpp
+++ b/src/core/arm/dyncom/arm_dyncom.cpp
@@ -6,7 +6,8 @@
6 6
7#include "common/make_unique.h" 7#include "common/make_unique.h"
8 8
9#include "core/arm/skyeye_common/armdefs.h" 9#include "core/arm/skyeye_common/armstate.h"
10#include "core/arm/skyeye_common/armsupp.h"
10#include "core/arm/skyeye_common/vfp/vfp.h" 11#include "core/arm/skyeye_common/vfp/vfp.h"
11 12
12#include "core/arm/dyncom/arm_dyncom.h" 13#include "core/arm/dyncom/arm_dyncom.h"
@@ -19,18 +20,8 @@
19ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) { 20ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
20 state = Common::make_unique<ARMul_State>(); 21 state = Common::make_unique<ARMul_State>();
21 22
22 ARMul_NewState(state.get());
23 ARMul_SelectProcessor(state.get(), ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
24
25 state->abort_model = ABORT_BASE_RESTORED;
26
27 state->bigendSig = LOW;
28 state->lateabtSig = LOW;
29 state->NirqSig = HIGH;
30
31 // Reset the core to initial state 23 // Reset the core to initial state
32 ARMul_Reset(state.get()); 24 ARMul_Reset(state.get());
33 state->Emulate = RUN;
34 25
35 // Switch to the desired privilege mode. 26 // Switch to the desired privilege mode.
36 switch_mode(state.get(), initial_mode); 27 switch_mode(state.get(), initial_mode);
diff --git a/src/core/arm/dyncom/arm_dyncom.h b/src/core/arm/dyncom/arm_dyncom.h
index cc9355722..87ab6908a 100644
--- a/src/core/arm/dyncom/arm_dyncom.h
+++ b/src/core/arm/dyncom/arm_dyncom.h
@@ -9,8 +9,8 @@
9#include "common/common_types.h" 9#include "common/common_types.h"
10 10
11#include "core/arm/arm_interface.h" 11#include "core/arm/arm_interface.h"
12#include "core/arm/skyeye_common/armdefs.h"
13#include "core/arm/skyeye_common/arm_regformat.h" 12#include "core/arm/skyeye_common/arm_regformat.h"
13#include "core/arm/skyeye_common/armstate.h"
14 14
15namespace Core { 15namespace Core {
16struct ThreadContext; 16struct ThreadContext;
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp
index 697be9556..3ab9f2c17 100644
--- a/src/core/arm/dyncom/arm_dyncom_dec.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp
@@ -2,8 +2,8 @@
2// Licensed under GPLv2 or any later version 2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included. 3// Refer to the license.txt file included.
4 4
5#include "core/arm/skyeye_common/armdefs.h"
6#include "core/arm/dyncom/arm_dyncom_dec.h" 5#include "core/arm/dyncom/arm_dyncom_dec.h"
6#include "core/arm/skyeye_common/armsupp.h"
7 7
8const ISEITEM arm_instruction[] = { 8const ISEITEM arm_instruction[] = {
9 { "vmla", 4, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x0, 9, 11, 0x5, 4, 4, 0 }}, 9 { "vmla", 4, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x0, 9, 11, 0x5, 4, 4, 0 }},
@@ -414,7 +414,7 @@ const ISEITEM arm_exclusion_code[] = {
414 { "invalid", 0, INVALID, { 0 }} 414 { "invalid", 0, INVALID, { 0 }}
415}; 415};
416 416
417int decode_arm_instr(uint32_t instr, int32_t *idx) { 417int decode_arm_instr(u32 instr, s32* idx) {
418 int n = 0; 418 int n = 0;
419 int base = 0; 419 int base = 0;
420 int ret = DECODE_FAILURE; 420 int ret = DECODE_FAILURE;
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.h b/src/core/arm/dyncom/arm_dyncom_dec.h
index 4b5f5ad7e..5f6279627 100644
--- a/src/core/arm/dyncom/arm_dyncom_dec.h
+++ b/src/core/arm/dyncom/arm_dyncom_dec.h
@@ -4,7 +4,9 @@
4 4
5#pragma once 5#pragma once
6 6
7int decode_arm_instr(uint32_t instr, int32_t *idx); 7#include "common/common_types.h"
8
9int decode_arm_instr(u32 instr, s32* idx);
8 10
9enum DECODE_STATUS { 11enum DECODE_STATUS {
10 DECODE_SUCCESS, 12 DECODE_SUCCESS,
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 785f39566..fd5e13295 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -17,8 +17,9 @@
17#include "core/arm/dyncom/arm_dyncom_interpreter.h" 17#include "core/arm/dyncom/arm_dyncom_interpreter.h"
18#include "core/arm/dyncom/arm_dyncom_thumb.h" 18#include "core/arm/dyncom/arm_dyncom_thumb.h"
19#include "core/arm/dyncom/arm_dyncom_run.h" 19#include "core/arm/dyncom/arm_dyncom_run.h"
20#include "core/arm/skyeye_common/armdefs.h"
21#include "core/arm/skyeye_common/armmmu.h" 20#include "core/arm/skyeye_common/armmmu.h"
21#include "core/arm/skyeye_common/armstate.h"
22#include "core/arm/skyeye_common/armsupp.h"
22#include "core/arm/skyeye_common/vfp/vfp.h" 23#include "core/arm/skyeye_common/vfp/vfp.h"
23 24
24Common::Profiling::TimingCategory profile_execute("DynCom::Execute"); 25Common::Profiling::TimingCategory profile_execute("DynCom::Execute");
@@ -50,22 +51,21 @@ typedef unsigned int (*shtop_fp_t)(ARMul_State* cpu, unsigned int sht_oper);
50// Defines a reservation granule of 2 words, which protects the first 2 words starting at the tag. 51// Defines a reservation granule of 2 words, which protects the first 2 words starting at the tag.
51// This is the smallest granule allowed by the v7 spec, and is coincidentally just large enough to 52// This is the smallest granule allowed by the v7 spec, and is coincidentally just large enough to
52// support LDR/STREXD. 53// support LDR/STREXD.
53static const ARMword RESERVATION_GRANULE_MASK = 0xFFFFFFF8; 54static const u32 RESERVATION_GRANULE_MASK = 0xFFFFFFF8;
54 55
55// Exclusive memory access 56// Exclusive memory access
56static int exclusive_detect(ARMul_State* state, ARMword addr) { 57static int exclusive_detect(ARMul_State* state, u32 addr) {
57 if(state->exclusive_tag == (addr & RESERVATION_GRANULE_MASK)) 58 if(state->exclusive_tag == (addr & RESERVATION_GRANULE_MASK))
58 return 0; 59 return 0;
59 else 60 else
60 return -1; 61 return -1;
61} 62}
62 63
63static void add_exclusive_addr(ARMul_State* state, ARMword addr){ 64static void add_exclusive_addr(ARMul_State* state, u32 addr){
64 state->exclusive_tag = addr & RESERVATION_GRANULE_MASK; 65 state->exclusive_tag = addr & RESERVATION_GRANULE_MASK;
65 return;
66} 66}
67 67
68static void remove_exclusive(ARMul_State* state, ARMword addr){ 68static void remove_exclusive(ARMul_State* state, u32 addr){
69 state->exclusive_tag = 0xFFFFFFFF; 69 state->exclusive_tag = 0xFFFFFFFF;
70} 70}
71 71
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.h b/src/core/arm/dyncom/arm_dyncom_interpreter.h
index 1c324d29c..7a46dcc94 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.h
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.h
@@ -4,6 +4,6 @@
4 4
5#pragma once 5#pragma once
6 6
7#include "core/arm/skyeye_common/armdefs.h" 7struct ARMul_State;
8 8
9unsigned InterpreterMainLoop(ARMul_State* state); 9unsigned InterpreterMainLoop(ARMul_State* state);
diff --git a/src/core/arm/dyncom/arm_dyncom_run.cpp b/src/core/arm/dyncom/arm_dyncom_run.cpp
index 5a9a6a788..4c6acba98 100644
--- a/src/core/arm/dyncom/arm_dyncom_run.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_run.cpp
@@ -3,7 +3,7 @@
3// Refer to the license.txt file included. 3// Refer to the license.txt file included.
4 4
5#include "core/arm/dyncom/arm_dyncom_run.h" 5#include "core/arm/dyncom/arm_dyncom_run.h"
6#include "core/arm/skyeye_common/armdefs.h" 6#include "core/arm/skyeye_common/armstate.h"
7 7
8void switch_mode(ARMul_State* core, uint32_t mode) { 8void switch_mode(ARMul_State* core, uint32_t mode) {
9 if (core->Mode == mode) 9 if (core->Mode == mode)
diff --git a/src/core/arm/dyncom/arm_dyncom_run.h b/src/core/arm/dyncom/arm_dyncom_run.h
index 85774c565..ef18455bc 100644
--- a/src/core/arm/dyncom/arm_dyncom_run.h
+++ b/src/core/arm/dyncom/arm_dyncom_run.h
@@ -18,7 +18,7 @@
18 18
19#pragma once 19#pragma once
20 20
21#include "core/arm/skyeye_common/armdefs.h" 21#include "core/arm/skyeye_common/armstate.h"
22 22
23void switch_mode(ARMul_State* core, uint32_t mode); 23void switch_mode(ARMul_State* core, uint32_t mode);
24 24
diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.cpp b/src/core/arm/dyncom/arm_dyncom_thumb.cpp
index f10a5b70f..2860af376 100644
--- a/src/core/arm/dyncom/arm_dyncom_thumb.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_thumb.cpp
@@ -6,6 +6,7 @@
6// ARM instruction, and using the existing ARM simulator. 6// ARM instruction, and using the existing ARM simulator.
7 7
8#include "core/arm/dyncom/arm_dyncom_thumb.h" 8#include "core/arm/dyncom/arm_dyncom_thumb.h"
9#include "core/arm/skyeye_common/armsupp.h"
9 10
10// Decode a 16bit Thumb instruction. The instruction is in the low 16-bits of the tinstr field, 11// Decode a 16bit Thumb instruction. The instruction is in the low 16-bits of the tinstr field,
11// with the following Thumb instruction held in the high 16-bits. Passing in two Thumb instructions 12// with the following Thumb instruction held in the high 16-bits. Passing in two Thumb instructions
@@ -13,7 +14,7 @@
13 14
14tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) { 15tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
15 tdstate valid = t_uninitialized; 16 tdstate valid = t_uninitialized;
16 ARMword tinstr = instr; 17 u32 tinstr = instr;
17 18
18 // The endian should be judge here 19 // The endian should be judge here
19 if((addr & 0x3) != 0) 20 if((addr & 0x3) != 0)
@@ -36,7 +37,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
36 37
37 case 3: // ADD/SUB 38 case 3: // ADD/SUB
38 { 39 {
39 static const ARMword subset[4] = { 40 static const u32 subset[4] = {
40 0xE0900000, // ADDS Rd,Rs,Rn 41 0xE0900000, // ADDS Rd,Rs,Rn
41 0xE0500000, // SUBS Rd,Rs,Rn 42 0xE0500000, // SUBS Rd,Rs,Rn
42 0xE2900000, // ADDS Rd,Rs,#imm3 43 0xE2900000, // ADDS Rd,Rs,#imm3
@@ -55,7 +56,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
55 case 6: // ADD 56 case 6: // ADD
56 case 7: // SUB 57 case 7: // SUB
57 { 58 {
58 static const ARMword subset[4] = { 59 static const u32 subset[4] = {
59 0xE3B00000, // MOVS Rd,#imm8 60 0xE3B00000, // MOVS Rd,#imm8
60 0xE3500000, // CMP Rd,#imm8 61 0xE3500000, // CMP Rd,#imm8
61 0xE2900000, // ADDS Rd,Rd,#imm8 62 0xE2900000, // ADDS Rd,Rd,#imm8
@@ -84,7 +85,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
84 }; 85 };
85 86
86 static const struct { 87 static const struct {
87 ARMword opcode; 88 u32 opcode;
88 otype type; 89 otype type;
89 } subset[16] = { 90 } subset[16] = {
90 { 0xE0100000, t_norm }, // ANDS Rd,Rd,Rs 91 { 0xE0100000, t_norm }, // ANDS Rd,Rd,Rs
@@ -129,8 +130,8 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
129 break; 130 break;
130 } 131 }
131 } else { 132 } else {
132 ARMword Rd = ((tinstr & 0x0007) >> 0); 133 u32 Rd = ((tinstr & 0x0007) >> 0);
133 ARMword Rs = ((tinstr & 0x0078) >> 3); 134 u32 Rs = ((tinstr & 0x0078) >> 3);
134 135
135 if (tinstr & (1 << 7)) 136 if (tinstr & (1 << 7))
136 Rd += 8; 137 Rd += 8;
@@ -184,7 +185,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
184 case 10: 185 case 10:
185 case 11: 186 case 11:
186 { 187 {
187 static const ARMword subset[8] = { 188 static const u32 subset[8] = {
188 0xE7800000, // STR Rd,[Rb,Ro] 189 0xE7800000, // STR Rd,[Rb,Ro]
189 0xE18000B0, // STRH Rd,[Rb,Ro] 190 0xE18000B0, // STRH Rd,[Rb,Ro]
190 0xE7C00000, // STRB Rd,[Rb,Ro] 191 0xE7C00000, // STRB Rd,[Rb,Ro]
@@ -207,7 +208,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
207 case 14: // STRB Rd,[Rb,#imm5] 208 case 14: // STRB Rd,[Rb,#imm5]
208 case 15: // LDRB Rd,[Rb,#imm5] 209 case 15: // LDRB Rd,[Rb,#imm5]
209 { 210 {
210 static const ARMword subset[4] = { 211 static const u32 subset[4] = {
211 0xE5800000, // STR Rd,[Rb,#imm5] 212 0xE5800000, // STR Rd,[Rb,#imm5]
212 0xE5900000, // LDR Rd,[Rb,#imm5] 213 0xE5900000, // LDR Rd,[Rb,#imm5]
213 0xE5C00000, // STRB Rd,[Rb,#imm5] 214 0xE5C00000, // STRB Rd,[Rb,#imm5]
@@ -274,7 +275,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
274 | BITS(tinstr, 0, 3) // imm4 field; 275 | BITS(tinstr, 0, 3) // imm4 field;
275 | (BITS(tinstr, 4, 7) << 8); // beginning 4 bits of imm12 276 | (BITS(tinstr, 4, 7) << 8); // beginning 4 bits of imm12
276 } else if ((tinstr & 0x0F00) == 0x0200) { 277 } else if ((tinstr & 0x0F00) == 0x0200) {
277 static const ARMword subset[4] = { 278 static const u32 subset[4] = {
278 0xE6BF0070, // SXTH 279 0xE6BF0070, // SXTH
279 0xE6AF0070, // SXTB 280 0xE6AF0070, // SXTB
280 0xE6FF0070, // UXTH 281 0xE6FF0070, // UXTH
@@ -298,7 +299,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
298 | (BIT(tinstr, 4) << 18); // enable bit 299 | (BIT(tinstr, 4) << 18); // enable bit
299 } 300 }
300 } else if ((tinstr & 0x0F00) == 0x0a00) { 301 } else if ((tinstr & 0x0F00) == 0x0a00) {
301 static const ARMword subset[3] = { 302 static const u32 subset[3] = {
302 0xE6BF0F30, // REV 303 0xE6BF0F30, // REV
303 0xE6BF0FB0, // REV16 304 0xE6BF0FB0, // REV16
304 0xE6FF0FB0, // REVSH 305 0xE6FF0FB0, // REVSH
@@ -308,7 +309,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
308 | (BITS(tinstr, 0, 2) << 12) // Rd 309 | (BITS(tinstr, 0, 2) << 12) // Rd
309 | BITS(tinstr, 3, 5); // Rm 310 | BITS(tinstr, 3, 5); // Rm
310 } else { 311 } else {
311 static const ARMword subset[4] = { 312 static const u32 subset[4] = {
312 0xE92D0000, // STMDB sp!,{rlist} 313 0xE92D0000, // STMDB sp!,{rlist}
313 0xE92D4000, // STMDB sp!,{rlist,lr} 314 0xE92D4000, // STMDB sp!,{rlist,lr}
314 0xE8BD0000, // LDMIA sp!,{rlist} 315 0xE8BD0000, // LDMIA sp!,{rlist}
diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.h b/src/core/arm/dyncom/arm_dyncom_thumb.h
index 8394ff156..c06f09580 100644
--- a/src/core/arm/dyncom/arm_dyncom_thumb.h
+++ b/src/core/arm/dyncom/arm_dyncom_thumb.h
@@ -26,7 +26,7 @@
26 26
27#pragma once 27#pragma once
28 28
29#include "core/arm/skyeye_common/armdefs.h" 29#include "common/common_types.h"
30 30
31enum tdstate { 31enum tdstate {
32 t_undefined, // Undefined Thumb instruction 32 t_undefined, // Undefined Thumb instruction
diff --git a/src/core/arm/skyeye_common/armdefs.h b/src/core/arm/skyeye_common/armdefs.h
deleted file mode 100644
index a0ec108c7..000000000
--- a/src/core/arm/skyeye_common/armdefs.h
+++ /dev/null
@@ -1,318 +0,0 @@
1/* armdefs.h -- ARMulator common definitions: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17
18#pragma once
19
20#include <unordered_map>
21
22#include "common/common_types.h"
23#include "core/arm/skyeye_common/arm_regformat.h"
24
25#define BITS(s, a, b) ((s << ((sizeof(s) * 8 - 1) - b)) >> (sizeof(s) * 8 - b + a - 1))
26#define BIT(s, n) ((s >> (n)) & 1)
27
28// Signal levels
29enum {
30 LOW = 0,
31 HIGH = 1,
32 LOWHIGH = 1,
33 HIGHLOW = 2
34};
35
36// Cache types
37enum {
38 NONCACHE = 0,
39 DATACACHE = 1,
40 INSTCACHE = 2,
41};
42
43// Abort models
44enum {
45 ABORT_BASE_RESTORED = 0,
46 ABORT_EARLY = 1,
47 ABORT_BASE_UPDATED = 2
48};
49
50#define POS(i) ( (~(i)) >> 31 )
51#define NEG(i) ( (i) >> 31 )
52
53typedef u64 ARMdword; // must be 64 bits wide
54typedef u32 ARMword; // must be 32 bits wide
55typedef u16 ARMhword; // must be 16 bits wide
56typedef u8 ARMbyte; // must be 8 bits wide
57
58#define VFP_REG_NUM 64
59struct ARMul_State
60{
61 ARMword Emulate; // To start and stop emulation
62
63 // Order of the following register should not be modified
64 ARMword Reg[16]; // The current register file
65 ARMword Cpsr; // The current PSR
66 ARMword Spsr_copy;
67 ARMword phys_pc;
68 ARMword Reg_usr[2];
69 ARMword Reg_svc[2]; // R13_SVC R14_SVC
70 ARMword Reg_abort[2]; // R13_ABORT R14_ABORT
71 ARMword Reg_undef[2]; // R13 UNDEF R14 UNDEF
72 ARMword Reg_irq[2]; // R13_IRQ R14_IRQ
73 ARMword Reg_firq[7]; // R8---R14 FIRQ
74 ARMword Spsr[7]; // The exception psr's
75 ARMword Mode; // The current mode
76 ARMword Bank; // The current register bank
77 ARMword exclusive_tag; // The address for which the local monitor is in exclusive access mode
78 ARMword exclusive_state;
79 ARMword exclusive_result;
80 ARMword CP15[CP15_REGISTER_COUNT];
81
82 // FPSID, FPSCR, and FPEXC
83 ARMword VFP[VFP_SYSTEM_REGISTER_COUNT];
84 // VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31).
85 // VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31),
86 // and only 32 singleword registers are accessible (S0-S31).
87 ARMword ExtReg[VFP_REG_NUM];
88 /* ---- End of the ordered registers ---- */
89
90 ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed
91 unsigned int shifter_carry_out;
92
93 // Add armv6 flags dyf:2010-08-09
94 ARMword GEFlag, EFlag, AFlag, QFlag;
95
96 ARMword TFlag; // Thumb state
97
98 unsigned long long NumInstrs; // The number of instructions executed
99 unsigned NumInstrsToExecute;
100
101 unsigned NresetSig; // Reset the processor
102 unsigned NfiqSig;
103 unsigned NirqSig;
104
105 unsigned abortSig;
106 unsigned NtransSig;
107 unsigned bigendSig;
108 unsigned syscallSig;
109
110/* 2004-05-09 chy
111----------------------------------------------------------
112read ARM Architecture Reference Manual
1132.6.5 Data Abort
114There are three Abort Model in ARM arch.
115
116Early Abort Model: used in some ARMv3 and earlier implementations. In this
117model, base register wirteback occurred for LDC,LDM,STC,STM instructions, and
118the base register was unchanged for all other instructions. (oldest)
119
120Base Restored Abort Model: If a Data Abort occurs in an instruction which
121specifies base register writeback, the value in the base register is
122unchanged. (strongarm, xscale)
123
124Base Updated Abort Model: If a Data Abort occurs in an instruction which
125specifies base register writeback, the base register writeback still occurs.
126(arm720T)
127
128read PART B
129chap2 The System Control Coprocessor CP15
1302.4 Register1:control register
131L(bit 6): in some ARMv3 and earlier implementations, the abort model of the
132processor could be configured:
1330=early Abort Model Selected(now obsolete)
1341=Late Abort Model selceted(same as Base Updated Abort Model)
135
136on later processors, this bit reads as 1 and ignores writes.
137-------------------------------------------------------------
138So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
139 if lateabtSig=0, then it means Base Restored Abort Model
140*/
141 unsigned lateabtSig;
142
143 // For differentiating ARM core emulaiton.
144 bool is_v4; // Are we emulating a v4 architecture (or higher)?
145 bool is_v5; // Are we emulating a v5 architecture?
146 bool is_v5e; // Are we emulating a v5e architecture?
147 bool is_v6; // Are we emulating a v6 architecture?
148 bool is_v7; // Are we emulating a v7 architecture?
149
150 // ARM_ARM A2-18
151 // 0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model
152 int abort_model;
153
154 // TODO(bunnei): Move this cache to a better place - it should be per codeset (likely per
155 // process for our purposes), not per ARMul_State (which tracks CPU core state).
156 std::unordered_map<u32, int> instruction_cache;
157};
158
159/***************************************************************************\
160* Types of ARM we know about *
161\***************************************************************************/
162
163enum {
164 ARM_v4_Prop = 0x01,
165 ARM_v5_Prop = 0x02,
166 ARM_v5e_Prop = 0x04,
167 ARM_v6_Prop = 0x08,
168 ARM_v7_Prop = 0x10,
169};
170
171/***************************************************************************\
172* The hardware vector addresses *
173\***************************************************************************/
174
175enum {
176 ARMResetV = 0,
177 ARMUndefinedInstrV = 4,
178 ARMSWIV = 8,
179 ARMPrefetchAbortV = 12,
180 ARMDataAbortV = 16,
181 ARMAddrExceptnV = 20,
182 ARMIRQV = 24,
183 ARMFIQV = 28,
184 ARMErrorV = 32, // This is an offset, not an address!
185
186 ARMul_ResetV = ARMResetV,
187 ARMul_UndefinedInstrV = ARMUndefinedInstrV,
188 ARMul_SWIV = ARMSWIV,
189 ARMul_PrefetchAbortV = ARMPrefetchAbortV,
190 ARMul_DataAbortV = ARMDataAbortV,
191 ARMul_AddrExceptnV = ARMAddrExceptnV,
192 ARMul_IRQV = ARMIRQV,
193 ARMul_FIQV = ARMFIQV
194};
195
196/***************************************************************************\
197* Mode and Bank Constants *
198\***************************************************************************/
199
200enum PrivilegeMode {
201 USER32MODE = 16,
202 FIQ32MODE = 17,
203 IRQ32MODE = 18,
204 SVC32MODE = 19,
205 ABORT32MODE = 23,
206 UNDEF32MODE = 27,
207 SYSTEM32MODE = 31
208};
209
210enum {
211 USERBANK = 0,
212 FIQBANK = 1,
213 IRQBANK = 2,
214 SVCBANK = 3,
215 ABORTBANK = 4,
216 UNDEFBANK = 5,
217 DUMMYBANK = 6,
218 SYSTEMBANK = 7
219};
220
221/***************************************************************************\
222* Definitions of things in the emulator *
223\***************************************************************************/
224void ARMul_Reset(ARMul_State* state);
225ARMul_State* ARMul_NewState(ARMul_State* state);
226
227/***************************************************************************\
228* Definitions of things in the co-processor interface *
229\***************************************************************************/
230
231enum {
232 ARMul_FIRST = 0,
233 ARMul_TRANSFER = 1,
234 ARMul_BUSY = 2,
235 ARMul_DATA = 3,
236 ARMul_INTERRUPT = 4,
237 ARMul_DONE = 0,
238 ARMul_CANT = 1,
239 ARMul_INC = 3
240};
241
242/***************************************************************************\
243* Definitions of things in the host environment *
244\***************************************************************************/
245
246enum ConditionCode {
247 EQ = 0,
248 NE = 1,
249 CS = 2,
250 CC = 3,
251 MI = 4,
252 PL = 5,
253 VS = 6,
254 VC = 7,
255 HI = 8,
256 LS = 9,
257 GE = 10,
258 LT = 11,
259 GT = 12,
260 LE = 13,
261 AL = 14,
262 NV = 15,
263};
264
265// Flags for use with the APSR.
266enum : u32 {
267 NBIT = (1U << 31U),
268 ZBIT = (1 << 30),
269 CBIT = (1 << 29),
270 VBIT = (1 << 28),
271 QBIT = (1 << 27),
272 JBIT = (1 << 24),
273 EBIT = (1 << 9),
274 ABIT = (1 << 8),
275 IBIT = (1 << 7),
276 FBIT = (1 << 6),
277 TBIT = (1 << 5),
278
279 // Masks for groups of bits in the APSR.
280 MODEBITS = 0x1F,
281 INTBITS = 0x1C0,
282};
283
284// Values for Emulate.
285enum {
286 STOP = 0, // Stop
287 CHANGEMODE = 1, // Change mode
288 ONCE = 2, // Execute just one iteration
289 RUN = 3 // Continuous execution
290};
291
292
293bool AddOverflow(ARMword, ARMword, ARMword);
294bool SubOverflow(ARMword, ARMword, ARMword);
295
296void ARMul_SelectProcessor(ARMul_State*, unsigned);
297
298u32 AddWithCarry(u32, u32, u32, bool*, bool*);
299bool ARMul_AddOverflowQ(ARMword, ARMword);
300
301u8 ARMul_SignedSaturatedAdd8(u8, u8);
302u8 ARMul_SignedSaturatedSub8(u8, u8);
303u16 ARMul_SignedSaturatedAdd16(u16, u16);
304u16 ARMul_SignedSaturatedSub16(u16, u16);
305
306u8 ARMul_UnsignedSaturatedAdd8(u8, u8);
307u16 ARMul_UnsignedSaturatedAdd16(u16, u16);
308u8 ARMul_UnsignedSaturatedSub8(u8, u8);
309u16 ARMul_UnsignedSaturatedSub16(u16, u16);
310u8 ARMul_UnsignedAbsoluteDifference(u8, u8);
311u32 ARMul_SignedSatQ(s32, u8, bool*);
312u32 ARMul_UnsignedSatQ(s32, u8, bool*);
313
314bool InBigEndianMode(ARMul_State*);
315bool InAPrivilegedMode(ARMul_State*);
316
317u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2);
318void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2);
diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/skyeye_common/arminit.cpp
index 4f7a48fab..b7c508d75 100644
--- a/src/core/arm/interpreter/arminit.cpp
+++ b/src/core/arm/skyeye_common/arminit.cpp
@@ -16,36 +16,9 @@
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17 17
18#include <cstring> 18#include <cstring>
19#include "core/arm/skyeye_common/armdefs.h" 19#include "core/arm/skyeye_common/armstate.h"
20#include "core/arm/skyeye_common/vfp/vfp.h" 20#include "core/arm/skyeye_common/vfp/vfp.h"
21 21
22/***************************************************************************\
23* Returns a new instantiation of the ARMulator's state *
24\***************************************************************************/
25ARMul_State* ARMul_NewState(ARMul_State* state)
26{
27 state->Emulate = RUN;
28 state->Mode = USER32MODE;
29
30 state->lateabtSig = HIGH;
31 state->bigendSig = LOW;
32
33 return state;
34}
35
36/***************************************************************************\
37* Call this routine to set ARMulator to model a certain processor *
38\***************************************************************************/
39
40void ARMul_SelectProcessor(ARMul_State* state, unsigned properties)
41{
42 state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) != 0;
43 state->is_v5 = (properties & ARM_v5_Prop) != 0;
44 state->is_v5e = (properties & ARM_v5e_Prop) != 0;
45 state->is_v6 = (properties & ARM_v6_Prop) != 0;
46 state->is_v7 = (properties & ARM_v7_Prop) != 0;
47}
48
49// Resets certain MPCore CP15 values to their ARM-defined reset values. 22// Resets certain MPCore CP15 values to their ARM-defined reset values.
50static void ResetMPCoreCP15Registers(ARMul_State* cpu) 23static void ResetMPCoreCP15Registers(ARMul_State* cpu)
51{ 24{
@@ -104,9 +77,7 @@ static void ResetMPCoreCP15Registers(ARMul_State* cpu)
104 cpu->CP15[CP15_TLB_DEBUG_CONTROL] = 0x00000000; 77 cpu->CP15[CP15_TLB_DEBUG_CONTROL] = 0x00000000;
105} 78}
106 79
107/***************************************************************************\ 80// Performs a reset
108* Call this routine to set up the initial machine state (or perform a RESET *
109\***************************************************************************/
110void ARMul_Reset(ARMul_State* state) 81void ARMul_Reset(ARMul_State* state)
111{ 82{
112 VFPInit(state); 83 VFPInit(state);
@@ -125,4 +96,5 @@ void ARMul_Reset(ARMul_State* state)
125 state->abortSig = LOW; 96 state->abortSig = LOW;
126 97
127 state->NumInstrs = 0; 98 state->NumInstrs = 0;
99 state->Emulate = RUN;
128} 100}
diff --git a/src/core/arm/skyeye_common/armmmu.h b/src/core/arm/skyeye_common/armmmu.h
index c67d7209b..5423588c0 100644
--- a/src/core/arm/skyeye_common/armmmu.h
+++ b/src/core/arm/skyeye_common/armmmu.h
@@ -23,7 +23,8 @@
23#include "common/swap.h" 23#include "common/swap.h"
24 24
25#include "core/memory.h" 25#include "core/memory.h"
26#include "core/arm/skyeye_common/armdefs.h" 26#include "core/arm/skyeye_common/armstate.h"
27#include "core/arm/skyeye_common/armsupp.h"
27 28
28// Register numbers in the MMU 29// Register numbers in the MMU
29enum 30enum
diff --git a/src/core/arm/skyeye_common/armstate.h b/src/core/arm/skyeye_common/armstate.h
new file mode 100644
index 000000000..3ba0ba5cd
--- /dev/null
+++ b/src/core/arm/skyeye_common/armstate.h
@@ -0,0 +1,215 @@
1/* armdefs.h -- ARMulator common definitions: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17
18#pragma once
19
20#include <unordered_map>
21
22#include "common/common_types.h"
23#include "core/arm/skyeye_common/arm_regformat.h"
24
25// Signal levels
26enum {
27 LOW = 0,
28 HIGH = 1,
29 LOWHIGH = 1,
30 HIGHLOW = 2
31};
32
33// Cache types
34enum {
35 NONCACHE = 0,
36 DATACACHE = 1,
37 INSTCACHE = 2,
38};
39
40#define VFP_REG_NUM 64
41struct ARMul_State
42{
43 u32 Emulate; // To start and stop emulation
44
45 // Order of the following register should not be modified
46 u32 Reg[16]; // The current register file
47 u32 Cpsr; // The current PSR
48 u32 Spsr_copy;
49 u32 phys_pc;
50 u32 Reg_usr[2];
51 u32 Reg_svc[2]; // R13_SVC R14_SVC
52 u32 Reg_abort[2]; // R13_ABORT R14_ABORT
53 u32 Reg_undef[2]; // R13 UNDEF R14 UNDEF
54 u32 Reg_irq[2]; // R13_IRQ R14_IRQ
55 u32 Reg_firq[7]; // R8---R14 FIRQ
56 u32 Spsr[7]; // The exception psr's
57 u32 Mode; // The current mode
58 u32 Bank; // The current register bank
59 u32 exclusive_tag; // The address for which the local monitor is in exclusive access mode
60 u32 exclusive_state;
61 u32 exclusive_result;
62 u32 CP15[CP15_REGISTER_COUNT];
63
64 // FPSID, FPSCR, and FPEXC
65 u32 VFP[VFP_SYSTEM_REGISTER_COUNT];
66 // VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31).
67 // VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31),
68 // and only 32 singleword registers are accessible (S0-S31).
69 u32 ExtReg[VFP_REG_NUM];
70 /* ---- End of the ordered registers ---- */
71
72 u32 NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed
73 unsigned int shifter_carry_out;
74
75 // Add armv6 flags dyf:2010-08-09
76 u32 GEFlag, EFlag, AFlag, QFlag;
77
78 u32 TFlag; // Thumb state
79
80 unsigned long long NumInstrs; // The number of instructions executed
81 unsigned NumInstrsToExecute;
82
83 unsigned NresetSig; // Reset the processor
84 unsigned NfiqSig;
85 unsigned NirqSig;
86
87 unsigned abortSig;
88 unsigned NtransSig;
89 unsigned bigendSig;
90 unsigned syscallSig;
91
92 // TODO(bunnei): Move this cache to a better place - it should be per codeset (likely per
93 // process for our purposes), not per ARMul_State (which tracks CPU core state).
94 std::unordered_map<u32, int> instruction_cache;
95};
96
97/***************************************************************************\
98* The hardware vector addresses *
99\***************************************************************************/
100
101enum {
102 ARMResetV = 0,
103 ARMUndefinedInstrV = 4,
104 ARMSWIV = 8,
105 ARMPrefetchAbortV = 12,
106 ARMDataAbortV = 16,
107 ARMAddrExceptnV = 20,
108 ARMIRQV = 24,
109 ARMFIQV = 28,
110 ARMErrorV = 32, // This is an offset, not an address!
111
112 ARMul_ResetV = ARMResetV,
113 ARMul_UndefinedInstrV = ARMUndefinedInstrV,
114 ARMul_SWIV = ARMSWIV,
115 ARMul_PrefetchAbortV = ARMPrefetchAbortV,
116 ARMul_DataAbortV = ARMDataAbortV,
117 ARMul_AddrExceptnV = ARMAddrExceptnV,
118 ARMul_IRQV = ARMIRQV,
119 ARMul_FIQV = ARMFIQV
120};
121
122/***************************************************************************\
123* Mode and Bank Constants *
124\***************************************************************************/
125
126enum PrivilegeMode {
127 USER32MODE = 16,
128 FIQ32MODE = 17,
129 IRQ32MODE = 18,
130 SVC32MODE = 19,
131 ABORT32MODE = 23,
132 UNDEF32MODE = 27,
133 SYSTEM32MODE = 31
134};
135
136enum {
137 USERBANK = 0,
138 FIQBANK = 1,
139 IRQBANK = 2,
140 SVCBANK = 3,
141 ABORTBANK = 4,
142 UNDEFBANK = 5,
143 DUMMYBANK = 6,
144 SYSTEMBANK = 7
145};
146
147/***************************************************************************\
148* Definitions of things in the emulator *
149\***************************************************************************/
150void ARMul_Reset(ARMul_State* state);
151
152/***************************************************************************\
153* Definitions of things in the co-processor interface *
154\***************************************************************************/
155
156enum {
157 ARMul_FIRST = 0,
158 ARMul_TRANSFER = 1,
159 ARMul_BUSY = 2,
160 ARMul_DATA = 3,
161 ARMul_INTERRUPT = 4,
162 ARMul_DONE = 0,
163 ARMul_CANT = 1,
164 ARMul_INC = 3
165};
166
167/***************************************************************************\
168* Definitions of things in the host environment *
169\***************************************************************************/
170
171enum ConditionCode {
172 EQ = 0,
173 NE = 1,
174 CS = 2,
175 CC = 3,
176 MI = 4,
177 PL = 5,
178 VS = 6,
179 VC = 7,
180 HI = 8,
181 LS = 9,
182 GE = 10,
183 LT = 11,
184 GT = 12,
185 LE = 13,
186 AL = 14,
187 NV = 15,
188};
189
190// Flags for use with the APSR.
191enum : u32 {
192 NBIT = (1U << 31U),
193 ZBIT = (1 << 30),
194 CBIT = (1 << 29),
195 VBIT = (1 << 28),
196 QBIT = (1 << 27),
197 JBIT = (1 << 24),
198 EBIT = (1 << 9),
199 ABIT = (1 << 8),
200 IBIT = (1 << 7),
201 FBIT = (1 << 6),
202 TBIT = (1 << 5),
203
204 // Masks for groups of bits in the APSR.
205 MODEBITS = 0x1F,
206 INTBITS = 0x1C0,
207};
208
209// Values for Emulate.
210enum {
211 STOP = 0, // Stop
212 CHANGEMODE = 1, // Change mode
213 ONCE = 2, // Execute just one iteration
214 RUN = 3 // Continuous execution
215};
diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/skyeye_common/armsupp.cpp
index 83f7f3e2c..affbf193a 100644
--- a/src/core/arm/interpreter/armsupp.cpp
+++ b/src/core/arm/skyeye_common/armsupp.cpp
@@ -18,8 +18,9 @@
18#include "common/logging/log.h" 18#include "common/logging/log.h"
19 19
20#include "core/mem_map.h" 20#include "core/mem_map.h"
21#include "core/arm/skyeye_common/armdefs.h"
22#include "core/arm/skyeye_common/arm_regformat.h" 21#include "core/arm/skyeye_common/arm_regformat.h"
22#include "core/arm/skyeye_common/armstate.h"
23#include "core/arm/skyeye_common/armsupp.h"
23 24
24// Unsigned sum of absolute difference 25// Unsigned sum of absolute difference
25u8 ARMul_UnsignedAbsoluteDifference(u8 left, u8 right) 26u8 ARMul_UnsignedAbsoluteDifference(u8 left, u8 right)
@@ -47,21 +48,21 @@ u32 AddWithCarry(u32 left, u32 right, u32 carry_in, bool* carry_out_occurred, bo
47} 48}
48 49
49// Compute whether an addition of A and B, giving RESULT, overflowed. 50// Compute whether an addition of A and B, giving RESULT, overflowed.
50bool AddOverflow(ARMword a, ARMword b, ARMword result) 51bool AddOverflow(u32 a, u32 b, u32 result)
51{ 52{
52 return ((NEG(a) && NEG(b) && POS(result)) || 53 return ((NEG(a) && NEG(b) && POS(result)) ||
53 (POS(a) && POS(b) && NEG(result))); 54 (POS(a) && POS(b) && NEG(result)));
54} 55}
55 56
56// Compute whether a subtraction of A and B, giving RESULT, overflowed. 57// Compute whether a subtraction of A and B, giving RESULT, overflowed.
57bool SubOverflow(ARMword a, ARMword b, ARMword result) 58bool SubOverflow(u32 a, u32 b, u32 result)
58{ 59{
59 return ((NEG(a) && POS(b) && POS(result)) || 60 return ((NEG(a) && POS(b) && POS(result)) ||
60 (POS(a) && NEG(b) && NEG(result))); 61 (POS(a) && NEG(b) && NEG(result)));
61} 62}
62 63
63// Returns true if the Q flag should be set as a result of overflow. 64// Returns true if the Q flag should be set as a result of overflow.
64bool ARMul_AddOverflowQ(ARMword a, ARMword b) 65bool ARMul_AddOverflowQ(u32 a, u32 b)
65{ 66{
66 u32 result = a + b; 67 u32 result = a + b;
67 if (((result ^ a) & (u32)0x80000000) && ((a ^ b) & (u32)0x80000000) == 0) 68 if (((result ^ a) & (u32)0x80000000) && ((a ^ b) & (u32)0x80000000) == 0)
diff --git a/src/core/arm/skyeye_common/armsupp.h b/src/core/arm/skyeye_common/armsupp.h
new file mode 100644
index 000000000..5cf1cd1d3
--- /dev/null
+++ b/src/core/arm/skyeye_common/armsupp.h
@@ -0,0 +1,40 @@
1// Copyright 2014 Citra Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#pragma once
6
7#include "common/common_types.h"
8
9struct ARMul_State;
10
11#define BITS(s, a, b) ((s << ((sizeof(s) * 8 - 1) - b)) >> (sizeof(s) * 8 - b + a - 1))
12#define BIT(s, n) ((s >> (n)) & 1)
13
14#define POS(i) ( (~(i)) >> 31 )
15#define NEG(i) ( (i) >> 31 )
16
17bool AddOverflow(u32, u32, u32);
18bool SubOverflow(u32, u32, u32);
19
20u32 AddWithCarry(u32, u32, u32, bool*, bool*);
21bool ARMul_AddOverflowQ(u32, u32);
22
23u8 ARMul_SignedSaturatedAdd8(u8, u8);
24u8 ARMul_SignedSaturatedSub8(u8, u8);
25u16 ARMul_SignedSaturatedAdd16(u16, u16);
26u16 ARMul_SignedSaturatedSub16(u16, u16);
27
28u8 ARMul_UnsignedSaturatedAdd8(u8, u8);
29u16 ARMul_UnsignedSaturatedAdd16(u16, u16);
30u8 ARMul_UnsignedSaturatedSub8(u8, u8);
31u16 ARMul_UnsignedSaturatedSub16(u16, u16);
32u8 ARMul_UnsignedAbsoluteDifference(u8, u8);
33u32 ARMul_SignedSatQ(s32, u8, bool*);
34u32 ARMul_UnsignedSatQ(s32, u8, bool*);
35
36bool InBigEndianMode(ARMul_State*);
37bool InAPrivilegedMode(ARMul_State*);
38
39u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2);
40void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2);
diff --git a/src/core/arm/skyeye_common/vfp/vfp.cpp b/src/core/arm/skyeye_common/vfp/vfp.cpp
index 1ffc1f9af..26f303de4 100644
--- a/src/core/arm/skyeye_common/vfp/vfp.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfp.cpp
@@ -23,7 +23,7 @@
23#include "common/common_funcs.h" 23#include "common/common_funcs.h"
24#include "common/logging/log.h" 24#include "common/logging/log.h"
25 25
26#include "core/arm/skyeye_common/armdefs.h" 26#include "core/arm/skyeye_common/armstate.h"
27#include "core/arm/skyeye_common/vfp/asm_vfp.h" 27#include "core/arm/skyeye_common/vfp/asm_vfp.h"
28#include "core/arm/skyeye_common/vfp/vfp.h" 28#include "core/arm/skyeye_common/vfp/vfp.h"
29 29
@@ -43,7 +43,7 @@ void VFPInit(ARMul_State* state)
43 state->VFP[VFP_MVFR1] = 0; 43 state->VFP[VFP_MVFR1] = 0;
44} 44}
45 45
46void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword* value) 46void VMOVBRS(ARMul_State* state, u32 to_arm, u32 t, u32 n, u32* value)
47{ 47{
48 if (to_arm) 48 if (to_arm)
49 { 49 {
@@ -55,7 +55,7 @@ void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword*
55 } 55 }
56} 56}
57 57
58void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2) 58void VMOVBRRD(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2)
59{ 59{
60 if (to_arm) 60 if (to_arm)
61 { 61 {
@@ -68,7 +68,7 @@ void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword
68 state->ExtReg[n*2] = *value1; 68 state->ExtReg[n*2] = *value1;
69 } 69 }
70} 70}
71void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2) 71void VMOVBRRSS(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2)
72{ 72{
73 if (to_arm) 73 if (to_arm)
74 { 74 {
@@ -82,7 +82,7 @@ void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMwor
82 } 82 }
83} 83}
84 84
85void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm) 85void VMOVI(ARMul_State* state, u32 single, u32 d, u32 imm)
86{ 86{
87 if (single) 87 if (single)
88 { 88 {
@@ -95,7 +95,7 @@ void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm)
95 state->ExtReg[d*2] = 0; 95 state->ExtReg[d*2] = 0;
96 } 96 }
97} 97}
98void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword m) 98void VMOVR(ARMul_State* state, u32 single, u32 d, u32 m)
99{ 99{
100 if (single) 100 if (single)
101 { 101 {
diff --git a/src/core/arm/skyeye_common/vfp/vfp.h b/src/core/arm/skyeye_common/vfp/vfp.h
index 80ca93ccd..88908da9f 100644
--- a/src/core/arm/skyeye_common/vfp/vfp.h
+++ b/src/core/arm/skyeye_common/vfp/vfp.h
@@ -36,8 +36,8 @@ void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpsc
36u32 vfp_single_cpdo(ARMul_State* state, u32 inst, u32 fpscr); 36u32 vfp_single_cpdo(ARMul_State* state, u32 inst, u32 fpscr);
37u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr); 37u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr);
38 38
39void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword* value); 39void VMOVBRS(ARMul_State* state, u32 to_arm, u32 t, u32 n, u32* value);
40void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2); 40void VMOVBRRD(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2);
41void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2); 41void VMOVBRRSS(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2);
42void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm); 42void VMOVI(ARMul_State* state, u32 single, u32 d, u32 imm);
43void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword imm); 43void VMOVR(ARMul_State* state, u32 single, u32 d, u32 imm);
diff --git a/src/core/arm/skyeye_common/vfp/vfp_helper.h b/src/core/arm/skyeye_common/vfp/vfp_helper.h
index 2007d6dc4..91a8d4d57 100644
--- a/src/core/arm/skyeye_common/vfp/vfp_helper.h
+++ b/src/core/arm/skyeye_common/vfp/vfp_helper.h
@@ -34,7 +34,7 @@
34 34
35#include <cstdio> 35#include <cstdio>
36#include "common/common_types.h" 36#include "common/common_types.h"
37#include "core/arm/skyeye_common/armdefs.h" 37#include "core/arm/skyeye_common/armstate.h"
38#include "core/arm/skyeye_common/vfp/asm_vfp.h" 38#include "core/arm/skyeye_common/vfp/asm_vfp.h"
39 39
40#define do_div(n, base) {n/=base;} 40#define do_div(n, base) {n/=base;}
@@ -415,7 +415,7 @@ struct op {
415 u32 flags; 415 u32 flags;
416}; 416};
417 417
418static inline u32 fls(ARMword x) 418static inline u32 fls(u32 x)
419{ 419{
420 int r = 32; 420 int r = 32;
421 421
diff --git a/src/core/arm/skyeye_common/vfp/vfpdouble.cpp b/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
index f91049585..1d844a66e 100644
--- a/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
@@ -70,9 +70,9 @@ static void vfp_double_dump(const char *str, struct vfp_double *d)
70 70
71static void vfp_double_normalise_denormal(struct vfp_double *vd) 71static void vfp_double_normalise_denormal(struct vfp_double *vd)
72{ 72{
73 int bits = 31 - fls((ARMword)(vd->significand >> 32)); 73 int bits = 31 - fls((u32)(vd->significand >> 32));
74 if (bits == 31) 74 if (bits == 31)
75 bits = 63 - fls((ARMword)vd->significand); 75 bits = 63 - fls((u32)vd->significand);
76 76
77 vfp_double_dump("normalise_denormal: in", vd); 77 vfp_double_dump("normalise_denormal: in", vd);
78 78
@@ -109,9 +109,9 @@ u32 vfp_double_normaliseround(ARMul_State* state, int dd, struct vfp_double *vd,
109 exponent = vd->exponent; 109 exponent = vd->exponent;
110 significand = vd->significand; 110 significand = vd->significand;
111 111
112 shift = 32 - fls((ARMword)(significand >> 32)); 112 shift = 32 - fls((u32)(significand >> 32));
113 if (shift == 32) 113 if (shift == 32)
114 shift = 64 - fls((ARMword)significand); 114 shift = 64 - fls((u32)significand);
115 if (shift) { 115 if (shift) {
116 exponent -= shift; 116 exponent -= shift;
117 significand <<= shift; 117 significand <<= shift;
@@ -566,7 +566,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
566 /* 566 /*
567 * 2^0 <= m < 2^32-2^8 567 * 2^0 <= m < 2^32-2^8
568 */ 568 */
569 d = (ARMword)((vdm.significand << 1) >> shift); 569 d = (u32)((vdm.significand << 1) >> shift);
570 rem = vdm.significand << (65 - shift); 570 rem = vdm.significand << (65 - shift);
571 571
572 if (rmode == FPSCR_ROUND_NEAREST) { 572 if (rmode == FPSCR_ROUND_NEAREST) {
@@ -647,7 +647,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
647 int shift = 1023 + 63 - vdm.exponent; /* 58 */ 647 int shift = 1023 + 63 - vdm.exponent; /* 58 */
648 u64 rem, incr = 0; 648 u64 rem, incr = 0;
649 649
650 d = (ARMword)((vdm.significand << 1) >> shift); 650 d = (u32)((vdm.significand << 1) >> shift);
651 rem = vdm.significand << (65 - shift); 651 rem = vdm.significand << (65 - shift);
652 652
653 if (rmode == FPSCR_ROUND_NEAREST) { 653 if (rmode == FPSCR_ROUND_NEAREST) {
diff --git a/src/core/hle/kernel/thread.cpp b/src/core/hle/kernel/thread.cpp
index 8b49fc7df..29ea6d531 100644
--- a/src/core/hle/kernel/thread.cpp
+++ b/src/core/hle/kernel/thread.cpp
@@ -13,7 +13,7 @@
13#include "common/thread_queue_list.h" 13#include "common/thread_queue_list.h"
14 14
15#include "core/arm/arm_interface.h" 15#include "core/arm/arm_interface.h"
16#include "core/arm/skyeye_common/armdefs.h" 16#include "core/arm/skyeye_common/armstate.h"
17#include "core/core.h" 17#include "core/core.h"
18#include "core/core_timing.h" 18#include "core/core_timing.h"
19#include "core/hle/hle.h" 19#include "core/hle/hle.h"
HIC SVNT DRACONES