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-rw-r--r--src/video_core/engines/shader_bytecode.h7
-rw-r--r--src/video_core/shader/decode/other.cpp6
2 files changed, 13 insertions, 0 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index 8520a0143..083ee3304 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -560,6 +560,11 @@ union Instruction {
560 BitField<48, 16, u64> opcode; 560 BitField<48, 16, u64> opcode;
561 561
562 union { 562 union {
563 BitField<8, 5, ConditionCode> cc;
564 BitField<13, 1, u64> trigger;
565 } nop;
566
567 union {
563 BitField<8, 8, Register> gpr; 568 BitField<8, 8, Register> gpr;
564 BitField<20, 24, s64> offset; 569 BitField<20, 24, s64> offset;
565 } gmem; 570 } gmem;
@@ -1516,6 +1521,7 @@ public:
1516 TMML, // Texture Mip Map Level 1521 TMML, // Texture Mip Map Level
1517 SUST, // Surface Store 1522 SUST, // Surface Store
1518 EXIT, 1523 EXIT,
1524 NOP,
1519 IPA, 1525 IPA,
1520 OUT_R, // Emit vertex/primitive 1526 OUT_R, // Emit vertex/primitive
1521 ISBERD, 1527 ISBERD,
@@ -1795,6 +1801,7 @@ private:
1795 INST("110111110110----", Id::TMML_B, Type::Texture, "TMML_B"), 1801 INST("110111110110----", Id::TMML_B, Type::Texture, "TMML_B"),
1796 INST("1101111101011---", Id::TMML, Type::Texture, "TMML"), 1802 INST("1101111101011---", Id::TMML, Type::Texture, "TMML"),
1797 INST("11101011001-----", Id::SUST, Type::Image, "SUST"), 1803 INST("11101011001-----", Id::SUST, Type::Image, "SUST"),
1804 INST("0101000010110---", Id::NOP, Type::Trivial, "NOP"),
1798 INST("11100000--------", Id::IPA, Type::Trivial, "IPA"), 1805 INST("11100000--------", Id::IPA, Type::Trivial, "IPA"),
1799 INST("1111101111100---", Id::OUT_R, Type::Trivial, "OUT_R"), 1806 INST("1111101111100---", Id::OUT_R, Type::Trivial, "OUT_R"),
1800 INST("1110111111010---", Id::ISBERD, Type::Trivial, "ISBERD"), 1807 INST("1110111111010---", Id::ISBERD, Type::Trivial, "ISBERD"),
diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp
index c0f64d7a0..ac0e764d6 100644
--- a/src/video_core/shader/decode/other.cpp
+++ b/src/video_core/shader/decode/other.cpp
@@ -22,6 +22,12 @@ u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) {
22 const auto opcode = OpCode::Decode(instr); 22 const auto opcode = OpCode::Decode(instr);
23 23
24 switch (opcode->get().GetId()) { 24 switch (opcode->get().GetId()) {
25 case OpCode::Id::NOP: {
26 UNIMPLEMENTED_IF(instr.nop.cc != Tegra::Shader::ConditionCode::T);
27 UNIMPLEMENTED_IF(instr.nop.trigger != 0);
28 // With the previous preconditions, this instruction is a no-operation.
29 break;
30 }
25 case OpCode::Id::EXIT: { 31 case OpCode::Id::EXIT: {
26 const Tegra::Shader::ConditionCode cc = instr.flow_condition_code; 32 const Tegra::Shader::ConditionCode cc = instr.flow_condition_code;
27 UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "EXIT condition code used: {}", 33 UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "EXIT condition code used: {}",