diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 54 |
1 files changed, 17 insertions, 37 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index f899e2e8a..233cd3e3a 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp | |||
| @@ -26,7 +26,7 @@ | |||
| 26 | #define CITRA_IGNORE_EXIT(x) | 26 | #define CITRA_IGNORE_EXIT(x) |
| 27 | 27 | ||
| 28 | #include <algorithm> | 28 | #include <algorithm> |
| 29 | #include <map> | 29 | #include <unordered_map> |
| 30 | #include <stdio.h> | 30 | #include <stdio.h> |
| 31 | #include <assert.h> | 31 | #include <assert.h> |
| 32 | #include <cstdio> | 32 | #include <cstdio> |
| @@ -94,9 +94,8 @@ typedef unsigned int (*shtop_fp_t)(arm_processor *cpu, unsigned int sht_oper); | |||
| 94 | 94 | ||
| 95 | /* exclusive memory access */ | 95 | /* exclusive memory access */ |
| 96 | static int exclusive_detect(ARMul_State* state, ARMword addr){ | 96 | static int exclusive_detect(ARMul_State* state, ARMword addr){ |
| 97 | int i; | ||
| 98 | #if 0 | 97 | #if 0 |
| 99 | for(i = 0; i < 128; i++){ | 98 | for(int i = 0; i < 128; i++){ |
| 100 | if(state->exclusive_tag_array[i] == addr) | 99 | if(state->exclusive_tag_array[i] == addr) |
| 101 | return 0; | 100 | return 0; |
| 102 | } | 101 | } |
| @@ -108,9 +107,8 @@ static int exclusive_detect(ARMul_State* state, ARMword addr){ | |||
| 108 | } | 107 | } |
| 109 | 108 | ||
| 110 | static void add_exclusive_addr(ARMul_State* state, ARMword addr){ | 109 | static void add_exclusive_addr(ARMul_State* state, ARMword addr){ |
| 111 | int i; | ||
| 112 | #if 0 | 110 | #if 0 |
| 113 | for(i = 0; i < 128; i++){ | 111 | for(int i = 0; i < 128; i++){ |
| 114 | if(state->exclusive_tag_array[i] == 0xffffffff){ | 112 | if(state->exclusive_tag_array[i] == 0xffffffff){ |
| 115 | state->exclusive_tag_array[i] = addr; | 113 | state->exclusive_tag_array[i] = addr; |
| 116 | //DEBUG_LOG(ARM11, "In %s, add addr 0x%x\n", __func__, addr); | 114 | //DEBUG_LOG(ARM11, "In %s, add addr 0x%x\n", __func__, addr); |
| @@ -3309,9 +3307,8 @@ const transop_fp_t arm_instruction_trans[] = { | |||
| 3309 | INTERPRETER_TRANSLATE(blx_1_thumb) | 3307 | INTERPRETER_TRANSLATE(blx_1_thumb) |
| 3310 | }; | 3308 | }; |
| 3311 | 3309 | ||
| 3312 | typedef map<unsigned int, int> bb_map; | 3310 | typedef std::unordered_map<u32, int> bb_map; |
| 3313 | bb_map CreamCache[65536]; | 3311 | bb_map CreamCache; |
| 3314 | bb_map ProfileCache[65536]; | ||
| 3315 | 3312 | ||
| 3316 | //#define USE_DUMMY_CACHE | 3313 | //#define USE_DUMMY_CACHE |
| 3317 | 3314 | ||
| @@ -3319,14 +3316,12 @@ bb_map ProfileCache[65536]; | |||
| 3319 | unsigned int DummyCache[0x100000]; | 3316 | unsigned int DummyCache[0x100000]; |
| 3320 | #endif | 3317 | #endif |
| 3321 | 3318 | ||
| 3322 | #define HASH(x) ((x + (x << 3) + (x >> 6)) % 65536) | ||
| 3323 | void insert_bb(unsigned int addr, int start) | 3319 | void insert_bb(unsigned int addr, int start) |
| 3324 | { | 3320 | { |
| 3325 | #ifdef USE_DUMMY_CACHE | 3321 | #ifdef USE_DUMMY_CACHE |
| 3326 | DummyCache[addr] = start; | 3322 | DummyCache[addr] = start; |
| 3327 | #else | 3323 | #else |
| 3328 | // CreamCache[addr] = start; | 3324 | CreamCache[addr] = start; |
| 3329 | CreamCache[HASH(addr)][addr] = start; | ||
| 3330 | #endif | 3325 | #endif |
| 3331 | } | 3326 | } |
| 3332 | 3327 | ||
| @@ -3341,8 +3336,8 @@ int find_bb(unsigned int addr, int &start) | |||
| 3341 | } else | 3336 | } else |
| 3342 | ret = -1; | 3337 | ret = -1; |
| 3343 | #else | 3338 | #else |
| 3344 | bb_map::const_iterator it = CreamCache[HASH(addr)].find(addr); | 3339 | bb_map::const_iterator it = CreamCache.find(addr); |
| 3345 | if (it != CreamCache[HASH(addr)].end()) { | 3340 | if (it != CreamCache.end()) { |
| 3346 | start = static_cast<int>(it->second); | 3341 | start = static_cast<int>(it->second); |
| 3347 | ret = 0; | 3342 | ret = 0; |
| 3348 | #if HYBRID_MODE | 3343 | #if HYBRID_MODE |
| @@ -3473,30 +3468,15 @@ void flush_bb(uint32_t addr) | |||
| 3473 | uint32_t start; | 3468 | uint32_t start; |
| 3474 | 3469 | ||
| 3475 | addr &= 0xfffff000; | 3470 | addr &= 0xfffff000; |
| 3476 | for (int i = 0; i < 65536; i ++) { | 3471 | for (it = CreamCache.begin(); it != CreamCache.end(); ) { |
| 3477 | for (it = CreamCache[i].begin(); it != CreamCache[i].end(); ) { | 3472 | start = static_cast<uint32_t>(it->first); |
| 3478 | start = static_cast<uint32_t>(it->first); | 3473 | //start = (start >> 12) << 12; |
| 3479 | //start = (start >> 12) << 12; | 3474 | start &= 0xfffff000; |
| 3480 | start &= 0xfffff000; | 3475 | if (start == addr) { |
| 3481 | if (start == addr) { | 3476 | //DEBUG_LOG(ARM11, "[ERASE][0x%08x]\n", static_cast<int>(it->first)); |
| 3482 | //DEBUG_LOG(ARM11, "[ERASE][0x%08x]\n", static_cast<int>(it->first)); | 3477 | CreamCache.erase(it++); |
| 3483 | CreamCache[i].erase(it ++); | 3478 | } else |
| 3484 | } else | 3479 | ++it; |
| 3485 | ++it; | ||
| 3486 | } | ||
| 3487 | } | ||
| 3488 | |||
| 3489 | for (int i = 0; i < 65536; i ++) { | ||
| 3490 | for (it = ProfileCache[i].begin(); it != ProfileCache[i].end(); ) { | ||
| 3491 | start = static_cast<uint32_t>(it->first); | ||
| 3492 | //start = (start >> 12) << 12; | ||
| 3493 | start &= 0xfffff000; | ||
| 3494 | if (start == addr) { | ||
| 3495 | //DEBUG_LOG(ARM11, "[ERASE][0x%08x]\n", static_cast<int>(it->first)); | ||
| 3496 | ProfileCache[i].erase(it ++); | ||
| 3497 | } else | ||
| 3498 | ++it; | ||
| 3499 | } | ||
| 3500 | } | 3480 | } |
| 3501 | 3481 | ||
| 3502 | //DEBUG_LOG(ARM11, "flush bb @ %x\n", addr); | 3482 | //DEBUG_LOG(ARM11, "flush bb @ %x\n", addr); |