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-rw-r--r--src/video_core/engines/shader_bytecode.h7
-rw-r--r--src/video_core/renderer_opengl/gl_shader_decompiler.cpp12
2 files changed, 13 insertions, 6 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index 663c1d4af..9d604afd5 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -243,7 +243,8 @@ enum class TextureType : u64 {
243 TextureCube = 3, 243 TextureCube = 3,
244}; 244};
245 245
246enum class IpaMode : u64 { Pass = 0, None = 1, Constant = 2, Sc = 3 }; 246enum class IpaInterpMode : u64 { Linear = 0, Perspective = 1, Flat = 2, Sc = 3 };
247enum class IpaSampleMode : u64 { Default = 0, Centroid = 1, Offset = 2 };
247 248
248union Instruction { 249union Instruction {
249 Instruction& operator=(const Instruction& instr) { 250 Instruction& operator=(const Instruction& instr) {
@@ -328,7 +329,9 @@ union Instruction {
328 } alu; 329 } alu;
329 330
330 union { 331 union {
331 BitField<54, 3, IpaMode> mode; 332 BitField<51, 1, u64> saturate;
333 BitField<52, 2, IpaSampleMode> sample_mode;
334 BitField<54, 2, IpaInterpMode> interp_mode;
332 } ipa; 335 } ipa;
333 336
334 union { 337 union {
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
index e7d581d2d..274c2854b 100644
--- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
+++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
@@ -2125,8 +2125,12 @@ private:
2125 case OpCode::Id::IPA: { 2125 case OpCode::Id::IPA: {
2126 const auto& attribute = instr.attribute.fmt28; 2126 const auto& attribute = instr.attribute.fmt28;
2127 const auto& reg = instr.gpr0; 2127 const auto& reg = instr.gpr0;
2128 switch (instr.ipa.mode) { 2128 ASSERT_MSG(instr.ipa.sample_mode == Tegra::Shader::IpaSampleMode::Default,
2129 case Tegra::Shader::IpaMode::Pass: 2129 "Unhandled IPA sample mode: {}",
2130 static_cast<u32>(instr.ipa.sample_mode.Value()));
2131 ASSERT_MSG(instr.ipa.saturate == 0, "IPA saturate not implemented");
2132 switch (instr.ipa.interp_mode) {
2133 case Tegra::Shader::IpaInterpMode::Linear:
2130 if (stage == Maxwell3D::Regs::ShaderStage::Fragment && 2134 if (stage == Maxwell3D::Regs::ShaderStage::Fragment &&
2131 attribute.index == Attribute::Index::Position) { 2135 attribute.index == Attribute::Index::Position) {
2132 switch (attribute.element) { 2136 switch (attribute.element) {
@@ -2147,12 +2151,12 @@ private:
2147 regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); 2151 regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
2148 } 2152 }
2149 break; 2153 break;
2150 case Tegra::Shader::IpaMode::None: 2154 case Tegra::Shader::IpaInterpMode::Perspective:
2151 regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); 2155 regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
2152 break; 2156 break;
2153 default: 2157 default:
2154 LOG_CRITICAL(HW_GPU, "Unhandled IPA mode: {}", 2158 LOG_CRITICAL(HW_GPU, "Unhandled IPA mode: {}",
2155 static_cast<u32>(instr.ipa.mode.Value())); 2159 static_cast<u32>(instr.ipa.interp_mode.Value()));
2156 UNREACHABLE(); 2160 UNREACHABLE();
2157 regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); 2161 regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
2158 } 2162 }