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-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp61
1 files changed, 58 insertions, 3 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index f2ea0e9dd..7ba82503d 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -2766,7 +2766,29 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab)(unsigned int inst, int index){
2766 2766
2767 return inst_base; 2767 return inst_base;
2768} 2768}
2769ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SXTAB16"); } 2769
2770ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab16)(unsigned int inst, int index)
2771{
2772 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(sxtab_inst));
2773 sxtab_inst* const inst_cream = (sxtab_inst*)inst_base->component;
2774
2775 inst_base->cond = BITS(inst, 28, 31);
2776 inst_base->idx = index;
2777 inst_base->br = NON_BRANCH;
2778 inst_base->load_r15 = 0;
2779
2780 inst_cream->Rm = BITS(inst, 0, 3);
2781 inst_cream->Rn = BITS(inst, 16, 19);
2782 inst_cream->Rd = BITS(inst, 12, 15);
2783 inst_cream->rotate = BITS(inst, 10, 11);
2784
2785 return inst_base;
2786}
2787ARM_INST_PTR INTERPRETER_TRANSLATE(sxtb16)(unsigned int inst, int index)
2788{
2789 return INTERPRETER_TRANSLATE(sxtab16)(inst, index);
2790}
2791
2770ARM_INST_PTR INTERPRETER_TRANSLATE(sxtah)(unsigned int inst, int index){ 2792ARM_INST_PTR INTERPRETER_TRANSLATE(sxtah)(unsigned int inst, int index){
2771 LOG_WARNING(Core_ARM11, "SXTAH untested"); 2793 LOG_WARNING(Core_ARM11, "SXTAH untested");
2772 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sxtah_inst)); 2794 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sxtah_inst));
@@ -2784,7 +2806,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(sxtah)(unsigned int inst, int index){
2784 2806
2785 return inst_base; 2807 return inst_base;
2786} 2808}
2787ARM_INST_PTR INTERPRETER_TRANSLATE(sxtb16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SXTB16"); } 2809
2788ARM_INST_PTR INTERPRETER_TRANSLATE(teq)(unsigned int inst, int index) 2810ARM_INST_PTR INTERPRETER_TRANSLATE(teq)(unsigned int inst, int index)
2789{ 2811{
2790 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(teq_inst)); 2812 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(teq_inst));
@@ -5896,7 +5918,40 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
5896 FETCH_INST; 5918 FETCH_INST;
5897 GOTO_NEXT_INST; 5919 GOTO_NEXT_INST;
5898 } 5920 }
5921
5899 SXTAB16_INST: 5922 SXTAB16_INST:
5923 SXTB16_INST:
5924 {
5925 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
5926 sxtab_inst* const inst_cream = (sxtab_inst*)inst_base->component;
5927
5928 const u8 rotation = inst_cream->rotate * 8;
5929 u32 rm_val = RM;
5930 u32 rn_val = RN;
5931
5932 if (rotation)
5933 rm_val = ((rm_val << (32 - rotation)) | (rm_val >> rotation));
5934
5935 // SXTB16
5936 if (inst_cream->Rn == 15) {
5937 u32 lo = (u32)(s8)rm_val;
5938 u32 hi = (u32)(s8)(rm_val >> 16);
5939 RD = (lo | (hi << 16));
5940 }
5941 // SXTAB16
5942 else {
5943 u32 lo = (rn_val & 0xFFFF) + (u32)(s8)(rm_val & 0xFF);
5944 u32 hi = ((rn_val >> 16) & 0xFFFF) + (u32)(s8)((rm_val >> 16) & 0xFF);
5945 RD = (lo | (hi << 16));
5946 }
5947 }
5948
5949 cpu->Reg[15] += GET_INST_SIZE(cpu);
5950 INC_PC(sizeof(sxtab_inst));
5951 FETCH_INST;
5952 GOTO_NEXT_INST;
5953 }
5954
5900 SXTAH_INST: 5955 SXTAH_INST:
5901 { 5956 {
5902 sxtah_inst *inst_cream = (sxtah_inst *)inst_base->component; 5957 sxtah_inst *inst_cream = (sxtah_inst *)inst_base->component;
@@ -5915,7 +5970,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
5915 FETCH_INST; 5970 FETCH_INST;
5916 GOTO_NEXT_INST; 5971 GOTO_NEXT_INST;
5917 } 5972 }
5918 SXTB16_INST: 5973
5919 TEQ_INST: 5974 TEQ_INST:
5920 { 5975 {
5921 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 5976 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {