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-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp8
1 files changed, 2 insertions, 6 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 9ed61947e..a6faf42b9 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -3955,9 +3955,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
3955 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3955 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3956 add_inst* const inst_cream = (add_inst*)inst_base->component; 3956 add_inst* const inst_cream = (add_inst*)inst_base->component;
3957 3957
3958 u32 rn_val = RN; 3958 u32 rn_val = CHECK_READ_REG15_WA(cpu, inst_cream->Rn);
3959 if (inst_cream->Rn == 15)
3960 rn_val += 2 * cpu->GetInstructionSize();
3961 3959
3962 bool carry; 3960 bool carry;
3963 bool overflow; 3961 bool overflow;
@@ -6167,9 +6165,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
6167 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 6165 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
6168 sub_inst* const inst_cream = (sub_inst*)inst_base->component; 6166 sub_inst* const inst_cream = (sub_inst*)inst_base->component;
6169 6167
6170 u32 rn_val = RN; 6168 u32 rn_val = CHECK_READ_REG15_WA(cpu, inst_cream->Rn);
6171 if (inst_cream->Rn == 15)
6172 rn_val += 2 * cpu->GetInstructionSize();
6173 6169
6174 bool carry; 6170 bool carry;
6175 bool overflow; 6171 bool overflow;