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-rw-r--r--src/citra_qt/debugger/graphics.cpp34
-rw-r--r--src/common/register_set.h14
-rw-r--r--src/core/hle/config_mem.h6
-rw-r--r--src/core/hle/service/gsp.cpp143
-rw-r--r--src/core/hle/service/gsp.h60
-rw-r--r--src/core/hw/gpu.cpp253
-rw-r--r--src/core/hw/gpu.h219
-rw-r--r--src/core/hw/hw.h4
-rw-r--r--src/video_core/gpu_debugger.h11
-rw-r--r--src/video_core/renderer_opengl/renderer_opengl.cpp62
-rw-r--r--src/video_core/renderer_opengl/renderer_opengl.h7
11 files changed, 585 insertions, 228 deletions
diff --git a/src/citra_qt/debugger/graphics.cpp b/src/citra_qt/debugger/graphics.cpp
index 9aaade8f9..0f911a015 100644
--- a/src/citra_qt/debugger/graphics.cpp
+++ b/src/citra_qt/debugger/graphics.cpp
@@ -28,22 +28,24 @@ QVariant GPUCommandStreamItemModel::data(const QModelIndex& index, int role) con
28 const GSP_GPU::GXCommand& command = GetDebugger()->ReadGXCommandHistory(command_index); 28 const GSP_GPU::GXCommand& command = GetDebugger()->ReadGXCommandHistory(command_index);
29 if (role == Qt::DisplayRole) 29 if (role == Qt::DisplayRole)
30 { 30 {
31 std::map<GSP_GPU::GXCommandId, const char*> command_names; 31 std::map<GSP_GPU::GXCommandId, const char*> command_names = {
32 command_names[GSP_GPU::GXCommandId::REQUEST_DMA] = "REQUEST_DMA"; 32 { GSP_GPU::GXCommandId::REQUEST_DMA, "REQUEST_DMA" },
33 command_names[GSP_GPU::GXCommandId::SET_COMMAND_LIST_FIRST] = "SET_COMMAND_LIST_FIRST"; 33 { GSP_GPU::GXCommandId::SET_COMMAND_LIST_FIRST, "SET_COMMAND_LIST_FIRST" },
34 command_names[GSP_GPU::GXCommandId::SET_MEMORY_FILL] = "SET_MEMORY_FILL"; 34 { GSP_GPU::GXCommandId::SET_MEMORY_FILL, "SET_MEMORY_FILL" },
35 command_names[GSP_GPU::GXCommandId::SET_DISPLAY_TRANSFER] = "SET_DISPLAY_TRANSFER"; 35 { GSP_GPU::GXCommandId::SET_DISPLAY_TRANSFER, "SET_DISPLAY_TRANSFER" },
36 command_names[GSP_GPU::GXCommandId::SET_TEXTURE_COPY] = "SET_TEXTURE_COPY"; 36 { GSP_GPU::GXCommandId::SET_TEXTURE_COPY, "SET_TEXTURE_COPY" },
37 command_names[GSP_GPU::GXCommandId::SET_COMMAND_LIST_LAST] = "SET_COMMAND_LIST_LAST"; 37 { GSP_GPU::GXCommandId::SET_COMMAND_LIST_LAST, "SET_COMMAND_LIST_LAST" }
38 QString str = QString("%1 %2 %3 %4 %5 %6 %7 %8 %9").arg(command_names[static_cast<GSP_GPU::GXCommandId>(command.id)]) 38 };
39 .arg(command.data[0], 8, 16, QLatin1Char('0')) 39 const u32* command_data = reinterpret_cast<const u32*>(&command);
40 .arg(command.data[1], 8, 16, QLatin1Char('0')) 40 QString str = QString("%1 %2 %3 %4 %5 %6 %7 %8 %9").arg(command_names[command.id])
41 .arg(command.data[2], 8, 16, QLatin1Char('0')) 41 .arg(command_data[0], 8, 16, QLatin1Char('0'))
42 .arg(command.data[3], 8, 16, QLatin1Char('0')) 42 .arg(command_data[1], 8, 16, QLatin1Char('0'))
43 .arg(command.data[4], 8, 16, QLatin1Char('0')) 43 .arg(command_data[2], 8, 16, QLatin1Char('0'))
44 .arg(command.data[5], 8, 16, QLatin1Char('0')) 44 .arg(command_data[3], 8, 16, QLatin1Char('0'))
45 .arg(command.data[6], 8, 16, QLatin1Char('0')) 45 .arg(command_data[4], 8, 16, QLatin1Char('0'))
46 .arg(command.data[7], 8, 16, QLatin1Char('0')); 46 .arg(command_data[5], 8, 16, QLatin1Char('0'))
47 .arg(command_data[6], 8, 16, QLatin1Char('0'))
48 .arg(command_data[7], 8, 16, QLatin1Char('0'));
47 return QVariant(str); 49 return QVariant(str);
48 } 50 }
49 else 51 else
diff --git a/src/common/register_set.h b/src/common/register_set.h
index 0418551b3..ba19a2614 100644
--- a/src/common/register_set.h
+++ b/src/common/register_set.h
@@ -34,7 +34,7 @@
34/* 34/*
35 * Standardized way to define a group of registers and corresponding data structures. To define 35 * Standardized way to define a group of registers and corresponding data structures. To define
36 * a new register set, first define struct containing an enumeration called "Id" containing 36 * a new register set, first define struct containing an enumeration called "Id" containing
37 * all register IDs and a template union called "Struct". Specialize the Struct union for any 37 * all register IDs and a template struct called "Struct". Specialize the Struct struct for any
38 * register ID which needs to be accessed in a specialized way. You can then declare the object 38 * register ID which needs to be accessed in a specialized way. You can then declare the object
39 * containing all register values using the RegisterSet<BaseType, DefiningStruct> type, where 39 * containing all register values using the RegisterSet<BaseType, DefiningStruct> type, where
40 * BaseType is the underlying type of each register (e.g. u32). 40 * BaseType is the underlying type of each register (e.g. u32).
@@ -54,7 +54,7 @@
54 * 54 *
55 * // declare register definition structures 55 * // declare register definition structures
56 * template<Id id> 56 * template<Id id>
57 * union Struct; 57 * struct Struct;
58 * }; 58 * };
59 * 59 *
60 * // Define register set object 60 * // Define register set object
@@ -62,9 +62,11 @@
62 * 62 *
63 * // define register definition structures 63 * // define register definition structures
64 * template<> 64 * template<>
65 * union Regs::Struct<Regs::Value1> { 65 * struct Regs::Struct<Regs::Value1> {
66 * BitField<0, 4, u32> some_field; 66 * union {
67 * BitField<4, 3, u32> some_other_field; 67 * BitField<0, 4, u32> some_field;
68 * BitField<4, 3, u32> some_other_field;
69 * };
68 * }; 70 * };
69 * 71 *
70 * Usage in external code (within SomeNamespace scope): 72 * Usage in external code (within SomeNamespace scope):
@@ -77,7 +79,7 @@
77 * 79 *
78 * 80 *
79 * @tparam BaseType Base type used for storing individual registers, e.g. u32 81 * @tparam BaseType Base type used for storing individual registers, e.g. u32
80 * @tparam RegDefinition Class defining an enumeration called "Id" and a template<Id id> union, as described above. 82 * @tparam RegDefinition Class defining an enumeration called "Id" and a template<Id id> struct, as described above.
81 * @note RegDefinition::Id needs to have an enum value called NumIds defining the number of registers to be allocated. 83 * @note RegDefinition::Id needs to have an enum value called NumIds defining the number of registers to be allocated.
82 */ 84 */
83template<typename BaseType, typename RegDefinition> 85template<typename BaseType, typename RegDefinition>
diff --git a/src/core/hle/config_mem.h b/src/core/hle/config_mem.h
index da396a3e6..fa01b5cdb 100644
--- a/src/core/hle/config_mem.h
+++ b/src/core/hle/config_mem.h
@@ -1,10 +1,10 @@
1// Copyright 2014 Citra Emulator Project 1// Copyright 2014 Citra Emulator Project
2// Licensed under GPLv2 2// Licensed under GPLv2
3// Refer to the license.txt file included. 3// Refer to the license.txt file included.
4 4
5#pragma once 5#pragma once
6 6
7// Configuration memory stores various hardware/kernel configuration settings. This memory page is 7// Configuration memory stores various hardware/kernel configuration settings. This memory page is
8// read-only for ARM11 processes. I'm guessing this would normally be written to by the firmware/ 8// read-only for ARM11 processes. I'm guessing this would normally be written to by the firmware/
9// bootrom. Because we're not emulating this, and essentially just "stubbing" the functionality, I'm 9// bootrom. Because we're not emulating this, and essentially just "stubbing" the functionality, I'm
10// putting this as a subset of HLE for now. 10// putting this as a subset of HLE for now.
@@ -16,6 +16,6 @@
16namespace ConfigMem { 16namespace ConfigMem {
17 17
18template <typename T> 18template <typename T>
19inline void Read(T &var, const u32 addr); 19void Read(T &var, const u32 addr);
20 20
21} // namespace 21} // namespace
diff --git a/src/core/hle/service/gsp.cpp b/src/core/hle/service/gsp.cpp
index 1fdbdf342..b20203e27 100644
--- a/src/core/hle/service/gsp.cpp
+++ b/src/core/hle/service/gsp.cpp
@@ -47,11 +47,6 @@ Handle g_shared_memory = 0;
47 47
48u32 g_thread_id = 0; 48u32 g_thread_id = 0;
49 49
50enum {
51 REG_FRAMEBUFFER_1 = 0x00400468,
52 REG_FRAMEBUFFER_2 = 0x00400494,
53};
54
55/// Gets a pointer to the start (header) of a command buffer in GSP shared memory 50/// Gets a pointer to the start (header) of a command buffer in GSP shared memory
56static inline u8* GX_GetCmdBufferPointer(u32 thread_id, u32 offset=0) { 51static inline u8* GX_GetCmdBufferPointer(u32 thread_id, u32 offset=0) {
57 return Kernel::GetSharedMemoryPointer(g_shared_memory, 0x800 + (thread_id * 0x200) + offset); 52 return Kernel::GetSharedMemoryPointer(g_shared_memory, 0x800 + (thread_id * 0x200) + offset);
@@ -67,38 +62,62 @@ void GX_FinishCommand(u32 thread_id) {
67 // TODO: Increment header->index? 62 // TODO: Increment header->index?
68} 63}
69 64
65/// Write a GSP GPU hardware register
66void WriteHWRegs(Service::Interface* self) {
67 u32* cmd_buff = Service::GetCommandBuffer();
68 u32 reg_addr = cmd_buff[1];
69 u32 size = cmd_buff[2];
70
71 // TODO: Return proper error codes
72 if (reg_addr + size >= 0x420000) {
73 ERROR_LOG(GPU, "Write address out of range! (address=0x%08x, size=0x%08x)", reg_addr, size);
74 return;
75 }
76
77 // size should be word-aligned
78 if ((size % 4) != 0) {
79 ERROR_LOG(GPU, "Invalid size 0x%08x", size);
80 return;
81 }
82
83 u32* src = (u32*)Memory::GetPointer(cmd_buff[0x4]);
84
85 while (size > 0) {
86 GPU::Write<u32>(reg_addr + 0x1EB00000, *src);
87
88 size -= 4;
89 ++src;
90 reg_addr += 4;
91 }
92}
93
70/// Read a GSP GPU hardware register 94/// Read a GSP GPU hardware register
71void ReadHWRegs(Service::Interface* self) { 95void ReadHWRegs(Service::Interface* self) {
72 static const u32 framebuffer_1[] = {GPU::PADDR_VRAM_TOP_LEFT_FRAME1, GPU::PADDR_VRAM_TOP_RIGHT_FRAME1};
73 static const u32 framebuffer_2[] = {GPU::PADDR_VRAM_TOP_LEFT_FRAME2, GPU::PADDR_VRAM_TOP_RIGHT_FRAME2};
74
75 u32* cmd_buff = Service::GetCommandBuffer(); 96 u32* cmd_buff = Service::GetCommandBuffer();
76 u32 reg_addr = cmd_buff[1]; 97 u32 reg_addr = cmd_buff[1];
77 u32 size = cmd_buff[2]; 98 u32 size = cmd_buff[2];
78 u32* dst = (u32*)Memory::GetPointer(cmd_buff[0x41]);
79 99
80 switch (reg_addr) { 100 // TODO: Return proper error codes
101 if (reg_addr + size >= 0x420000) {
102 ERROR_LOG(GPU, "Read address out of range! (address=0x%08x, size=0x%08x)", reg_addr, size);
103 return;
104 }
81 105
82 // NOTE: Calling SetFramebufferLocation here is a hack... Not sure the correct way yet to set 106 // size should be word-aligned
83 // whether the framebuffers should be in VRAM or GSP heap, but from what I understand, if the 107 if ((size % 4) != 0) {
84 // user application is reading from either of these registers, then its going to be in VRAM. 108 ERROR_LOG(GPU, "Invalid size 0x%08x", size);
109 return;
110 }
85 111
86 // Top framebuffer 1 addresses 112 u32* dst = (u32*)Memory::GetPointer(cmd_buff[0x41]);
87 case REG_FRAMEBUFFER_1:
88 GPU::SetFramebufferLocation(GPU::FRAMEBUFFER_LOCATION_VRAM);
89 memcpy(dst, framebuffer_1, size);
90 break;
91 113
92 // Top framebuffer 2 addresses 114 while (size > 0) {
93 case REG_FRAMEBUFFER_2: 115 GPU::Read<u32>(*dst, reg_addr + 0x1EB00000);
94 GPU::SetFramebufferLocation(GPU::FRAMEBUFFER_LOCATION_VRAM);
95 memcpy(dst, framebuffer_2, size);
96 break;
97 116
98 default: 117 size -= 4;
99 ERROR_LOG(GSP, "unknown register read at address %08X", reg_addr); 118 ++dst;
119 reg_addr += 4;
100 } 120 }
101
102} 121}
103 122
104/** 123/**
@@ -120,8 +139,8 @@ void RegisterInterruptRelayQueue(Service::Interface* self) {
120 139
121 Kernel::SetEventLocked(g_event, false); 140 Kernel::SetEventLocked(g_event, false);
122 141
123 // Hack - This function will permanently set the state of the GSP event such that GPU command 142 // Hack - This function will permanently set the state of the GSP event such that GPU command
124 // synchronization barriers always passthrough. Correct solution would be to set this after the 143 // synchronization barriers always passthrough. Correct solution would be to set this after the
125 // GPU as processed all queued up commands, but due to the emulator being single-threaded they 144 // GPU as processed all queued up commands, but due to the emulator being single-threaded they
126 // will always be ready. 145 // will always be ready.
127 Kernel::SetPermanentLock(g_event, true); 146 Kernel::SetPermanentLock(g_event, true);
@@ -134,52 +153,92 @@ void RegisterInterruptRelayQueue(Service::Interface* self) {
134 153
135/// This triggers handling of the GX command written to the command buffer in shared memory. 154/// This triggers handling of the GX command written to the command buffer in shared memory.
136void TriggerCmdReqQueue(Service::Interface* self) { 155void TriggerCmdReqQueue(Service::Interface* self) {
156
157 // Utility function to convert register ID to address
158 auto WriteGPURegister = [](u32 id, u32 data) {
159 GPU::Write<u32>(0x1EF00000 + 4 * id, data);
160 };
161
137 GX_CmdBufferHeader* header = (GX_CmdBufferHeader*)GX_GetCmdBufferPointer(g_thread_id); 162 GX_CmdBufferHeader* header = (GX_CmdBufferHeader*)GX_GetCmdBufferPointer(g_thread_id);
138 u32* cmd_buff = (u32*)GX_GetCmdBufferPointer(g_thread_id, 0x20 + (header->index * 0x20)); 163 auto& command = *(const GXCommand*)GX_GetCmdBufferPointer(g_thread_id, 0x20 + (header->index * 0x20));
139 164
140 switch (static_cast<GXCommandId>(cmd_buff[0])) { 165 switch (command.id) {
141 166
142 // GX request DMA - typically used for copying memory from GSP heap to VRAM 167 // GX request DMA - typically used for copying memory from GSP heap to VRAM
143 case GXCommandId::REQUEST_DMA: 168 case GXCommandId::REQUEST_DMA:
144 memcpy(Memory::GetPointer(cmd_buff[2]), Memory::GetPointer(cmd_buff[1]), cmd_buff[3]); 169 memcpy(Memory::GetPointer(command.dma_request.dest_address),
170 Memory::GetPointer(command.dma_request.source_address),
171 command.dma_request.size);
145 break; 172 break;
146 173
174 // ctrulib homebrew sends all relevant command list data with this command,
175 // hence we do all "interesting" stuff here and do nothing in SET_COMMAND_LIST_FIRST.
176 // TODO: This will need some rework in the future.
147 case GXCommandId::SET_COMMAND_LIST_LAST: 177 case GXCommandId::SET_COMMAND_LIST_LAST:
148 GPU::Write<u32>(GPU::Registers::CommandListAddress, cmd_buff[1] >> 3); 178 {
149 GPU::Write<u32>(GPU::Registers::CommandListSize, cmd_buff[2] >> 3); 179 auto& params = command.set_command_list_last;
150 GPU::Write<u32>(GPU::Registers::ProcessCommandList, 1); // TODO: Not sure if we are supposed to always write this 180 WriteGPURegister(GPU::Regs::CommandProcessor + 2, params.address >> 3);
181 WriteGPURegister(GPU::Regs::CommandProcessor, params.size >> 3);
182 WriteGPURegister(GPU::Regs::CommandProcessor + 4, 1); // TODO: Not sure if we are supposed to always write this .. seems to trigger processing though
151 183
152 // TODO: Move this to GPU 184 // TODO: Move this to GPU
153 // TODO: Not sure what units the size is measured in 185 // TODO: Not sure what units the size is measured in
154 g_debugger.CommandListCalled(cmd_buff[1], (u32*)Memory::GetPointer(cmd_buff[1]), cmd_buff[2]); 186 g_debugger.CommandListCalled(params.address,
187 (u32*)Memory::GetPointer(params.address),
188 params.size);
155 break; 189 break;
190 }
156 191
192 // It's assumed that the two "blocks" behave equivalently.
193 // Presumably this is done simply to allow two memory fills to run in parallel.
157 case GXCommandId::SET_MEMORY_FILL: 194 case GXCommandId::SET_MEMORY_FILL:
195 {
196 auto& params = command.memory_fill;
197 WriteGPURegister(GPU::Regs::MemoryFill, params.start1 >> 3);
198 WriteGPURegister(GPU::Regs::MemoryFill + 1, params.end1 >> 3);
199 WriteGPURegister(GPU::Regs::MemoryFill + 2, params.end1 - params.start1);
200 WriteGPURegister(GPU::Regs::MemoryFill + 3, params.value1);
201
202 WriteGPURegister(GPU::Regs::MemoryFill + 4, params.start2 >> 3);
203 WriteGPURegister(GPU::Regs::MemoryFill + 5, params.end2 >> 3);
204 WriteGPURegister(GPU::Regs::MemoryFill + 6, params.end2 - params.start2);
205 WriteGPURegister(GPU::Regs::MemoryFill + 7, params.value2);
158 break; 206 break;
207 }
159 208
209 // TODO: Check if texture copies are implemented correctly..
160 case GXCommandId::SET_DISPLAY_TRANSFER: 210 case GXCommandId::SET_DISPLAY_TRANSFER:
161 break;
162
163 case GXCommandId::SET_TEXTURE_COPY: 211 case GXCommandId::SET_TEXTURE_COPY:
212 {
213 auto& params = command.image_copy;
214 WriteGPURegister(GPU::Regs::DisplayTransfer, params.in_buffer_address >> 3);
215 WriteGPURegister(GPU::Regs::DisplayTransfer + 1, params.out_buffer_address >> 3);
216 WriteGPURegister(GPU::Regs::DisplayTransfer + 3, params.in_buffer_size);
217 WriteGPURegister(GPU::Regs::DisplayTransfer + 2, params.out_buffer_size);
218 WriteGPURegister(GPU::Regs::DisplayTransfer + 4, params.flags);
219
220 // TODO: Should this only be ORed with 1 for texture copies?
221 // trigger transfer
222 WriteGPURegister(GPU::Regs::DisplayTransfer + 6, 1);
164 break; 223 break;
224 }
165 225
226 // TODO: Figure out what exactly SET_COMMAND_LIST_FIRST and SET_COMMAND_LIST_LAST
227 // are supposed to do.
166 case GXCommandId::SET_COMMAND_LIST_FIRST: 228 case GXCommandId::SET_COMMAND_LIST_FIRST:
167 { 229 {
168 //u32* buf0_data = (u32*)Memory::GetPointer(cmd_buff[1]);
169 //u32* buf1_data = (u32*)Memory::GetPointer(cmd_buff[3]);
170 //u32* buf2_data = (u32*)Memory::GetPointer(cmd_buff[5]);
171 break; 230 break;
172 } 231 }
173 232
174 default: 233 default:
175 ERROR_LOG(GSP, "unknown command 0x%08X", cmd_buff[0]); 234 ERROR_LOG(GSP, "unknown command 0x%08X", (int)command.id.Value());
176 } 235 }
177 236
178 GX_FinishCommand(g_thread_id); 237 GX_FinishCommand(g_thread_id);
179} 238}
180 239
181const Interface::FunctionInfo FunctionTable[] = { 240const Interface::FunctionInfo FunctionTable[] = {
182 {0x00010082, nullptr, "WriteHWRegs"}, 241 {0x00010082, WriteHWRegs, "WriteHWRegs"},
183 {0x00020084, nullptr, "WriteHWRegsWithMask"}, 242 {0x00020084, nullptr, "WriteHWRegsWithMask"},
184 {0x00030082, nullptr, "WriteHWRegRepeat"}, 243 {0x00030082, nullptr, "WriteHWRegRepeat"},
185 {0x00040080, ReadHWRegs, "ReadHWRegs"}, 244 {0x00040080, ReadHWRegs, "ReadHWRegs"},
diff --git a/src/core/hle/service/gsp.h b/src/core/hle/service/gsp.h
index 214de140f..a83cb4846 100644
--- a/src/core/hle/service/gsp.h
+++ b/src/core/hle/service/gsp.h
@@ -4,6 +4,7 @@
4 4
5#pragma once 5#pragma once
6 6
7#include "common/bit_field.h"
7#include "core/hle/service/service.h" 8#include "core/hle/service/service.h"
8 9
9//////////////////////////////////////////////////////////////////////////////////////////////////// 10////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -12,21 +13,58 @@
12namespace GSP_GPU { 13namespace GSP_GPU {
13 14
14enum class GXCommandId : u32 { 15enum class GXCommandId : u32 {
15 REQUEST_DMA = 0x00000000, 16 REQUEST_DMA = 0x00,
16 SET_COMMAND_LIST_LAST = 0x00000001, 17 SET_COMMAND_LIST_LAST = 0x01,
17 SET_MEMORY_FILL = 0x00000002, // TODO: Confirm? (lictru uses 0x01000102) 18
18 SET_DISPLAY_TRANSFER = 0x00000003, 19 // Fills a given memory range with a particular value
19 SET_TEXTURE_COPY = 0x00000004, 20 SET_MEMORY_FILL = 0x02,
20 SET_COMMAND_LIST_FIRST = 0x00000005, 21
22 // Copies an image and optionally performs color-conversion or scaling.
23 // This is highly similar to the GameCube's EFB copy feature
24 SET_DISPLAY_TRANSFER = 0x03,
25
26 // Conceptionally similar to SET_DISPLAY_TRANSFER and presumable uses the same hardware path
27 SET_TEXTURE_COPY = 0x04,
28
29 SET_COMMAND_LIST_FIRST = 0x05,
21}; 30};
22 31
23union GXCommand { 32struct GXCommand {
24 struct { 33 BitField<0, 8, GXCommandId> id;
25 GXCommandId id;
26 };
27 34
28 u32 data[0x20]; 35 union {
36 struct {
37 u32 source_address;
38 u32 dest_address;
39 u32 size;
40 } dma_request;
41
42 struct {
43 u32 address;
44 u32 size;
45 } set_command_list_last;
46
47 struct {
48 u32 start1;
49 u32 value1;
50 u32 end1;
51 u32 start2;
52 u32 value2;
53 u32 end2;
54 } memory_fill;
55
56 struct {
57 u32 in_buffer_address;
58 u32 out_buffer_address;
59 u32 in_buffer_size;
60 u32 out_buffer_size;
61 u32 flags;
62 } image_copy;
63
64 u8 raw_data[0x1C];
65 };
29}; 66};
67static_assert(sizeof(GXCommand) == 0x20, "GXCommand struct has incorrect size");
30 68
31/// Interface to "srv:" service 69/// Interface to "srv:" service
32class Interface : public Service::Interface { 70class Interface : public Service::Interface {
diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp
index f0ca4eada..c00be2a83 100644
--- a/src/core/hw/gpu.cpp
+++ b/src/core/hw/gpu.cpp
@@ -15,48 +15,58 @@
15 15
16namespace GPU { 16namespace GPU {
17 17
18Registers g_regs; 18RegisterSet<u32, Regs> g_regs;
19 19
20u64 g_last_ticks = 0; ///< Last CPU ticks 20u64 g_last_ticks = 0; ///< Last CPU ticks
21 21
22/** 22/**
23 * Sets whether the framebuffers are in the GSP heap (FCRAM) or VRAM 23 * Sets whether the framebuffers are in the GSP heap (FCRAM) or VRAM
24 * @param 24 * @param
25 */ 25 */
26void SetFramebufferLocation(const FramebufferLocation mode) { 26void SetFramebufferLocation(const FramebufferLocation mode) {
27 switch (mode) { 27 switch (mode) {
28 case FRAMEBUFFER_LOCATION_FCRAM: 28 case FRAMEBUFFER_LOCATION_FCRAM:
29 g_regs.framebuffer_top_left_1 = PADDR_TOP_LEFT_FRAME1; 29 {
30 g_regs.framebuffer_top_left_2 = PADDR_TOP_LEFT_FRAME2; 30 auto& framebuffer_top = g_regs.Get<Regs::FramebufferTop>();
31 g_regs.framebuffer_top_right_1 = PADDR_TOP_RIGHT_FRAME1; 31 auto& framebuffer_sub = g_regs.Get<Regs::FramebufferBottom>();
32 g_regs.framebuffer_top_right_2 = PADDR_TOP_RIGHT_FRAME2; 32
33 g_regs.framebuffer_sub_left_1 = PADDR_SUB_FRAME1; 33 framebuffer_top.address_left1 = PADDR_TOP_LEFT_FRAME1;
34 //g_regs.framebuffer_sub_left_2 = unknown; 34 framebuffer_top.address_left2 = PADDR_TOP_LEFT_FRAME2;
35 g_regs.framebuffer_sub_right_1 = PADDR_SUB_FRAME2; 35 framebuffer_top.address_right1 = PADDR_TOP_RIGHT_FRAME1;
36 //g_regs.framebufferr_sub_right_2 = unknown; 36 framebuffer_top.address_right2 = PADDR_TOP_RIGHT_FRAME2;
37 framebuffer_sub.address_left1 = PADDR_SUB_FRAME1;
38 //framebuffer_sub.address_left2 = unknown;
39 framebuffer_sub.address_right1 = PADDR_SUB_FRAME2;
40 //framebuffer_sub.address_right2 = unknown;
37 break; 41 break;
42 }
38 43
39 case FRAMEBUFFER_LOCATION_VRAM: 44 case FRAMEBUFFER_LOCATION_VRAM:
40 g_regs.framebuffer_top_left_1 = PADDR_VRAM_TOP_LEFT_FRAME1; 45 {
41 g_regs.framebuffer_top_left_2 = PADDR_VRAM_TOP_LEFT_FRAME2; 46 auto& framebuffer_top = g_regs.Get<Regs::FramebufferTop>();
42 g_regs.framebuffer_top_right_1 = PADDR_VRAM_TOP_RIGHT_FRAME1; 47 auto& framebuffer_sub = g_regs.Get<Regs::FramebufferBottom>();
43 g_regs.framebuffer_top_right_2 = PADDR_VRAM_TOP_RIGHT_FRAME2; 48
44 g_regs.framebuffer_sub_left_1 = PADDR_VRAM_SUB_FRAME1; 49 framebuffer_top.address_left1 = PADDR_VRAM_TOP_LEFT_FRAME1;
45 //g_regs.framebuffer_sub_left_2 = unknown; 50 framebuffer_top.address_left2 = PADDR_VRAM_TOP_LEFT_FRAME2;
46 g_regs.framebuffer_sub_right_1 = PADDR_VRAM_SUB_FRAME2; 51 framebuffer_top.address_right1 = PADDR_VRAM_TOP_RIGHT_FRAME1;
47 //g_regs.framebufferr_sub_right_2 = unknown; 52 framebuffer_top.address_right2 = PADDR_VRAM_TOP_RIGHT_FRAME2;
53 framebuffer_sub.address_left1 = PADDR_VRAM_SUB_FRAME1;
54 //framebuffer_sub.address_left2 = unknown;
55 framebuffer_sub.address_right1 = PADDR_VRAM_SUB_FRAME2;
56 //framebuffer_sub.address_right2 = unknown;
48 break; 57 break;
49 } 58 }
59 }
50} 60}
51 61
52/** 62/**
53 * Gets the location of the framebuffers 63 * Gets the location of the framebuffers
54 * @return Location of framebuffers as FramebufferLocation enum 64 * @return Location of framebuffers as FramebufferLocation enum
55 */ 65 */
56const FramebufferLocation GetFramebufferLocation() { 66FramebufferLocation GetFramebufferLocation(u32 address) {
57 if ((g_regs.framebuffer_top_right_1 & ~Memory::VRAM_MASK) == Memory::VRAM_PADDR) { 67 if ((address & ~Memory::VRAM_MASK) == Memory::VRAM_PADDR) {
58 return FRAMEBUFFER_LOCATION_VRAM; 68 return FRAMEBUFFER_LOCATION_VRAM;
59 } else if ((g_regs.framebuffer_top_right_1 & ~Memory::FCRAM_MASK) == Memory::FCRAM_PADDR) { 69 } else if ((address & ~Memory::FCRAM_MASK) == Memory::FCRAM_PADDR) {
60 return FRAMEBUFFER_LOCATION_FCRAM; 70 return FRAMEBUFFER_LOCATION_FCRAM;
61 } else { 71 } else {
62 ERROR_LOG(GPU, "unknown framebuffer location!"); 72 ERROR_LOG(GPU, "unknown framebuffer location!");
@@ -64,91 +74,161 @@ const FramebufferLocation GetFramebufferLocation() {
64 return FRAMEBUFFER_LOCATION_UNKNOWN; 74 return FRAMEBUFFER_LOCATION_UNKNOWN;
65} 75}
66 76
77u32 GetFramebufferAddr(const u32 address) {
78 switch (GetFramebufferLocation(address)) {
79 case FRAMEBUFFER_LOCATION_FCRAM:
80 return Memory::VirtualAddressFromPhysical_FCRAM(address);
81 case FRAMEBUFFER_LOCATION_VRAM:
82 return Memory::VirtualAddressFromPhysical_VRAM(address);
83 default:
84 ERROR_LOG(GPU, "unknown framebuffer location");
85 }
86 return 0;
87}
88
67/** 89/**
68 * Gets a read-only pointer to a framebuffer in memory 90 * Gets a read-only pointer to a framebuffer in memory
69 * @param address Physical address of framebuffer 91 * @param address Physical address of framebuffer
70 * @return Returns const pointer to raw framebuffer 92 * @return Returns const pointer to raw framebuffer
71 */ 93 */
72const u8* GetFramebufferPointer(const u32 address) { 94const u8* GetFramebufferPointer(const u32 address) {
73 switch (GetFramebufferLocation()) { 95 u32 addr = GetFramebufferAddr(address);
74 case FRAMEBUFFER_LOCATION_FCRAM: 96 return (addr != 0) ? Memory::GetPointer(addr) : nullptr;
75 return (const u8*)Memory::GetPointer(Memory::VirtualAddressFromPhysical_FCRAM(address));
76 case FRAMEBUFFER_LOCATION_VRAM:
77 return (const u8*)Memory::GetPointer(Memory::VirtualAddressFromPhysical_VRAM(address));
78 default:
79 ERROR_LOG(GPU, "unknown framebuffer location");
80 }
81 return NULL;
82} 97}
83 98
84template <typename T> 99template <typename T>
85inline void Read(T &var, const u32 addr) { 100inline void Read(T &var, const u32 raw_addr) {
86 switch (addr) { 101 u32 addr = raw_addr - 0x1EF00000;
87 case Registers::FramebufferTopLeft1: 102 int index = addr / 4;
88 var = g_regs.framebuffer_top_left_1;
89 break;
90 103
91 case Registers::FramebufferTopLeft2: 104 // Reads other than u32 are untested, so I'd rather have them abort than silently fail
92 var = g_regs.framebuffer_top_left_2; 105 if (index >= Regs::NumIds || !std::is_same<T,u32>::value)
93 break; 106 {
107 ERROR_LOG(GPU, "unknown Read%d @ 0x%08X", sizeof(var) * 8, addr);
108 return;
109 }
94 110
95 case Registers::FramebufferTopRight1: 111 var = g_regs[static_cast<Regs::Id>(addr / 4)];
96 var = g_regs.framebuffer_top_right_1; 112}
97 break;
98 113
99 case Registers::FramebufferTopRight2: 114template <typename T>
100 var = g_regs.framebuffer_top_right_2; 115inline void Write(u32 addr, const T data) {
101 break; 116 addr -= 0x1EF00000;
117 int index = addr / 4;
102 118
103 case Registers::FramebufferSubLeft1: 119 // Writes other than u32 are untested, so I'd rather have them abort than silently fail
104 var = g_regs.framebuffer_sub_left_1; 120 if (index >= Regs::NumIds || !std::is_same<T,u32>::value)
105 break; 121 {
122 ERROR_LOG(GPU, "unknown Write%d 0x%08X @ 0x%08X", sizeof(data) * 8, data, addr);
123 return;
124 }
106 125
107 case Registers::FramebufferSubRight1: 126 g_regs[static_cast<Regs::Id>(index)] = data;
108 var = g_regs.framebuffer_sub_right_1;
109 break;
110 127
111 case Registers::CommandListSize: 128 switch (static_cast<Regs::Id>(index)) {
112 var = g_regs.command_list_size;
113 break;
114 129
115 case Registers::CommandListAddress: 130 // Memory fills are triggered once the fill value is written.
116 var = g_regs.command_list_address; 131 // NOTE: This is not verified.
117 break; 132 case Regs::MemoryFill + 3:
133 case Regs::MemoryFill + 7:
134 {
135 const auto& config = g_regs.Get<Regs::MemoryFill>(static_cast<Regs::Id>(index - 3));
118 136
119 case Registers::ProcessCommandList: 137 // TODO: Not sure if this check should be done at GSP level instead
120 var = g_regs.command_processing_enabled; 138 if (config.address_start) {
121 break; 139 // TODO: Not sure if this algorithm is correct, particularly because it doesn't use the size member at all
140 u32* start = (u32*)Memory::GetPointer(config.GetStartAddress());
141 u32* end = (u32*)Memory::GetPointer(config.GetEndAddress());
142 for (u32* ptr = start; ptr < end; ++ptr)
143 *ptr = bswap32(config.value); // TODO: This is just a workaround to missing framebuffer format emulation
122 144
123 default: 145 DEBUG_LOG(GPU, "MemoryFill from 0x%08x to 0x%08x", config.GetStartAddress(), config.GetEndAddress());
124 ERROR_LOG(GPU, "unknown Read%d @ 0x%08X", sizeof(var) * 8, addr); 146 }
125 break; 147 break;
126 } 148 }
127}
128
129template <typename T>
130inline void Write(u32 addr, const T data) {
131 switch (static_cast<Registers::Id>(addr)) {
132 case Registers::CommandListSize:
133 g_regs.command_list_size = data;
134 break;
135 149
136 case Registers::CommandListAddress: 150 case Regs::DisplayTransfer + 6:
137 g_regs.command_list_address = data; 151 {
152 const auto& config = g_regs.Get<Regs::DisplayTransfer>();
153 if (config.trigger & 1) {
154 u8* source_pointer = Memory::GetPointer(config.GetPhysicalInputAddress());
155 u8* dest_pointer = Memory::GetPointer(config.GetPhysicalOutputAddress());
156
157 for (int y = 0; y < config.output_height; ++y) {
158 // TODO: Why does the register seem to hold twice the framebuffer width?
159 for (int x = 0; x < config.output_width / 2; ++x) {
160 struct {
161 int r, g, b, a;
162 } source_color = { 0, 0, 0, 0 };
163
164 switch (config.input_format) {
165 case Regs::FramebufferFormat::RGBA8:
166 {
167 // TODO: Most likely got the component order messed up.
168 u8* srcptr = source_pointer + x * 4 + y * config.input_width * 4 / 2;
169 source_color.r = srcptr[0]; // blue
170 source_color.g = srcptr[1]; // green
171 source_color.b = srcptr[2]; // red
172 source_color.a = srcptr[3]; // alpha
173 break;
174 }
175
176 default:
177 ERROR_LOG(GPU, "Unknown source framebuffer format %x", config.input_format.Value());
178 break;
179 }
180
181 switch (config.output_format) {
182 /*case Regs::FramebufferFormat::RGBA8:
183 {
184 // TODO: Untested
185 u8* dstptr = (u32*)(dest_pointer + x * 4 + y * config.output_width * 4);
186 dstptr[0] = source_color.r;
187 dstptr[1] = source_color.g;
188 dstptr[2] = source_color.b;
189 dstptr[3] = source_color.a;
190 break;
191 }*/
192
193 case Regs::FramebufferFormat::RGB8:
194 {
195 // TODO: Most likely got the component order messed up.
196 u8* dstptr = dest_pointer + x * 3 + y * config.output_width * 3 / 2;
197 dstptr[0] = source_color.r; // blue
198 dstptr[1] = source_color.g; // green
199 dstptr[2] = source_color.b; // red
200 break;
201 }
202
203 default:
204 ERROR_LOG(GPU, "Unknown destination framebuffer format %x", config.output_format.Value());
205 break;
206 }
207 }
208 }
209
210 DEBUG_LOG(GPU, "DisplayTriggerTransfer: 0x%08x bytes from 0x%08x(%dx%d)-> 0x%08x(%dx%d), dst format %x",
211 config.output_height * config.output_width * 4,
212 config.GetPhysicalInputAddress(), (int)config.input_width, (int)config.input_height,
213 config.GetPhysicalOutputAddress(), (int)config.output_width, (int)config.output_height,
214 config.output_format.Value());
215 }
138 break; 216 break;
217 }
139 218
140 case Registers::ProcessCommandList: 219 case Regs::CommandProcessor + 4:
141 g_regs.command_processing_enabled = data; 220 {
142 if (g_regs.command_processing_enabled & 1) 221 const auto& config = g_regs.Get<Regs::CommandProcessor>();
222 if (config.trigger & 1)
143 { 223 {
144 // u32* buffer = (u32*)Memory::GetPointer(g_regs.command_list_address << 3); 224 // u32* buffer = (u32*)Memory::GetPointer(config.address << 3);
145 ERROR_LOG(GPU, "Beginning %x bytes of commands from address %x", g_regs.command_list_size, g_regs.command_list_address << 3); 225 ERROR_LOG(GPU, "Beginning 0x%08x bytes of commands from address 0x%08x", config.size, config.address << 3);
146 // TODO: Process command list! 226 // TODO: Process command list!
147 } 227 }
148 break; 228 break;
229 }
149 230
150 default: 231 default:
151 ERROR_LOG(GPU, "unknown Write%d 0x%08X @ 0x%08X", sizeof(data) * 8, data, addr);
152 break; 232 break;
153 } 233 }
154} 234}
@@ -180,7 +260,24 @@ void Update() {
180/// Initialize hardware 260/// Initialize hardware
181void Init() { 261void Init() {
182 g_last_ticks = Core::g_app_core->GetTicks(); 262 g_last_ticks = Core::g_app_core->GetTicks();
183 SetFramebufferLocation(FRAMEBUFFER_LOCATION_FCRAM); 263// SetFramebufferLocation(FRAMEBUFFER_LOCATION_FCRAM);
264 SetFramebufferLocation(FRAMEBUFFER_LOCATION_VRAM);
265
266 auto& framebuffer_top = g_regs.Get<Regs::FramebufferTop>();
267 auto& framebuffer_sub = g_regs.Get<Regs::FramebufferBottom>();
268 // TODO: Width should be 240 instead?
269 framebuffer_top.width = 480;
270 framebuffer_top.height = 400;
271 framebuffer_top.stride = 480*3;
272 framebuffer_top.color_format = Regs::FramebufferFormat::RGB8;
273 framebuffer_top.active_fb = 0;
274
275 framebuffer_sub.width = 480;
276 framebuffer_sub.height = 400;
277 framebuffer_sub.stride = 480*3;
278 framebuffer_sub.color_format = Regs::FramebufferFormat::RGB8;
279 framebuffer_sub.active_fb = 0;
280
184 NOTICE_LOG(GPU, "initialized OK"); 281 NOTICE_LOG(GPU, "initialized OK");
185} 282}
186 283
diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h
index 3314ba989..42f18a0e7 100644
--- a/src/core/hw/gpu.h
+++ b/src/core/hw/gpu.h
@@ -5,43 +5,168 @@
5#pragma once 5#pragma once
6 6
7#include "common/common_types.h" 7#include "common/common_types.h"
8#include "common/bit_field.h"
9#include "common/register_set.h"
8 10
9namespace GPU { 11namespace GPU {
10 12
11static const u32 kFrameCycles = 268123480 / 60; ///< 268MHz / 60 frames per second 13static const u32 kFrameCycles = 268123480 / 60; ///< 268MHz / 60 frames per second
12static const u32 kFrameTicks = kFrameCycles / 3; ///< Approximate number of instructions/frame 14static const u32 kFrameTicks = kFrameCycles / 3; ///< Approximate number of instructions/frame
13 15
14struct Registers { 16// MMIO region 0x1EFxxxxx
17struct Regs {
15 enum Id : u32 { 18 enum Id : u32 {
16 FramebufferTopLeft1 = 0x1EF00468, // Main LCD, first framebuffer for 3D left 19 MemoryFill = 0x00004, // + 5,6,7; second block at 8-11
17 FramebufferTopLeft2 = 0x1EF0046C, // Main LCD, second framebuffer for 3D left 20
18 FramebufferTopRight1 = 0x1EF00494, // Main LCD, first framebuffer for 3D right 21 FramebufferTop = 0x00117, // + 11a,11b,11c,11d(?),11e...126
19 FramebufferTopRight2 = 0x1EF00498, // Main LCD, second framebuffer for 3D right 22 FramebufferBottom = 0x00157, // + 15a,15b,15c,15d(?),15e...166
20 FramebufferSubLeft1 = 0x1EF00568, // Sub LCD, first framebuffer 23
21 FramebufferSubLeft2 = 0x1EF0056C, // Sub LCD, second framebuffer 24 DisplayTransfer = 0x00300, // + 301,302,303,304,305,306
22 FramebufferSubRight1 = 0x1EF00594, // Sub LCD, unused first framebuffer 25
23 FramebufferSubRight2 = 0x1EF00598, // Sub LCD, unused second framebuffer 26 CommandProcessor = 0x00638, // + 63a,63c
24 27
25 CommandListSize = 0x1EF018E0, 28 NumIds = 0x01000
26 CommandListAddress = 0x1EF018E8, 29 };
27 ProcessCommandList = 0x1EF018F0, 30
31 template<Id id>
32 struct Struct;
33
34 enum class FramebufferFormat : u32 {
35 RGBA8 = 0,
36 RGB8 = 1,
37 RGB565 = 2,
38 RGB5A1 = 3,
39 RGBA4 = 4,
40 };
41};
42
43template<>
44struct Regs::Struct<Regs::MemoryFill> {
45 u32 address_start;
46 u32 address_end; // ?
47 u32 size;
48 u32 value; // ?
49
50 inline u32 GetStartAddress() const {
51 return address_start * 8;
52 }
53
54 inline u32 GetEndAddress() const {
55 return address_end * 8;
56 }
57};
58static_assert(sizeof(Regs::Struct<Regs::MemoryFill>) == 0x10, "Structure size and register block length don't match");
59
60template<>
61struct Regs::Struct<Regs::FramebufferTop> {
62 using Format = Regs::FramebufferFormat;
63
64 union {
65 u32 size;
66
67 BitField< 0, 16, u32> width;
68 BitField<16, 16, u32> height;
69 };
70
71 u32 pad0[2];
72
73 u32 address_left1;
74 u32 address_left2;
75
76 union {
77 u32 format;
78
79 BitField< 0, 3, Format> color_format;
80 };
81
82 u32 pad1;
83
84 union {
85 u32 active_fb;
86
87 // 0: Use parameters ending with "1"
88 // 1: Use parameters ending with "2"
89 BitField<0, 1, u32> second_fb_active;
90 };
91
92 u32 pad2[5];
93
94 // Distance between two pixel rows, in bytes
95 u32 stride;
96
97 u32 address_right1;
98 u32 address_right2;
99};
100
101template<>
102struct Regs::Struct<Regs::FramebufferBottom> : public Regs::Struct<Regs::FramebufferTop> {
103};
104static_assert(sizeof(Regs::Struct<Regs::FramebufferTop>) == 0x40, "Structure size and register block length don't match");
105
106template<>
107struct Regs::Struct<Regs::DisplayTransfer> {
108 using Format = Regs::FramebufferFormat;
109
110 u32 input_address;
111 u32 output_address;
112
113 inline u32 GetPhysicalInputAddress() const {
114 return input_address * 8;
115 }
116
117 inline u32 GetPhysicalOutputAddress() const {
118 return output_address * 8;
119 }
120
121 union {
122 u32 output_size;
123
124 BitField< 0, 16, u32> output_width;
125 BitField<16, 16, u32> output_height;
126 };
127
128 union {
129 u32 input_size;
130
131 BitField< 0, 16, u32> input_width;
132 BitField<16, 16, u32> input_height;
28 }; 133 };
29 134
30 u32 framebuffer_top_left_1; 135 union {
31 u32 framebuffer_top_left_2; 136 u32 flags;
32 u32 framebuffer_top_right_1; 137
33 u32 framebuffer_top_right_2; 138 BitField< 0, 1, u32> flip_data; // flips input data horizontally (TODO) if true
34 u32 framebuffer_sub_left_1; 139 BitField< 8, 3, Format> input_format;
35 u32 framebuffer_sub_left_2; 140 BitField<12, 3, Format> output_format;
36 u32 framebuffer_sub_right_1; 141 BitField<16, 1, u32> output_tiled; // stores output in a tiled format
37 u32 framebuffer_sub_right_2; 142 };
38 143
39 u32 command_list_size; 144 u32 unknown;
40 u32 command_list_address; 145
41 u32 command_processing_enabled; 146 // it seems that writing to this field triggers the display transfer
147 u32 trigger;
42}; 148};
149static_assert(sizeof(Regs::Struct<Regs::DisplayTransfer>) == 0x1C, "Structure size and register block length don't match");
150
151template<>
152struct Regs::Struct<Regs::CommandProcessor> {
153 // command list size
154 u32 size;
155
156 u32 pad0;
157
158 // command list address
159 u32 address;
43 160
44extern Registers g_regs; 161 u32 pad1;
162
163 // it seems that writing to this field triggers command list processing
164 u32 trigger;
165};
166static_assert(sizeof(Regs::Struct<Regs::CommandProcessor>) == 0x14, "Structure size and register block length don't match");
167
168
169extern RegisterSet<u32, Regs> g_regs;
45 170
46enum { 171enum {
47 TOP_ASPECT_X = 0x5, 172 TOP_ASPECT_X = 0x5,
@@ -51,23 +176,35 @@ enum {
51 TOP_WIDTH = 400, 176 TOP_WIDTH = 400,
52 BOTTOM_WIDTH = 320, 177 BOTTOM_WIDTH = 320,
53 178
54 // Physical addresses in FCRAM used by ARM9 applications - these are correct for real hardware 179 // Physical addresses in FCRAM (chosen arbitrarily)
55 PADDR_FRAMEBUFFER_SEL = 0x20184E59, 180 PADDR_TOP_LEFT_FRAME1 = 0x201D4C00,
56 PADDR_TOP_LEFT_FRAME1 = 0x20184E60, 181 PADDR_TOP_LEFT_FRAME2 = 0x202D4C00,
182 PADDR_TOP_RIGHT_FRAME1 = 0x203D4C00,
183 PADDR_TOP_RIGHT_FRAME2 = 0x204D4C00,
184 PADDR_SUB_FRAME1 = 0x205D4C00,
185 PADDR_SUB_FRAME2 = 0x206D4C00,
186 // Physical addresses in FCRAM used by ARM9 applications
187/* PADDR_TOP_LEFT_FRAME1 = 0x20184E60,
57 PADDR_TOP_LEFT_FRAME2 = 0x201CB370, 188 PADDR_TOP_LEFT_FRAME2 = 0x201CB370,
58 PADDR_TOP_RIGHT_FRAME1 = 0x20282160, 189 PADDR_TOP_RIGHT_FRAME1 = 0x20282160,
59 PADDR_TOP_RIGHT_FRAME2 = 0x202C8670, 190 PADDR_TOP_RIGHT_FRAME2 = 0x202C8670,
60 PADDR_SUB_FRAME1 = 0x202118E0, 191 PADDR_SUB_FRAME1 = 0x202118E0,
61 PADDR_SUB_FRAME2 = 0x20249CF0, 192 PADDR_SUB_FRAME2 = 0x20249CF0,*/
62 193
63 // Physical addresses in VRAM - I'm not sure how these are actually allocated (so not real) 194 // Physical addresses in VRAM
64 PADDR_VRAM_FRAMEBUFFER_SEL = 0x18184E59, 195 // TODO: These should just be deduced from the ones above
65 PADDR_VRAM_TOP_LEFT_FRAME1 = 0x18184E60, 196 PADDR_VRAM_TOP_LEFT_FRAME1 = 0x181D4C00,
66 PADDR_VRAM_TOP_LEFT_FRAME2 = 0x181CB370, 197 PADDR_VRAM_TOP_LEFT_FRAME2 = 0x182D4C00,
198 PADDR_VRAM_TOP_RIGHT_FRAME1 = 0x183D4C00,
199 PADDR_VRAM_TOP_RIGHT_FRAME2 = 0x184D4C00,
200 PADDR_VRAM_SUB_FRAME1 = 0x185D4C00,
201 PADDR_VRAM_SUB_FRAME2 = 0x186D4C00,
202 // Physical addresses in VRAM used by ARM9 applications
203/* PADDR_VRAM_TOP_LEFT_FRAME2 = 0x181CB370,
67 PADDR_VRAM_TOP_RIGHT_FRAME1 = 0x18282160, 204 PADDR_VRAM_TOP_RIGHT_FRAME1 = 0x18282160,
68 PADDR_VRAM_TOP_RIGHT_FRAME2 = 0x182C8670, 205 PADDR_VRAM_TOP_RIGHT_FRAME2 = 0x182C8670,
69 PADDR_VRAM_SUB_FRAME1 = 0x182118E0, 206 PADDR_VRAM_SUB_FRAME1 = 0x182118E0,
70 PADDR_VRAM_SUB_FRAME2 = 0x18249CF0, 207 PADDR_VRAM_SUB_FRAME2 = 0x18249CF0,*/
71}; 208};
72 209
73/// Framebuffer location 210/// Framebuffer location
@@ -79,7 +216,7 @@ enum FramebufferLocation {
79 216
80/** 217/**
81 * Sets whether the framebuffers are in the GSP heap (FCRAM) or VRAM 218 * Sets whether the framebuffers are in the GSP heap (FCRAM) or VRAM
82 * @param 219 * @param
83 */ 220 */
84void SetFramebufferLocation(const FramebufferLocation mode); 221void SetFramebufferLocation(const FramebufferLocation mode);
85 222
@@ -90,16 +227,18 @@ void SetFramebufferLocation(const FramebufferLocation mode);
90 */ 227 */
91const u8* GetFramebufferPointer(const u32 address); 228const u8* GetFramebufferPointer(const u32 address);
92 229
230u32 GetFramebufferAddr(const u32 address);
231
93/** 232/**
94 * Gets the location of the framebuffers 233 * Gets the location of the framebuffers
95 */ 234 */
96const FramebufferLocation GetFramebufferLocation(); 235FramebufferLocation GetFramebufferLocation(u32 address);
97 236
98template <typename T> 237template <typename T>
99inline void Read(T &var, const u32 addr); 238void Read(T &var, const u32 addr);
100 239
101template <typename T> 240template <typename T>
102inline void Write(u32 addr, const T data); 241void Write(u32 addr, const T data);
103 242
104/// Update hardware 243/// Update hardware
105void Update(); 244void Update();
diff --git a/src/core/hw/hw.h b/src/core/hw/hw.h
index 92e9304ca..1055ed94f 100644
--- a/src/core/hw/hw.h
+++ b/src/core/hw/hw.h
@@ -9,10 +9,10 @@
9namespace HW { 9namespace HW {
10 10
11template <typename T> 11template <typename T>
12inline void Read(T &var, const u32 addr); 12void Read(T &var, const u32 addr);
13 13
14template <typename T> 14template <typename T>
15inline void Write(u32 addr, const T data); 15void Write(u32 addr, const T data);
16 16
17/// Update hardware 17/// Update hardware
18void Update(); 18void Update();
diff --git a/src/video_core/gpu_debugger.h b/src/video_core/gpu_debugger.h
index 5d909beba..d92ceaa72 100644
--- a/src/video_core/gpu_debugger.h
+++ b/src/video_core/gpu_debugger.h
@@ -50,7 +50,7 @@ public:
50 virtual void GXCommandProcessed(int total_command_count) 50 virtual void GXCommandProcessed(int total_command_count)
51 { 51 {
52 const GSP_GPU::GXCommand& cmd = observed->ReadGXCommandHistory(total_command_count-1); 52 const GSP_GPU::GXCommand& cmd = observed->ReadGXCommandHistory(total_command_count-1);
53 ERROR_LOG(GSP, "Received command: id=%x", cmd.id); 53 ERROR_LOG(GSP, "Received command: id=%x", (int)cmd.id.Value());
54 } 54 }
55 55
56 /** 56 /**
@@ -78,11 +78,13 @@ public:
78 78
79 void GXCommandProcessed(u8* command_data) 79 void GXCommandProcessed(u8* command_data)
80 { 80 {
81 if (observers.empty())
82 return;
83
81 gx_command_history.push_back(GSP_GPU::GXCommand()); 84 gx_command_history.push_back(GSP_GPU::GXCommand());
82 GSP_GPU::GXCommand& cmd = gx_command_history[gx_command_history.size()-1]; 85 GSP_GPU::GXCommand& cmd = gx_command_history[gx_command_history.size()-1];
83 86
84 const int cmd_length = sizeof(GSP_GPU::GXCommand); 87 memcpy(&cmd, command_data, sizeof(GSP_GPU::GXCommand));
85 memcpy(cmd.data, command_data, cmd_length);
86 88
87 ForEachObserver([this](DebuggerObserver* observer) { 89 ForEachObserver([this](DebuggerObserver* observer) {
88 observer->GXCommandProcessed(this->gx_command_history.size()); 90 observer->GXCommandProcessed(this->gx_command_history.size());
@@ -91,6 +93,9 @@ public:
91 93
92 void CommandListCalled(u32 address, u32* command_list, u32 size_in_words) 94 void CommandListCalled(u32 address, u32* command_list, u32 size_in_words)
93 { 95 {
96 if (observers.empty())
97 return;
98
94 PicaCommandList cmdlist; 99 PicaCommandList cmdlist;
95 for (u32* parse_pointer = command_list; parse_pointer < command_list + size_in_words;) 100 for (u32* parse_pointer = command_list; parse_pointer < command_list + size_in_words;)
96 { 101 {
diff --git a/src/video_core/renderer_opengl/renderer_opengl.cpp b/src/video_core/renderer_opengl/renderer_opengl.cpp
index 70af47c59..d0a8ec1da 100644
--- a/src/video_core/renderer_opengl/renderer_opengl.cpp
+++ b/src/video_core/renderer_opengl/renderer_opengl.cpp
@@ -12,8 +12,8 @@
12 12
13/// RendererOpenGL constructor 13/// RendererOpenGL constructor
14RendererOpenGL::RendererOpenGL() { 14RendererOpenGL::RendererOpenGL() {
15 memset(m_fbo, 0, sizeof(m_fbo)); 15 memset(m_fbo, 0, sizeof(m_fbo));
16 memset(m_fbo_rbo, 0, sizeof(m_fbo_rbo)); 16 memset(m_fbo_rbo, 0, sizeof(m_fbo_rbo));
17 memset(m_fbo_depth_buffers, 0, sizeof(m_fbo_depth_buffers)); 17 memset(m_fbo_depth_buffers, 0, sizeof(m_fbo_depth_buffers));
18 18
19 m_resolution_width = max(VideoCore::kScreenTopWidth, VideoCore::kScreenBottomWidth); 19 m_resolution_width = max(VideoCore::kScreenTopWidth, VideoCore::kScreenBottomWidth);
@@ -35,7 +35,7 @@ void RendererOpenGL::SwapBuffers() {
35 m_render_window->MakeCurrent(); 35 m_render_window->MakeCurrent();
36 36
37 // EFB->XFB copy 37 // EFB->XFB copy
38 // TODO(bunnei): This is a hack and does not belong here. The copy should be triggered by some 38 // TODO(bunnei): This is a hack and does not belong here. The copy should be triggered by some
39 // register write We're also treating both framebuffers as a single one in OpenGL. 39 // register write We're also treating both framebuffers as a single one in OpenGL.
40 common::Rect framebuffer_size(0, 0, m_resolution_width, m_resolution_height); 40 common::Rect framebuffer_size(0, 0, m_resolution_width, m_resolution_height);
41 RenderXFB(framebuffer_size, framebuffer_size); 41 RenderXFB(framebuffer_size, framebuffer_size);
@@ -61,24 +61,40 @@ void RendererOpenGL::FlipFramebuffer(const u8* in, u8* out) {
61 int in_coord = 0; 61 int in_coord = 0;
62 for (int x = 0; x < VideoCore::kScreenTopWidth; x++) { 62 for (int x = 0; x < VideoCore::kScreenTopWidth; x++) {
63 for (int y = VideoCore::kScreenTopHeight-1; y >= 0; y--) { 63 for (int y = VideoCore::kScreenTopHeight-1; y >= 0; y--) {
64 // TODO: Properly support other framebuffer formats
64 int out_coord = (x + y * VideoCore::kScreenTopWidth) * 3; 65 int out_coord = (x + y * VideoCore::kScreenTopWidth) * 3;
65 out[out_coord] = in[in_coord]; 66 out[out_coord] = in[in_coord]; // blue?
66 out[out_coord + 1] = in[in_coord + 1]; 67 out[out_coord + 1] = in[in_coord + 1]; // green?
67 out[out_coord + 2] = in[in_coord + 2]; 68 out[out_coord + 2] = in[in_coord + 2]; // red?
68 in_coord+=3; 69 in_coord+=3;
69 } 70 }
70 } 71 }
71} 72}
72 73
73/** 74/**
74 * Renders external framebuffer (XFB) 75 * Renders external framebuffer (XFB)
75 * @param src_rect Source rectangle in XFB to copy 76 * @param src_rect Source rectangle in XFB to copy
76 * @param dst_rect Destination rectangle in output framebuffer to copy to 77 * @param dst_rect Destination rectangle in output framebuffer to copy to
77 */ 78 */
78void RendererOpenGL::RenderXFB(const common::Rect& src_rect, const common::Rect& dst_rect) { 79void RendererOpenGL::RenderXFB(const common::Rect& src_rect, const common::Rect& dst_rect) {
79 80
80 FlipFramebuffer(GPU::GetFramebufferPointer(GPU::g_regs.framebuffer_top_left_1), m_xfb_top_flipped); 81 const auto& framebuffer_top = GPU::g_regs.Get<GPU::Regs::FramebufferTop>();
81 FlipFramebuffer(GPU::GetFramebufferPointer(GPU::g_regs.framebuffer_sub_left_1), m_xfb_bottom_flipped); 82 const auto& framebuffer_sub = GPU::g_regs.Get<GPU::Regs::FramebufferBottom>();
83 const u32 active_fb_top = (framebuffer_top.active_fb == 1)
84 ? framebuffer_top.address_left2
85 : framebuffer_top.address_left1;
86 const u32 active_fb_sub = (framebuffer_sub.active_fb == 1)
87 ? framebuffer_sub.address_left2
88 : framebuffer_sub.address_left1;
89
90 DEBUG_LOG(GPU, "RenderXFB: 0x%08x bytes from 0x%08x(%dx%d), fmt %x",
91 framebuffer_top.stride * framebuffer_top.height,
92 GPU::GetFramebufferAddr(active_fb_top), (int)framebuffer_top.width,
93 (int)framebuffer_top.height, (int)framebuffer_top.format);
94
95 // TODO: This should consider the GPU registers for framebuffer width, height and stride.
96 FlipFramebuffer(GPU::GetFramebufferPointer(active_fb_top), m_xfb_top_flipped);
97 FlipFramebuffer(GPU::GetFramebufferPointer(active_fb_sub), m_xfb_bottom_flipped);
82 98
83 // Blit the top framebuffer 99 // Blit the top framebuffer
84 // ------------------------ 100 // ------------------------
@@ -98,7 +114,7 @@ void RendererOpenGL::RenderXFB(const common::Rect& src_rect, const common::Rect&
98 glReadBuffer(GL_COLOR_ATTACHMENT0); 114 glReadBuffer(GL_COLOR_ATTACHMENT0);
99 115
100 // Blit 116 // Blit
101 glBlitFramebuffer(src_rect.x0_, src_rect.y0_, src_rect.x1_, src_rect.y1_, 117 glBlitFramebuffer(src_rect.x0_, src_rect.y0_, src_rect.x1_, src_rect.y1_,
102 dst_rect.x0_, dst_rect.y1_, dst_rect.x1_, dst_rect.y0_, 118 dst_rect.x0_, dst_rect.y1_, dst_rect.x1_, dst_rect.y0_,
103 GL_COLOR_BUFFER_BIT, GL_LINEAR); 119 GL_COLOR_BUFFER_BIT, GL_LINEAR);
104 120
@@ -110,7 +126,7 @@ void RendererOpenGL::RenderXFB(const common::Rect& src_rect, const common::Rect&
110 // Update textures with contents of XFB in RAM - bottom 126 // Update textures with contents of XFB in RAM - bottom
111 glBindTexture(GL_TEXTURE_2D, m_xfb_texture_bottom); 127 glBindTexture(GL_TEXTURE_2D, m_xfb_texture_bottom);
112 glTexSubImage2D(GL_TEXTURE_2D, 0, 0, 0, VideoCore::kScreenTopWidth, VideoCore::kScreenTopHeight, 128 glTexSubImage2D(GL_TEXTURE_2D, 0, 0, 0, VideoCore::kScreenTopWidth, VideoCore::kScreenTopHeight,
113 GL_RGB, GL_UNSIGNED_BYTE, m_xfb_bottom_flipped); 129 GL_BGR, GL_UNSIGNED_BYTE, m_xfb_bottom_flipped);
114 glBindTexture(GL_TEXTURE_2D, 0); 130 glBindTexture(GL_TEXTURE_2D, 0);
115 131
116 // Render target is destination framebuffer 132 // Render target is destination framebuffer
@@ -124,7 +140,7 @@ void RendererOpenGL::RenderXFB(const common::Rect& src_rect, const common::Rect&
124 140
125 // Blit 141 // Blit
126 int offset = (VideoCore::kScreenTopWidth - VideoCore::kScreenBottomWidth) / 2; 142 int offset = (VideoCore::kScreenTopWidth - VideoCore::kScreenBottomWidth) / 2;
127 glBlitFramebuffer(0,0, VideoCore::kScreenBottomWidth, VideoCore::kScreenBottomHeight, 143 glBlitFramebuffer(0,0, VideoCore::kScreenBottomWidth, VideoCore::kScreenBottomHeight,
128 offset, VideoCore::kScreenBottomHeight, VideoCore::kScreenBottomWidth + offset, 0, 144 offset, VideoCore::kScreenBottomHeight, VideoCore::kScreenBottomWidth + offset, 0,
129 GL_COLOR_BUFFER_BIT, GL_LINEAR); 145 GL_COLOR_BUFFER_BIT, GL_LINEAR);
130 146
@@ -133,7 +149,7 @@ void RendererOpenGL::RenderXFB(const common::Rect& src_rect, const common::Rect&
133 149
134/// Initialize the FBO 150/// Initialize the FBO
135void RendererOpenGL::InitFramebuffer() { 151void RendererOpenGL::InitFramebuffer() {
136 // TODO(bunnei): This should probably be implemented with the top screen and bottom screen as 152 // TODO(bunnei): This should probably be implemented with the top screen and bottom screen as
137 // separate framebuffers 153 // separate framebuffers
138 154
139 // Init the FBOs 155 // Init the FBOs
@@ -146,12 +162,12 @@ void RendererOpenGL::InitFramebuffer() {
146 for (int i = 0; i < kMaxFramebuffers; i++) { 162 for (int i = 0; i < kMaxFramebuffers; i++) {
147 // Generate color buffer storage 163 // Generate color buffer storage
148 glBindRenderbuffer(GL_RENDERBUFFER, m_fbo_rbo[i]); 164 glBindRenderbuffer(GL_RENDERBUFFER, m_fbo_rbo[i]);
149 glRenderbufferStorage(GL_RENDERBUFFER, GL_RGBA8, VideoCore::kScreenTopWidth, 165 glRenderbufferStorage(GL_RENDERBUFFER, GL_RGBA8, VideoCore::kScreenTopWidth,
150 VideoCore::kScreenTopHeight + VideoCore::kScreenBottomHeight); 166 VideoCore::kScreenTopHeight + VideoCore::kScreenBottomHeight);
151 167
152 // Generate depth buffer storage 168 // Generate depth buffer storage
153 glBindRenderbuffer(GL_RENDERBUFFER, m_fbo_depth_buffers[i]); 169 glBindRenderbuffer(GL_RENDERBUFFER, m_fbo_depth_buffers[i]);
154 glRenderbufferStorage(GL_RENDERBUFFER, GL_DEPTH_COMPONENT32, VideoCore::kScreenTopWidth, 170 glRenderbufferStorage(GL_RENDERBUFFER, GL_DEPTH_COMPONENT32, VideoCore::kScreenTopWidth,
155 VideoCore::kScreenTopHeight + VideoCore::kScreenBottomHeight); 171 VideoCore::kScreenTopHeight + VideoCore::kScreenBottomHeight);
156 172
157 // Attach the buffers 173 // Attach the buffers
@@ -167,7 +183,7 @@ void RendererOpenGL::InitFramebuffer() {
167 } else { 183 } else {
168 ERROR_LOG(RENDER, "couldn't create OpenGL frame buffer"); 184 ERROR_LOG(RENDER, "couldn't create OpenGL frame buffer");
169 exit(1); 185 exit(1);
170 } 186 }
171 } 187 }
172 glBindFramebuffer(GL_FRAMEBUFFER, 0); // Unbind our frame buffer(s) 188 glBindFramebuffer(GL_FRAMEBUFFER, 0); // Unbind our frame buffer(s)
173 189
@@ -175,8 +191,8 @@ void RendererOpenGL::InitFramebuffer() {
175 // ------------------------------- 191 // -------------------------------
176 192
177 // Create XFB textures 193 // Create XFB textures
178 glGenTextures(1, &m_xfb_texture_top); 194 glGenTextures(1, &m_xfb_texture_top);
179 glGenTextures(1, &m_xfb_texture_bottom); 195 glGenTextures(1, &m_xfb_texture_bottom);
180 196
181 // Alocate video memorry for XFB textures 197 // Alocate video memorry for XFB textures
182 glBindTexture(GL_TEXTURE_2D, m_xfb_texture_top); 198 glBindTexture(GL_TEXTURE_2D, m_xfb_texture_top);
@@ -192,13 +208,13 @@ void RendererOpenGL::InitFramebuffer() {
192 // Create the FBO and attach color/depth textures 208 // Create the FBO and attach color/depth textures
193 glGenFramebuffers(1, &m_xfb_top); // Generate framebuffer 209 glGenFramebuffers(1, &m_xfb_top); // Generate framebuffer
194 glBindFramebuffer(GL_DRAW_FRAMEBUFFER, m_xfb_top); 210 glBindFramebuffer(GL_DRAW_FRAMEBUFFER, m_xfb_top);
195 glFramebufferTexture2D(GL_DRAW_FRAMEBUFFER, GL_COLOR_ATTACHMENT0, GL_TEXTURE_2D, 211 glFramebufferTexture2D(GL_DRAW_FRAMEBUFFER, GL_COLOR_ATTACHMENT0, GL_TEXTURE_2D,
196 m_xfb_texture_top, 0); 212 m_xfb_texture_top, 0);
197 glBindFramebuffer(GL_FRAMEBUFFER, 0); 213 glBindFramebuffer(GL_FRAMEBUFFER, 0);
198 214
199 glGenFramebuffers(1, &m_xfb_bottom); // Generate framebuffer 215 glGenFramebuffers(1, &m_xfb_bottom); // Generate framebuffer
200 glBindFramebuffer(GL_DRAW_FRAMEBUFFER, m_xfb_bottom); 216 glBindFramebuffer(GL_DRAW_FRAMEBUFFER, m_xfb_bottom);
201 glFramebufferTexture2D(GL_DRAW_FRAMEBUFFER, GL_COLOR_ATTACHMENT0, GL_TEXTURE_2D, 217 glFramebufferTexture2D(GL_DRAW_FRAMEBUFFER, GL_COLOR_ATTACHMENT0, GL_TEXTURE_2D,
202 m_xfb_texture_bottom, 0); 218 m_xfb_texture_bottom, 0);
203 glBindFramebuffer(GL_FRAMEBUFFER, 0); 219 glBindFramebuffer(GL_FRAMEBUFFER, 0);
204} 220}
@@ -214,7 +230,7 @@ void RendererOpenGL::RenderFramebuffer() {
214 glReadBuffer(GL_COLOR_ATTACHMENT0); 230 glReadBuffer(GL_COLOR_ATTACHMENT0);
215 231
216 // Blit 232 // Blit
217 glBlitFramebuffer(0, 0, m_resolution_width, m_resolution_height, 0, 0, m_resolution_width, 233 glBlitFramebuffer(0, 0, m_resolution_width, m_resolution_height, 0, 0, m_resolution_width,
218 m_resolution_height, GL_COLOR_BUFFER_BIT, GL_LINEAR); 234 m_resolution_height, GL_COLOR_BUFFER_BIT, GL_LINEAR);
219 235
220 // Update the FPS count 236 // Update the FPS count
@@ -230,7 +246,7 @@ void RendererOpenGL::RenderFramebuffer() {
230void RendererOpenGL::UpdateFramerate() { 246void RendererOpenGL::UpdateFramerate() {
231} 247}
232 248
233/** 249/**
234 * Set the emulator window to use for renderer 250 * Set the emulator window to use for renderer
235 * @param window EmuWindow handle to emulator window to use for rendering 251 * @param window EmuWindow handle to emulator window to use for rendering
236 */ 252 */
@@ -264,7 +280,7 @@ void RendererOpenGL::Init() {
264 280
265 GLenum err = glewInit(); 281 GLenum err = glewInit();
266 if (GLEW_OK != err) { 282 if (GLEW_OK != err) {
267 ERROR_LOG(RENDER, "Failed to initialize GLEW! Error message: \"%s\". Exiting...", 283 ERROR_LOG(RENDER, "Failed to initialize GLEW! Error message: \"%s\". Exiting...",
268 glewGetErrorString(err)); 284 glewGetErrorString(err));
269 exit(-1); 285 exit(-1);
270 } 286 }
diff --git a/src/video_core/renderer_opengl/renderer_opengl.h b/src/video_core/renderer_opengl/renderer_opengl.h
index dd811cad6..30f4febe0 100644
--- a/src/video_core/renderer_opengl/renderer_opengl.h
+++ b/src/video_core/renderer_opengl/renderer_opengl.h
@@ -84,7 +84,6 @@ private:
84 // "Flipped" framebuffers translate scanlines from native 3DS left-to-right to top-to-bottom 84 // "Flipped" framebuffers translate scanlines from native 3DS left-to-right to top-to-bottom
85 // as OpenGL expects them in a texture. There probably is a more efficient way of doing this: 85 // as OpenGL expects them in a texture. There probably is a more efficient way of doing this:
86 86
87 u8 m_xfb_top_flipped[VideoCore::kScreenTopWidth * VideoCore::kScreenTopWidth * 4]; 87 u8 m_xfb_top_flipped[VideoCore::kScreenTopWidth * VideoCore::kScreenTopHeight * 4];
88 u8 m_xfb_bottom_flipped[VideoCore::kScreenTopWidth * VideoCore::kScreenTopWidth * 4]; 88 u8 m_xfb_bottom_flipped[VideoCore::kScreenBottomWidth * VideoCore::kScreenBottomHeight * 4];
89 89};
90}; \ No newline at end of file
HIC SVNT DRACONES