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-rw-r--r--src/android/app/build.gradle.kts3
-rw-r--r--src/core/CMakeLists.txt8
-rw-r--r--src/core/arm/nce/arm_nce.cpp107
-rw-r--r--src/core/arm/nce/arm_nce.h13
-rw-r--r--src/core/arm/nce/arm_nce.s60
-rw-r--r--src/core/arm/nce/arm_nce_asm_definitions.h3
-rw-r--r--src/core/arm/nce/interpreter_visitor.cpp825
-rw-r--r--src/core/arm/nce/interpreter_visitor.h103
-rw-r--r--src/core/arm/nce/visitor_base.h2777
9 files changed, 3854 insertions, 45 deletions
diff --git a/src/android/app/build.gradle.kts b/src/android/app/build.gradle.kts
index 5721327e7..f763c657e 100644
--- a/src/android/app/build.gradle.kts
+++ b/src/android/app/build.gradle.kts
@@ -174,7 +174,8 @@ android {
174 "-DANDROID_ARM_NEON=true", // cryptopp requires Neon to work 174 "-DANDROID_ARM_NEON=true", // cryptopp requires Neon to work
175 "-DYUZU_USE_BUNDLED_VCPKG=ON", 175 "-DYUZU_USE_BUNDLED_VCPKG=ON",
176 "-DYUZU_USE_BUNDLED_FFMPEG=ON", 176 "-DYUZU_USE_BUNDLED_FFMPEG=ON",
177 "-DYUZU_ENABLE_LTO=ON" 177 "-DYUZU_ENABLE_LTO=ON",
178 "-DCMAKE_EXPORT_COMPILE_COMMANDS=ON"
178 ) 179 )
179 180
180 abiFilters("arm64-v8a", "x86_64") 181 abiFilters("arm64-v8a", "x86_64")
diff --git a/src/core/CMakeLists.txt b/src/core/CMakeLists.txt
index dced37079..b22c9fd05 100644
--- a/src/core/CMakeLists.txt
+++ b/src/core/CMakeLists.txt
@@ -953,15 +953,19 @@ if (HAS_NCE)
953 set(CMAKE_ASM_FLAGS "${CFLAGS} -x assembler-with-cpp") 953 set(CMAKE_ASM_FLAGS "${CFLAGS} -x assembler-with-cpp")
954 954
955 target_sources(core PRIVATE 955 target_sources(core PRIVATE
956 arm/nce/arm_nce_asm_definitions.h
956 arm/nce/arm_nce.cpp 957 arm/nce/arm_nce.cpp
957 arm/nce/arm_nce.h 958 arm/nce/arm_nce.h
958 arm/nce/arm_nce.s 959 arm/nce/arm_nce.s
959 arm/nce/guest_context.h 960 arm/nce/guest_context.h
961 arm/nce/instructions.h
962 arm/nce/interpreter_visitor.cpp
963 arm/nce/interpreter_visitor.h
960 arm/nce/patcher.cpp 964 arm/nce/patcher.cpp
961 arm/nce/patcher.h 965 arm/nce/patcher.h
962 arm/nce/instructions.h 966 arm/nce/visitor_base.h
963 ) 967 )
964 target_link_libraries(core PRIVATE merry::oaknut) 968 target_link_libraries(core PRIVATE merry::mcl merry::oaknut)
965endif() 969endif()
966 970
967if (ARCHITECTURE_x86_64 OR ARCHITECTURE_arm64) 971if (ARCHITECTURE_x86_64 OR ARCHITECTURE_arm64)
diff --git a/src/core/arm/nce/arm_nce.cpp b/src/core/arm/nce/arm_nce.cpp
index b42a32a0b..1311e66a9 100644
--- a/src/core/arm/nce/arm_nce.cpp
+++ b/src/core/arm/nce/arm_nce.cpp
@@ -6,7 +6,7 @@
6 6
7#include "common/signal_chain.h" 7#include "common/signal_chain.h"
8#include "core/arm/nce/arm_nce.h" 8#include "core/arm/nce/arm_nce.h"
9#include "core/arm/nce/guest_context.h" 9#include "core/arm/nce/interpreter_visitor.h"
10#include "core/arm/nce/patcher.h" 10#include "core/arm/nce/patcher.h"
11#include "core/core.h" 11#include "core/core.h"
12#include "core/memory.h" 12#include "core/memory.h"
@@ -21,7 +21,8 @@ namespace Core {
21 21
22namespace { 22namespace {
23 23
24struct sigaction g_orig_action; 24struct sigaction g_orig_bus_action;
25struct sigaction g_orig_segv_action;
25 26
26// Verify assembly offsets. 27// Verify assembly offsets.
27using NativeExecutionParameters = Kernel::KThread::NativeExecutionParameters; 28using NativeExecutionParameters = Kernel::KThread::NativeExecutionParameters;
@@ -37,6 +38,9 @@ fpsimd_context* GetFloatingPointState(mcontext_t& host_ctx) {
37 return reinterpret_cast<fpsimd_context*>(header); 38 return reinterpret_cast<fpsimd_context*>(header);
38} 39}
39 40
41using namespace Common::Literals;
42constexpr u32 StackSize = 32_KiB;
43
40} // namespace 44} // namespace
41 45
42void* ArmNce::RestoreGuestContext(void* raw_context) { 46void* ArmNce::RestoreGuestContext(void* raw_context) {
@@ -104,19 +108,10 @@ void ArmNce::SaveGuestContext(GuestContext* guest_ctx, void* raw_context) {
104 host_ctx.regs[0] = guest_ctx->esr_el1.exchange(0); 108 host_ctx.regs[0] = guest_ctx->esr_el1.exchange(0);
105} 109}
106 110
107bool ArmNce::HandleGuestFault(GuestContext* guest_ctx, void* raw_info, void* raw_context) { 111bool ArmNce::HandleFailedGuestFault(GuestContext* guest_ctx, void* raw_info, void* raw_context) {
108 auto& host_ctx = static_cast<ucontext_t*>(raw_context)->uc_mcontext; 112 auto& host_ctx = static_cast<ucontext_t*>(raw_context)->uc_mcontext;
109 auto* info = static_cast<siginfo_t*>(raw_info); 113 auto* info = static_cast<siginfo_t*>(raw_info);
110 114
111 // Try to handle an invalid access.
112 // TODO: handle accesses which split a page?
113 const Common::ProcessAddress addr =
114 (reinterpret_cast<u64>(info->si_addr) & ~Memory::YUZU_PAGEMASK);
115 if (guest_ctx->system->ApplicationMemory().InvalidateNCE(addr, Memory::YUZU_PAGESIZE)) {
116 // We handled the access successfully and are returning to guest code.
117 return true;
118 }
119
120 // We can't handle the access, so determine why we crashed. 115 // We can't handle the access, so determine why we crashed.
121 const bool is_prefetch_abort = host_ctx.pc == reinterpret_cast<u64>(info->si_addr); 116 const bool is_prefetch_abort = host_ctx.pc == reinterpret_cast<u64>(info->si_addr);
122 117
@@ -143,8 +138,44 @@ bool ArmNce::HandleGuestFault(GuestContext* guest_ctx, void* raw_info, void* raw
143 return false; 138 return false;
144} 139}
145 140
146void ArmNce::HandleHostFault(int sig, void* raw_info, void* raw_context) { 141bool ArmNce::HandleGuestAlignmentFault(GuestContext* guest_ctx, void* raw_info, void* raw_context) {
147 return g_orig_action.sa_sigaction(sig, static_cast<siginfo_t*>(raw_info), raw_context); 142 auto& host_ctx = static_cast<ucontext_t*>(raw_context)->uc_mcontext;
143 auto* fpctx = GetFloatingPointState(host_ctx);
144 auto& memory = guest_ctx->system->ApplicationMemory();
145
146 // Match and execute an instruction.
147 auto next_pc = MatchAndExecuteOneInstruction(memory, &host_ctx, fpctx);
148 if (next_pc) {
149 host_ctx.pc = *next_pc;
150 return true;
151 }
152
153 // We couldn't handle the access.
154 return HandleFailedGuestFault(guest_ctx, raw_info, raw_context);
155}
156
157bool ArmNce::HandleGuestAccessFault(GuestContext* guest_ctx, void* raw_info, void* raw_context) {
158 auto* info = static_cast<siginfo_t*>(raw_info);
159
160 // Try to handle an invalid access.
161 // TODO: handle accesses which split a page?
162 const Common::ProcessAddress addr =
163 (reinterpret_cast<u64>(info->si_addr) & ~Memory::YUZU_PAGEMASK);
164 if (guest_ctx->system->ApplicationMemory().InvalidateNCE(addr, Memory::YUZU_PAGESIZE)) {
165 // We handled the access successfully and are returning to guest code.
166 return true;
167 }
168
169 // We couldn't handle the access.
170 return HandleFailedGuestFault(guest_ctx, raw_info, raw_context);
171}
172
173void ArmNce::HandleHostAlignmentFault(int sig, void* raw_info, void* raw_context) {
174 return g_orig_bus_action.sa_sigaction(sig, static_cast<siginfo_t*>(raw_info), raw_context);
175}
176
177void ArmNce::HandleHostAccessFault(int sig, void* raw_info, void* raw_context) {
178 return g_orig_segv_action.sa_sigaction(sig, static_cast<siginfo_t*>(raw_info), raw_context);
148} 179}
149 180
150void ArmNce::LockThread(Kernel::KThread* thread) { 181void ArmNce::LockThread(Kernel::KThread* thread) {
@@ -225,18 +256,31 @@ ArmNce::ArmNce(System& system, bool uses_wall_clock, std::size_t core_index)
225ArmNce::~ArmNce() = default; 256ArmNce::~ArmNce() = default;
226 257
227void ArmNce::Initialize() { 258void ArmNce::Initialize() {
228 m_thread_id = gettid(); 259 if (m_thread_id == -1) {
260 m_thread_id = gettid();
261 }
262
263 // Configure signal stack.
264 if (!m_stack) {
265 m_stack = std::make_unique<u8[]>(StackSize);
266
267 stack_t ss{};
268 ss.ss_sp = m_stack.get();
269 ss.ss_size = StackSize;
270 sigaltstack(&ss, nullptr);
271 }
229 272
230 // Setup our signals 273 // Set up signals.
231 static std::once_flag signals; 274 static std::once_flag flag;
232 std::call_once(signals, [] { 275 std::call_once(flag, [] {
233 using HandlerType = decltype(sigaction::sa_sigaction); 276 using HandlerType = decltype(sigaction::sa_sigaction);
234 277
235 sigset_t signal_mask; 278 sigset_t signal_mask;
236 sigemptyset(&signal_mask); 279 sigemptyset(&signal_mask);
237 sigaddset(&signal_mask, ReturnToRunCodeByExceptionLevelChangeSignal); 280 sigaddset(&signal_mask, ReturnToRunCodeByExceptionLevelChangeSignal);
238 sigaddset(&signal_mask, BreakFromRunCodeSignal); 281 sigaddset(&signal_mask, BreakFromRunCodeSignal);
239 sigaddset(&signal_mask, GuestFaultSignal); 282 sigaddset(&signal_mask, GuestAlignmentFaultSignal);
283 sigaddset(&signal_mask, GuestAccessFaultSignal);
240 284
241 struct sigaction return_to_run_code_action {}; 285 struct sigaction return_to_run_code_action {};
242 return_to_run_code_action.sa_flags = SA_SIGINFO | SA_ONSTACK; 286 return_to_run_code_action.sa_flags = SA_SIGINFO | SA_ONSTACK;
@@ -253,18 +297,19 @@ void ArmNce::Initialize() {
253 break_from_run_code_action.sa_mask = signal_mask; 297 break_from_run_code_action.sa_mask = signal_mask;
254 Common::SigAction(BreakFromRunCodeSignal, &break_from_run_code_action, nullptr); 298 Common::SigAction(BreakFromRunCodeSignal, &break_from_run_code_action, nullptr);
255 299
256 struct sigaction fault_action {}; 300 struct sigaction alignment_fault_action {};
257 fault_action.sa_flags = SA_SIGINFO | SA_ONSTACK | SA_RESTART; 301 alignment_fault_action.sa_flags = SA_SIGINFO | SA_ONSTACK;
258 fault_action.sa_sigaction = reinterpret_cast<HandlerType>(&ArmNce::GuestFaultSignalHandler); 302 alignment_fault_action.sa_sigaction =
259 fault_action.sa_mask = signal_mask; 303 reinterpret_cast<HandlerType>(&ArmNce::GuestAlignmentFaultSignalHandler);
260 Common::SigAction(GuestFaultSignal, &fault_action, &g_orig_action); 304 alignment_fault_action.sa_mask = signal_mask;
261 305 Common::SigAction(GuestAlignmentFaultSignal, &alignment_fault_action, nullptr);
262 // Simplify call for g_orig_action. 306
263 // These fields occupy the same space in memory, so this should be a no-op in practice. 307 struct sigaction access_fault_action {};
264 if (!(g_orig_action.sa_flags & SA_SIGINFO)) { 308 access_fault_action.sa_flags = SA_SIGINFO | SA_ONSTACK | SA_RESTART;
265 g_orig_action.sa_sigaction = 309 access_fault_action.sa_sigaction =
266 reinterpret_cast<decltype(g_orig_action.sa_sigaction)>(g_orig_action.sa_handler); 310 reinterpret_cast<HandlerType>(&ArmNce::GuestAccessFaultSignalHandler);
267 } 311 access_fault_action.sa_mask = signal_mask;
312 Common::SigAction(GuestAccessFaultSignal, &access_fault_action, &g_orig_segv_action);
268 }); 313 });
269} 314}
270 315
diff --git a/src/core/arm/nce/arm_nce.h b/src/core/arm/nce/arm_nce.h
index f55c10d1d..be9b304c4 100644
--- a/src/core/arm/nce/arm_nce.h
+++ b/src/core/arm/nce/arm_nce.h
@@ -61,7 +61,8 @@ private:
61 static void ReturnToRunCodeByExceptionLevelChangeSignalHandler(int sig, void* info, 61 static void ReturnToRunCodeByExceptionLevelChangeSignalHandler(int sig, void* info,
62 void* raw_context); 62 void* raw_context);
63 static void BreakFromRunCodeSignalHandler(int sig, void* info, void* raw_context); 63 static void BreakFromRunCodeSignalHandler(int sig, void* info, void* raw_context);
64 static void GuestFaultSignalHandler(int sig, void* info, void* raw_context); 64 static void GuestAlignmentFaultSignalHandler(int sig, void* info, void* raw_context);
65 static void GuestAccessFaultSignalHandler(int sig, void* info, void* raw_context);
65 66
66 static void LockThreadParameters(void* tpidr); 67 static void LockThreadParameters(void* tpidr);
67 static void UnlockThreadParameters(void* tpidr); 68 static void UnlockThreadParameters(void* tpidr);
@@ -70,8 +71,11 @@ private:
70 // C++ implementation functions for assembly definitions. 71 // C++ implementation functions for assembly definitions.
71 static void* RestoreGuestContext(void* raw_context); 72 static void* RestoreGuestContext(void* raw_context);
72 static void SaveGuestContext(GuestContext* ctx, void* raw_context); 73 static void SaveGuestContext(GuestContext* ctx, void* raw_context);
73 static bool HandleGuestFault(GuestContext* ctx, void* info, void* raw_context); 74 static bool HandleFailedGuestFault(GuestContext* ctx, void* info, void* raw_context);
74 static void HandleHostFault(int sig, void* info, void* raw_context); 75 static bool HandleGuestAlignmentFault(GuestContext* ctx, void* info, void* raw_context);
76 static bool HandleGuestAccessFault(GuestContext* ctx, void* info, void* raw_context);
77 static void HandleHostAlignmentFault(int sig, void* info, void* raw_context);
78 static void HandleHostAccessFault(int sig, void* info, void* raw_context);
75 79
76public: 80public:
77 Core::System& m_system; 81 Core::System& m_system;
@@ -83,6 +87,9 @@ public:
83 // Core context. 87 // Core context.
84 GuestContext m_guest_ctx{}; 88 GuestContext m_guest_ctx{};
85 Kernel::KThread* m_running_thread{}; 89 Kernel::KThread* m_running_thread{};
90
91 // Stack for signal processing.
92 std::unique_ptr<u8[]> m_stack{};
86}; 93};
87 94
88} // namespace Core 95} // namespace Core
diff --git a/src/core/arm/nce/arm_nce.s b/src/core/arm/nce/arm_nce.s
index 4aeda4740..c68c05949 100644
--- a/src/core/arm/nce/arm_nce.s
+++ b/src/core/arm/nce/arm_nce.s
@@ -130,11 +130,11 @@ _ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_:
130 ret 130 ret
131 131
132 132
133/* static void Core::ArmNce::GuestFaultSignalHandler(int sig, void* info, void* raw_context) */ 133/* static void Core::ArmNce::GuestAlignmentFaultSignalHandler(int sig, void* info, void* raw_context) */
134.section .text._ZN4Core6ArmNce23GuestFaultSignalHandlerEiPvS1_, "ax", %progbits 134.section .text._ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_, "ax", %progbits
135.global _ZN4Core6ArmNce23GuestFaultSignalHandlerEiPvS1_ 135.global _ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_
136.type _ZN4Core6ArmNce23GuestFaultSignalHandlerEiPvS1_, %function 136.type _ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_, %function
137_ZN4Core6ArmNce23GuestFaultSignalHandlerEiPvS1_: 137_ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_:
138 /* Check to see if we have the correct TLS magic. */ 138 /* Check to see if we have the correct TLS magic. */
139 mrs x8, tpidr_el0 139 mrs x8, tpidr_el0
140 ldr w9, [x8, #(TpidrEl0TlsMagic)] 140 ldr w9, [x8, #(TpidrEl0TlsMagic)]
@@ -146,7 +146,7 @@ _ZN4Core6ArmNce23GuestFaultSignalHandlerEiPvS1_:
146 146
147 /* Incorrect TLS magic, so this is a host fault. */ 147 /* Incorrect TLS magic, so this is a host fault. */
148 /* Tail call the handler. */ 148 /* Tail call the handler. */
149 b _ZN4Core6ArmNce15HandleHostFaultEiPvS1_ 149 b _ZN4Core6ArmNce24HandleHostAlignmentFaultEiPvS1_
150 150
1511: 1511:
152 /* Correct TLS magic, so this is a guest fault. */ 152 /* Correct TLS magic, so this is a guest fault. */
@@ -163,7 +163,53 @@ _ZN4Core6ArmNce23GuestFaultSignalHandlerEiPvS1_:
163 msr tpidr_el0, x3 163 msr tpidr_el0, x3
164 164
165 /* Call the handler. */ 165 /* Call the handler. */
166 bl _ZN4Core6ArmNce16HandleGuestFaultEPNS_12GuestContextEPvS3_ 166 bl _ZN4Core6ArmNce25HandleGuestAlignmentFaultEPNS_12GuestContextEPvS3_
167
168 /* If the handler returned false, we want to preserve the host tpidr_el0. */
169 cbz x0, 2f
170
171 /* Otherwise, restore guest tpidr_el0. */
172 msr tpidr_el0, x19
173
1742:
175 ldr x19, [sp, #0x10]
176 ldp x29, x30, [sp], #0x20
177 ret
178
179/* static void Core::ArmNce::GuestAccessFaultSignalHandler(int sig, void* info, void* raw_context) */
180.section .text._ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_, "ax", %progbits
181.global _ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_
182.type _ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_, %function
183_ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_:
184 /* Check to see if we have the correct TLS magic. */
185 mrs x8, tpidr_el0
186 ldr w9, [x8, #(TpidrEl0TlsMagic)]
187
188 LOAD_IMMEDIATE_32(w10, TlsMagic)
189
190 cmp w9, w10
191 b.eq 1f
192
193 /* Incorrect TLS magic, so this is a host fault. */
194 /* Tail call the handler. */
195 b _ZN4Core6ArmNce21HandleHostAccessFaultEiPvS1_
196
1971:
198 /* Correct TLS magic, so this is a guest fault. */
199 stp x29, x30, [sp, #-0x20]!
200 str x19, [sp, #0x10]
201 mov x29, sp
202
203 /* Save the old tpidr_el0. */
204 mov x19, x8
205
206 /* Restore host tpidr_el0. */
207 ldr x0, [x8, #(TpidrEl0NativeContext)]
208 ldr x3, [x0, #(GuestContextHostContext + HostContextTpidrEl0)]
209 msr tpidr_el0, x3
210
211 /* Call the handler. */
212 bl _ZN4Core6ArmNce22HandleGuestAccessFaultEPNS_12GuestContextEPvS3_
167 213
168 /* If the handler returned false, we want to preserve the host tpidr_el0. */ 214 /* If the handler returned false, we want to preserve the host tpidr_el0. */
169 cbz x0, 2f 215 cbz x0, 2f
diff --git a/src/core/arm/nce/arm_nce_asm_definitions.h b/src/core/arm/nce/arm_nce_asm_definitions.h
index 8a9b285b5..8ea4383f7 100644
--- a/src/core/arm/nce/arm_nce_asm_definitions.h
+++ b/src/core/arm/nce/arm_nce_asm_definitions.h
@@ -10,7 +10,8 @@
10 10
11#define ReturnToRunCodeByExceptionLevelChangeSignal SIGUSR2 11#define ReturnToRunCodeByExceptionLevelChangeSignal SIGUSR2
12#define BreakFromRunCodeSignal SIGURG 12#define BreakFromRunCodeSignal SIGURG
13#define GuestFaultSignal SIGSEGV 13#define GuestAccessFaultSignal SIGSEGV
14#define GuestAlignmentFaultSignal SIGBUS
14 15
15#define GuestContextSp 0xF8 16#define GuestContextSp 0xF8
16#define GuestContextHostContext 0x320 17#define GuestContextHostContext 0x320
diff --git a/src/core/arm/nce/interpreter_visitor.cpp b/src/core/arm/nce/interpreter_visitor.cpp
new file mode 100644
index 000000000..8e81c66a5
--- /dev/null
+++ b/src/core/arm/nce/interpreter_visitor.cpp
@@ -0,0 +1,825 @@
1// SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
2// SPDX-FileCopyrightText: Copyright 2023 merryhime <https://mary.rs>
3// SPDX-License-Identifier: GPL-2.0-or-later
4
5#include "common/bit_cast.h"
6#include "core/arm/nce/interpreter_visitor.h"
7
8#include <dynarmic/frontend/A64/decoder/a64.h>
9
10namespace Core {
11
12template <u32 BitSize>
13u64 SignExtendToLong(u64 value) {
14 u64 mask = 1ULL << (BitSize - 1);
15 value &= (1ULL << BitSize) - 1;
16 return (value ^ mask) - mask;
17}
18
19static u64 SignExtendToLong(u64 value, u64 bitsize) {
20 switch (bitsize) {
21 case 8:
22 return SignExtendToLong<8>(value);
23 case 16:
24 return SignExtendToLong<16>(value);
25 case 32:
26 return SignExtendToLong<32>(value);
27 default:
28 return value;
29 }
30}
31
32template <u64 BitSize>
33u32 SignExtendToWord(u32 value) {
34 u32 mask = 1ULL << (BitSize - 1);
35 value &= (1ULL << BitSize) - 1;
36 return (value ^ mask) - mask;
37}
38
39static u32 SignExtendToWord(u32 value, u64 bitsize) {
40 switch (bitsize) {
41 case 8:
42 return SignExtendToWord<8>(value);
43 case 16:
44 return SignExtendToWord<16>(value);
45 default:
46 return value;
47 }
48}
49
50static u64 SignExtend(u64 value, u64 bitsize, u64 regsize) {
51 if (regsize == 64) {
52 return SignExtendToLong(value, bitsize);
53 } else {
54 return SignExtendToWord(static_cast<u32>(value), bitsize);
55 }
56}
57
58static u128 VectorGetElement(u128 value, u64 bitsize) {
59 switch (bitsize) {
60 case 8:
61 return {value[0] & ((1ULL << 8) - 1), 0};
62 case 16:
63 return {value[0] & ((1ULL << 16) - 1), 0};
64 case 32:
65 return {value[0] & ((1ULL << 32) - 1), 0};
66 case 64:
67 return {value[0], 0};
68 default:
69 return value;
70 }
71}
72
73u64 InterpreterVisitor::ExtendReg(size_t bitsize, Reg reg, Imm<3> option, u8 shift) {
74 ASSERT(shift <= 4);
75 ASSERT(bitsize == 32 || bitsize == 64);
76 u64 val = this->GetReg(reg);
77 size_t len;
78 u64 extended;
79 bool signed_extend;
80
81 switch (option.ZeroExtend()) {
82 case 0b000: { // UXTB
83 val &= ((1ULL << 8) - 1);
84 len = 8;
85 signed_extend = false;
86 break;
87 }
88 case 0b001: { // UXTH
89 val &= ((1ULL << 16) - 1);
90 len = 16;
91 signed_extend = false;
92 break;
93 }
94 case 0b010: { // UXTW
95 val &= ((1ULL << 32) - 1);
96 len = 32;
97 signed_extend = false;
98 break;
99 }
100 case 0b011: { // UXTX
101 len = 64;
102 signed_extend = false;
103 break;
104 }
105 case 0b100: { // SXTB
106 val &= ((1ULL << 8) - 1);
107 len = 8;
108 signed_extend = true;
109 break;
110 }
111 case 0b101: { // SXTH
112 val &= ((1ULL << 16) - 1);
113 len = 16;
114 signed_extend = true;
115 break;
116 }
117 case 0b110: { // SXTW
118 val &= ((1ULL << 32) - 1);
119 len = 32;
120 signed_extend = true;
121 break;
122 }
123 case 0b111: { // SXTX
124 len = 64;
125 signed_extend = true;
126 break;
127 }
128 default:
129 UNREACHABLE();
130 }
131
132 if (len < bitsize && signed_extend) {
133 extended = SignExtend(val, len, bitsize);
134 } else {
135 extended = val;
136 }
137
138 return extended << shift;
139}
140
141u128 InterpreterVisitor::GetVec(Vec v) {
142 return m_fpsimd_regs[static_cast<u32>(v)];
143}
144
145u64 InterpreterVisitor::GetReg(Reg r) {
146 return m_regs[static_cast<u32>(r)];
147}
148
149u64 InterpreterVisitor::GetSp() {
150 return m_sp;
151}
152
153u64 InterpreterVisitor::GetPc() {
154 return m_pc;
155}
156
157void InterpreterVisitor::SetVec(Vec v, u128 value) {
158 m_fpsimd_regs[static_cast<u32>(v)] = value;
159}
160
161void InterpreterVisitor::SetReg(Reg r, u64 value) {
162 m_regs[static_cast<u32>(r)] = value;
163}
164
165void InterpreterVisitor::SetSp(u64 value) {
166 m_sp = value;
167}
168
169bool InterpreterVisitor::Ordered(size_t size, bool L, bool o0, Reg Rn, Reg Rt) {
170 const auto memop = L ? MemOp::Load : MemOp::Store;
171 const size_t elsize = 8 << size;
172 const size_t datasize = elsize;
173
174 // Operation
175 const size_t dbytes = datasize / 8;
176
177 u64 address;
178 if (Rn == Reg::SP) {
179 address = this->GetSp();
180 } else {
181 address = this->GetReg(Rn);
182 }
183
184 switch (memop) {
185 case MemOp::Store: {
186 std::atomic_thread_fence(std::memory_order_seq_cst);
187 u64 value = this->GetReg(Rt);
188 m_memory.WriteBlock(address, &value, dbytes);
189 std::atomic_thread_fence(std::memory_order_seq_cst);
190 break;
191 }
192 case MemOp::Load: {
193 u64 value = 0;
194 m_memory.ReadBlock(address, &value, dbytes);
195 this->SetReg(Rt, value);
196 std::atomic_thread_fence(std::memory_order_seq_cst);
197 break;
198 }
199 default:
200 UNREACHABLE();
201 }
202
203 return true;
204}
205
206bool InterpreterVisitor::STLLR(Imm<2> sz, Reg Rn, Reg Rt) {
207 const size_t size = sz.ZeroExtend<size_t>();
208 const bool L = 0;
209 const bool o0 = 0;
210 return this->Ordered(size, L, o0, Rn, Rt);
211}
212
213bool InterpreterVisitor::STLR(Imm<2> sz, Reg Rn, Reg Rt) {
214 const size_t size = sz.ZeroExtend<size_t>();
215 const bool L = 0;
216 const bool o0 = 1;
217 return this->Ordered(size, L, o0, Rn, Rt);
218}
219
220bool InterpreterVisitor::LDLAR(Imm<2> sz, Reg Rn, Reg Rt) {
221 const size_t size = sz.ZeroExtend<size_t>();
222 const bool L = 1;
223 const bool o0 = 0;
224 return this->Ordered(size, L, o0, Rn, Rt);
225}
226
227bool InterpreterVisitor::LDAR(Imm<2> sz, Reg Rn, Reg Rt) {
228 const size_t size = sz.ZeroExtend<size_t>();
229 const bool L = 1;
230 const bool o0 = 1;
231 return this->Ordered(size, L, o0, Rn, Rt);
232}
233
234bool InterpreterVisitor::LDR_lit_gen(bool opc_0, Imm<19> imm19, Reg Rt) {
235 const size_t size = opc_0 == 0 ? 4 : 8;
236 const s64 offset = Dynarmic::concatenate(imm19, Imm<2>{0}).SignExtend<s64>();
237 const u64 address = this->GetPc() + offset;
238
239 u64 data = 0;
240 m_memory.ReadBlock(address, &data, size);
241
242 this->SetReg(Rt, data);
243 return true;
244}
245
246bool InterpreterVisitor::LDR_lit_fpsimd(Imm<2> opc, Imm<19> imm19, Vec Vt) {
247 if (opc == 0b11) {
248 // Unallocated encoding
249 return false;
250 }
251
252 const u64 size = 4 << opc.ZeroExtend();
253 const u64 offset = imm19.SignExtend<u64>() << 2;
254 const u64 address = this->GetPc() + offset;
255
256 u128 data{};
257 m_memory.ReadBlock(address, &data, size);
258 this->SetVec(Vt, data);
259 return true;
260}
261
262bool InterpreterVisitor::STP_LDP_gen(Imm<2> opc, bool not_postindex, bool wback, Imm<1> L,
263 Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt) {
264 if ((L == 0 && opc.Bit<0>() == 1) || opc == 0b11) {
265 // Unallocated encoding
266 return false;
267 }
268
269 const auto memop = L == 1 ? MemOp::Load : MemOp::Store;
270 if (memop == MemOp::Load && wback && (Rt == Rn || Rt2 == Rn) && Rn != Reg::R31) {
271 // Unpredictable instruction
272 return false;
273 }
274 if (memop == MemOp::Store && wback && (Rt == Rn || Rt2 == Rn) && Rn != Reg::R31) {
275 // Unpredictable instruction
276 return false;
277 }
278 if (memop == MemOp::Load && Rt == Rt2) {
279 // Unpredictable instruction
280 return false;
281 }
282
283 u64 address;
284 if (Rn == Reg::SP) {
285 address = this->GetSp();
286 } else {
287 address = this->GetReg(Rn);
288 }
289
290 const bool postindex = !not_postindex;
291 const bool signed_ = opc.Bit<0>() != 0;
292 const size_t scale = 2 + opc.Bit<1>();
293 const size_t datasize = 8 << scale;
294 const u64 offset = imm7.SignExtend<u64>() << scale;
295
296 if (!postindex) {
297 address += offset;
298 }
299
300 const size_t dbytes = datasize / 8;
301 switch (memop) {
302 case MemOp::Store: {
303 u64 data1 = this->GetReg(Rt);
304 u64 data2 = this->GetReg(Rt2);
305 m_memory.WriteBlock(address, &data1, dbytes);
306 m_memory.WriteBlock(address + dbytes, &data2, dbytes);
307 break;
308 }
309 case MemOp::Load: {
310 u64 data1 = 0, data2 = 0;
311 m_memory.ReadBlock(address, &data1, dbytes);
312 m_memory.ReadBlock(address + dbytes, &data2, dbytes);
313 if (signed_) {
314 this->SetReg(Rt, SignExtend(data1, datasize, 64));
315 this->SetReg(Rt2, SignExtend(data2, datasize, 64));
316 } else {
317 this->SetReg(Rt, data1);
318 this->SetReg(Rt2, data2);
319 }
320 break;
321 }
322 default:
323 UNREACHABLE();
324 }
325
326 if (wback) {
327 if (postindex) {
328 address += offset;
329 }
330
331 if (Rn == Reg::SP) {
332 this->SetSp(address);
333 } else {
334 this->SetReg(Rn, address);
335 }
336 }
337
338 return true;
339}
340
341bool InterpreterVisitor::STP_LDP_fpsimd(Imm<2> opc, bool not_postindex, bool wback, Imm<1> L,
342 Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt) {
343 if (opc == 0b11) {
344 // Unallocated encoding
345 return false;
346 }
347
348 const auto memop = L == 1 ? MemOp::Load : MemOp::Store;
349 if (memop == MemOp::Load && Vt == Vt2) {
350 // Unpredictable instruction
351 return false;
352 }
353
354 u64 address;
355 if (Rn == Reg::SP) {
356 address = this->GetSp();
357 } else {
358 address = this->GetReg(Rn);
359 }
360
361 const bool postindex = !not_postindex;
362 const size_t scale = 2 + opc.ZeroExtend<size_t>();
363 const size_t datasize = 8 << scale;
364 const u64 offset = imm7.SignExtend<u64>() << scale;
365 const size_t dbytes = datasize / 8;
366
367 if (!postindex) {
368 address += offset;
369 }
370
371 switch (memop) {
372 case MemOp::Store: {
373 u128 data1 = VectorGetElement(this->GetVec(Vt), datasize);
374 u128 data2 = VectorGetElement(this->GetVec(Vt2), datasize);
375 m_memory.WriteBlock(address, &data1, dbytes);
376 m_memory.WriteBlock(address + dbytes, &data2, dbytes);
377 break;
378 }
379 case MemOp::Load: {
380 u128 data1{}, data2{};
381 m_memory.ReadBlock(address, &data1, dbytes);
382 m_memory.ReadBlock(address + dbytes, &data2, dbytes);
383 this->SetVec(Vt, data1);
384 this->SetVec(Vt2, data2);
385 break;
386 }
387 default:
388 UNREACHABLE();
389 }
390
391 if (wback) {
392 if (postindex) {
393 address += offset;
394 }
395
396 if (Rn == Reg::SP) {
397 this->SetSp(address);
398 } else {
399 this->SetReg(Rn, address);
400 }
401 }
402
403 return true;
404}
405
406bool InterpreterVisitor::RegisterImmediate(bool wback, bool postindex, size_t scale, u64 offset,
407 Imm<2> size, Imm<2> opc, Reg Rn, Reg Rt) {
408 MemOp memop;
409 bool signed_ = false;
410 size_t regsize = 0;
411
412 if (opc.Bit<1>() == 0) {
413 memop = opc.Bit<0>() ? MemOp::Load : MemOp::Store;
414 regsize = size == 0b11 ? 64 : 32;
415 signed_ = false;
416 } else if (size == 0b11) {
417 memop = MemOp::Prefetch;
418 ASSERT(!opc.Bit<0>());
419 } else {
420 memop = MemOp::Load;
421 ASSERT(!(size == 0b10 && opc.Bit<0>() == 1));
422 regsize = opc.Bit<0>() ? 32 : 64;
423 signed_ = true;
424 }
425
426 if (memop == MemOp::Load && wback && Rn == Rt && Rn != Reg::R31) {
427 // Unpredictable instruction
428 return false;
429 }
430 if (memop == MemOp::Store && wback && Rn == Rt && Rn != Reg::R31) {
431 // Unpredictable instruction
432 return false;
433 }
434
435 u64 address;
436 if (Rn == Reg::SP) {
437 address = this->GetSp();
438 } else {
439 address = this->GetReg(Rn);
440 }
441 if (!postindex) {
442 address += offset;
443 }
444
445 const size_t datasize = 8 << scale;
446 switch (memop) {
447 case MemOp::Store: {
448 u64 data = this->GetReg(Rt);
449 m_memory.WriteBlock(address, &data, datasize / 8);
450 break;
451 }
452 case MemOp::Load: {
453 u64 data = 0;
454 m_memory.ReadBlock(address, &data, datasize / 8);
455 if (signed_) {
456 this->SetReg(Rt, SignExtend(data, datasize, regsize));
457 } else {
458 this->SetReg(Rt, data);
459 }
460 break;
461 }
462 case MemOp::Prefetch:
463 // this->Prefetch(address, Rt)
464 break;
465 }
466
467 if (wback) {
468 if (postindex) {
469 address += offset;
470 }
471
472 if (Rn == Reg::SP) {
473 this->SetSp(address);
474 } else {
475 this->SetReg(Rn, address);
476 }
477 }
478
479 return true;
480}
481
482bool InterpreterVisitor::STRx_LDRx_imm_1(Imm<2> size, Imm<2> opc, Imm<9> imm9, bool not_postindex,
483 Reg Rn, Reg Rt) {
484 const bool wback = true;
485 const bool postindex = !not_postindex;
486 const size_t scale = size.ZeroExtend<size_t>();
487 const u64 offset = imm9.SignExtend<u64>();
488
489 return this->RegisterImmediate(wback, postindex, scale, offset, size, opc, Rn, Rt);
490}
491
492bool InterpreterVisitor::STRx_LDRx_imm_2(Imm<2> size, Imm<2> opc, Imm<12> imm12, Reg Rn, Reg Rt) {
493 const bool wback = false;
494 const bool postindex = false;
495 const size_t scale = size.ZeroExtend<size_t>();
496 const u64 offset = imm12.ZeroExtend<u64>() << scale;
497
498 return this->RegisterImmediate(wback, postindex, scale, offset, size, opc, Rn, Rt);
499}
500
501bool InterpreterVisitor::STURx_LDURx(Imm<2> size, Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) {
502 const bool wback = false;
503 const bool postindex = false;
504 const size_t scale = size.ZeroExtend<size_t>();
505 const u64 offset = imm9.SignExtend<u64>();
506
507 return this->RegisterImmediate(wback, postindex, scale, offset, size, opc, Rn, Rt);
508}
509
510bool InterpreterVisitor::SIMDImmediate(bool wback, bool postindex, size_t scale, u64 offset,
511 MemOp memop, Reg Rn, Vec Vt) {
512 const size_t datasize = 8 << scale;
513
514 u64 address;
515 if (Rn == Reg::SP) {
516 address = this->GetSp();
517 } else {
518 address = this->GetReg(Rn);
519 }
520
521 if (!postindex) {
522 address += offset;
523 }
524
525 switch (memop) {
526 case MemOp::Store: {
527 u128 data = VectorGetElement(this->GetVec(Vt), datasize);
528 m_memory.WriteBlock(address, &data, datasize / 8);
529 break;
530 }
531 case MemOp::Load: {
532 u128 data{};
533 m_memory.ReadBlock(address, &data, datasize);
534 this->SetVec(Vt, data);
535 break;
536 }
537 default:
538 UNREACHABLE();
539 }
540
541 if (wback) {
542 if (postindex) {
543 address += offset;
544 }
545
546 if (Rn == Reg::SP) {
547 this->SetSp(address);
548 } else {
549 this->SetReg(Rn, address);
550 }
551 }
552
553 return true;
554}
555
556bool InterpreterVisitor::STR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9,
557 bool not_postindex, Reg Rn, Vec Vt) {
558 const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>();
559 if (scale > 4) {
560 // Unallocated encoding
561 return false;
562 }
563
564 const bool wback = true;
565 const bool postindex = !not_postindex;
566 const u64 offset = imm9.SignExtend<u64>();
567
568 return this->SIMDImmediate(wback, postindex, scale, offset, MemOp::Store, Rn, Vt);
569}
570
571bool InterpreterVisitor::STR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn,
572 Vec Vt) {
573 const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>();
574 if (scale > 4) {
575 // Unallocated encoding
576 return false;
577 }
578
579 const bool wback = false;
580 const bool postindex = false;
581 const u64 offset = imm12.ZeroExtend<u64>() << scale;
582
583 return this->SIMDImmediate(wback, postindex, scale, offset, MemOp::Store, Rn, Vt);
584}
585
586bool InterpreterVisitor::LDR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9,
587 bool not_postindex, Reg Rn, Vec Vt) {
588 const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>();
589 if (scale > 4) {
590 // Unallocated encoding
591 return false;
592 }
593
594 const bool wback = true;
595 const bool postindex = !not_postindex;
596 const u64 offset = imm9.SignExtend<u64>();
597
598 return this->SIMDImmediate(wback, postindex, scale, offset, MemOp::Load, Rn, Vt);
599}
600
601bool InterpreterVisitor::LDR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn,
602 Vec Vt) {
603 const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>();
604 if (scale > 4) {
605 // Unallocated encoding
606 return false;
607 }
608
609 const bool wback = false;
610 const bool postindex = false;
611 const u64 offset = imm12.ZeroExtend<u64>() << scale;
612
613 return this->SIMDImmediate(wback, postindex, scale, offset, MemOp::Load, Rn, Vt);
614}
615
616bool InterpreterVisitor::STUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) {
617 const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>();
618 if (scale > 4) {
619 // Unallocated encoding
620 return false;
621 }
622
623 const bool wback = false;
624 const bool postindex = false;
625 const u64 offset = imm9.SignExtend<u64>();
626
627 return this->SIMDImmediate(wback, postindex, scale, offset, MemOp::Store, Rn, Vt);
628}
629
630bool InterpreterVisitor::LDUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) {
631 const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>();
632 if (scale > 4) {
633 // Unallocated encoding
634 return false;
635 }
636
637 const bool wback = false;
638 const bool postindex = false;
639 const u64 offset = imm9.SignExtend<u64>();
640
641 return this->SIMDImmediate(wback, postindex, scale, offset, MemOp::Load, Rn, Vt);
642}
643
644bool InterpreterVisitor::RegisterOffset(size_t scale, u8 shift, Imm<2> size, Imm<1> opc_1,
645 Imm<1> opc_0, Reg Rm, Imm<3> option, Reg Rn, Reg Rt) {
646 MemOp memop;
647 size_t regsize = 64;
648 bool signed_ = false;
649
650 if (opc_1 == 0) {
651 memop = opc_0 == 1 ? MemOp::Load : MemOp::Store;
652 regsize = size == 0b11 ? 64 : 32;
653 signed_ = false;
654 } else if (size == 0b11) {
655 memop = MemOp::Prefetch;
656 if (opc_0 == 1) {
657 // Unallocated encoding
658 return false;
659 }
660 } else {
661 memop = MemOp::Load;
662 if (size == 0b10 && opc_0 == 1) {
663 // Unallocated encoding
664 return false;
665 }
666 regsize = opc_0 == 1 ? 32 : 64;
667 signed_ = true;
668 }
669
670 const size_t datasize = 8 << scale;
671
672 // Operation
673 const u64 offset = this->ExtendReg(64, Rm, option, shift);
674
675 u64 address;
676 if (Rn == Reg::SP) {
677 address = this->GetSp();
678 } else {
679 address = this->GetReg(Rn);
680 }
681 address += offset;
682
683 switch (memop) {
684 case MemOp::Store: {
685 u64 data = this->GetReg(Rt);
686 m_memory.WriteBlock(address, &data, datasize / 8);
687 break;
688 }
689 case MemOp::Load: {
690 u64 data = 0;
691 m_memory.ReadBlock(address, &data, datasize / 8);
692 if (signed_) {
693 this->SetReg(Rt, SignExtend(data, datasize, regsize));
694 } else {
695 this->SetReg(Rt, data);
696 }
697 break;
698 }
699 case MemOp::Prefetch:
700 break;
701 }
702
703 return true;
704}
705
706bool InterpreterVisitor::STRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn,
707 Reg Rt) {
708 const Imm<1> opc_0{0};
709 const size_t scale = size.ZeroExtend<size_t>();
710 const u8 shift = S ? static_cast<u8>(scale) : 0;
711 if (!option.Bit<1>()) {
712 // Unallocated encoding
713 return false;
714 }
715 return this->RegisterOffset(scale, shift, size, opc_1, opc_0, Rm, option, Rn, Rt);
716}
717
718bool InterpreterVisitor::LDRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn,
719 Reg Rt) {
720 const Imm<1> opc_0{1};
721 const size_t scale = size.ZeroExtend<size_t>();
722 const u8 shift = S ? static_cast<u8>(scale) : 0;
723 if (!option.Bit<1>()) {
724 // Unallocated encoding
725 return false;
726 }
727 return this->RegisterOffset(scale, shift, size, opc_1, opc_0, Rm, option, Rn, Rt);
728}
729
730bool InterpreterVisitor::SIMDOffset(size_t scale, u8 shift, Imm<1> opc_0, Reg Rm, Imm<3> option,
731 Reg Rn, Vec Vt) {
732 const auto memop = opc_0 == 1 ? MemOp::Load : MemOp::Store;
733 const size_t datasize = 8 << scale;
734
735 // Operation
736 const u64 offset = this->ExtendReg(64, Rm, option, shift);
737
738 u64 address;
739 if (Rn == Reg::SP) {
740 address = this->GetSp();
741 } else {
742 address = this->GetReg(Rn);
743 }
744 address += offset;
745
746 switch (memop) {
747 case MemOp::Store: {
748 u128 data = VectorGetElement(this->GetVec(Vt), datasize);
749 m_memory.WriteBlock(address, &data, datasize / 8);
750 break;
751 }
752 case MemOp::Load: {
753 u128 data{};
754 m_memory.ReadBlock(address, &data, datasize / 8);
755 this->SetVec(Vt, data);
756 break;
757 }
758 default:
759 UNREACHABLE();
760 }
761
762 return true;
763}
764
765bool InterpreterVisitor::STR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S,
766 Reg Rn, Vec Vt) {
767 const Imm<1> opc_0{0};
768 const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>();
769 if (scale > 4) {
770 // Unallocated encoding
771 return false;
772 }
773 const u8 shift = S ? static_cast<u8>(scale) : 0;
774 if (!option.Bit<1>()) {
775 // Unallocated encoding
776 return false;
777 }
778 return this->SIMDOffset(scale, shift, opc_0, Rm, option, Rn, Vt);
779}
780
781bool InterpreterVisitor::LDR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S,
782 Reg Rn, Vec Vt) {
783 const Imm<1> opc_0{1};
784 const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>();
785 if (scale > 4) {
786 // Unallocated encoding
787 return false;
788 }
789 const u8 shift = S ? static_cast<u8>(scale) : 0;
790 if (!option.Bit<1>()) {
791 // Unallocated encoding
792 return false;
793 }
794 return this->SIMDOffset(scale, shift, opc_0, Rm, option, Rn, Vt);
795}
796
797std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, mcontext_t* context,
798 fpsimd_context* fpsimd_context) {
799 // Construct the interpreter.
800 std::span<u64, 31> regs(reinterpret_cast<u64*>(context->regs), 31);
801 std::span<u128, 32> vregs(reinterpret_cast<u128*>(fpsimd_context->vregs), 32);
802 u64& sp = *reinterpret_cast<u64*>(&context->sp);
803 const u64& pc = *reinterpret_cast<u64*>(&context->pc);
804
805 InterpreterVisitor visitor(memory, regs, vregs, sp, pc);
806
807 // Read the instruction at the program counter.
808 u32 instruction = memory.Read32(pc);
809 bool was_executed = false;
810
811 // Interpret the instruction.
812 if (auto decoder = Dynarmic::A64::Decode<VisitorBase>(instruction)) {
813 was_executed = decoder->get().call(visitor, instruction);
814 } else {
815 LOG_ERROR(Core_ARM, "Unallocated encoding: {:#x}", instruction);
816 }
817
818 if (was_executed) {
819 return pc + 4;
820 }
821
822 return std::nullopt;
823}
824
825} // namespace Core
diff --git a/src/core/arm/nce/interpreter_visitor.h b/src/core/arm/nce/interpreter_visitor.h
new file mode 100644
index 000000000..f90d876ab
--- /dev/null
+++ b/src/core/arm/nce/interpreter_visitor.h
@@ -0,0 +1,103 @@
1// SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
2// SPDX-FileCopyrightText: Copyright 2023 merryhime <https://mary.rs>
3// SPDX-License-Identifier: GPL-2.0-or-later
4
5#pragma once
6
7#include <signal.h>
8#include <unistd.h>
9
10#include "core/arm/nce/visitor_base.h"
11
12namespace Core {
13
14namespace Memory {
15class Memory;
16}
17
18class InterpreterVisitor final : public VisitorBase {
19public:
20 explicit InterpreterVisitor(Core::Memory::Memory& memory, std::span<u64, 31> regs,
21 std::span<u128, 32> fpsimd_regs, u64& sp, const u64& pc)
22 : m_memory(memory), m_regs(regs), m_fpsimd_regs(fpsimd_regs), m_sp(sp), m_pc(pc) {}
23 ~InterpreterVisitor() override = default;
24
25 enum class MemOp {
26 Load,
27 Store,
28 Prefetch,
29 };
30
31 u128 GetVec(Vec v);
32 u64 GetReg(Reg r);
33 u64 GetSp();
34 u64 GetPc();
35
36 void SetVec(Vec v, u128 value);
37 void SetReg(Reg r, u64 value);
38 void SetSp(u64 value);
39
40 u64 ExtendReg(size_t bitsize, Reg reg, Imm<3> option, u8 shift);
41
42 // Loads and stores - Load/Store Exclusive
43 bool Ordered(size_t size, bool L, bool o0, Reg Rn, Reg Rt);
44 bool STLLR(Imm<2> size, Reg Rn, Reg Rt) override;
45 bool STLR(Imm<2> size, Reg Rn, Reg Rt) override;
46 bool LDLAR(Imm<2> size, Reg Rn, Reg Rt) override;
47 bool LDAR(Imm<2> size, Reg Rn, Reg Rt) override;
48
49 // Loads and stores - Load register (literal)
50 bool LDR_lit_gen(bool opc_0, Imm<19> imm19, Reg Rt) override;
51 bool LDR_lit_fpsimd(Imm<2> opc, Imm<19> imm19, Vec Vt) override;
52
53 // Loads and stores - Load/Store register pair
54 bool STP_LDP_gen(Imm<2> opc, bool not_postindex, bool wback, Imm<1> L, Imm<7> imm7, Reg Rt2,
55 Reg Rn, Reg Rt) override;
56 bool STP_LDP_fpsimd(Imm<2> opc, bool not_postindex, bool wback, Imm<1> L, Imm<7> imm7, Vec Vt2,
57 Reg Rn, Vec Vt) override;
58
59 // Loads and stores - Load/Store register (immediate)
60 bool RegisterImmediate(bool wback, bool postindex, size_t scale, u64 offset, Imm<2> size,
61 Imm<2> opc, Reg Rn, Reg Rt);
62 bool STRx_LDRx_imm_1(Imm<2> size, Imm<2> opc, Imm<9> imm9, bool not_postindex, Reg Rn,
63 Reg Rt) override;
64 bool STRx_LDRx_imm_2(Imm<2> size, Imm<2> opc, Imm<12> imm12, Reg Rn, Reg Rt) override;
65 bool STURx_LDURx(Imm<2> size, Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) override;
66
67 bool SIMDImmediate(bool wback, bool postindex, size_t scale, u64 offset, MemOp memop, Reg Rn,
68 Vec Vt);
69 bool STR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, bool not_postindex, Reg Rn,
70 Vec Vt) override;
71 bool STR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn, Vec Vt) override;
72 bool LDR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, bool not_postindex, Reg Rn,
73 Vec Vt) override;
74 bool LDR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn, Vec Vt) override;
75 bool STUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) override;
76 bool LDUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) override;
77
78 // Loads and stores - Load/Store register (register offset)
79 bool RegisterOffset(size_t scale, u8 shift, Imm<2> size, Imm<1> opc_1, Imm<1> opc_0, Reg Rm,
80 Imm<3> option, Reg Rn, Reg Rt);
81 bool STRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn,
82 Reg Rt) override;
83 bool LDRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn,
84 Reg Rt) override;
85
86 bool SIMDOffset(size_t scale, u8 shift, Imm<1> opc_0, Reg Rm, Imm<3> option, Reg Rn, Vec Vt);
87 bool STR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn,
88 Vec Vt) override;
89 bool LDR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn,
90 Vec Vt) override;
91
92private:
93 Core::Memory::Memory& m_memory;
94 std::span<u64, 31> m_regs;
95 std::span<u128, 32> m_fpsimd_regs;
96 u64& m_sp;
97 const u64& m_pc;
98};
99
100std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, mcontext_t* context,
101 fpsimd_context* fpsimd_context);
102
103} // namespace Core
diff --git a/src/core/arm/nce/visitor_base.h b/src/core/arm/nce/visitor_base.h
new file mode 100644
index 000000000..8fb032912
--- /dev/null
+++ b/src/core/arm/nce/visitor_base.h
@@ -0,0 +1,2777 @@
1// SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
2// SPDX-FileCopyrightText: Copyright 2023 merryhime <https://mary.rs>
3// SPDX-License-Identifier: GPL-2.0-or-later
4
5#pragma once
6
7#include <dynarmic/frontend/A64/a64_types.h>
8#include <dynarmic/frontend/imm.h>
9
10namespace Core {
11
12class VisitorBase {
13public:
14 using instruction_return_type = bool;
15
16 template <size_t BitSize>
17 using Imm = Dynarmic::Imm<BitSize>;
18 using Reg = Dynarmic::A64::Reg;
19 using Vec = Dynarmic::A64::Vec;
20 using Cond = Dynarmic::A64::Cond;
21
22 virtual ~VisitorBase() {}
23
24 virtual bool UnallocatedEncoding() {
25 return false;
26 }
27
28 // Data processing - Immediate - PC relative addressing
29 virtual bool ADR(Imm<2> immlo, Imm<19> immhi, Reg Rd) {
30 return false;
31 }
32 virtual bool ADRP(Imm<2> immlo, Imm<19> immhi, Reg Rd) {
33 return false;
34 }
35
36 // Data processing - Immediate - Add/Sub (with tag)
37 virtual bool ADDG(Imm<6> offset_imm, Imm<4> tag_offset, Reg Rn, Reg Rd) {
38 return false;
39 }
40 virtual bool SUBG(Imm<6> offset_imm, Imm<4> tag_offset, Reg Rn, Reg Rd) {
41 return false;
42 }
43
44 // Data processing - Immediate - Add/Sub
45 virtual bool ADD_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd) {
46 return false;
47 }
48 virtual bool ADDS_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd) {
49 return false;
50 }
51 virtual bool SUB_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd) {
52 return false;
53 }
54 virtual bool SUBS_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd) {
55 return false;
56 }
57
58 // Data processing - Immediate - Logical
59 virtual bool AND_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) {
60 return false;
61 }
62 virtual bool ORR_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) {
63 return false;
64 }
65 virtual bool EOR_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) {
66 return false;
67 }
68 virtual bool ANDS_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) {
69 return false;
70 }
71
72 // Data processing - Immediate - Move Wide
73 virtual bool MOVN(bool sf, Imm<2> hw, Imm<16> imm16, Reg Rd) {
74 return false;
75 }
76 virtual bool MOVZ(bool sf, Imm<2> hw, Imm<16> imm16, Reg Rd) {
77 return false;
78 }
79 virtual bool MOVK(bool sf, Imm<2> hw, Imm<16> imm16, Reg Rd) {
80 return false;
81 }
82
83 // Data processing - Immediate - Bitfield
84 virtual bool SBFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) {
85 return false;
86 }
87 virtual bool BFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) {
88 return false;
89 }
90 virtual bool UBFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) {
91 return false;
92 }
93 virtual bool ASR_1(Imm<5> immr, Reg Rn, Reg Rd) {
94 return false;
95 }
96 virtual bool ASR_2(Imm<6> immr, Reg Rn, Reg Rd) {
97 return false;
98 }
99 virtual bool SXTB_1(Reg Rn, Reg Rd) {
100 return false;
101 }
102 virtual bool SXTB_2(Reg Rn, Reg Rd) {
103 return false;
104 }
105 virtual bool SXTH_1(Reg Rn, Reg Rd) {
106 return false;
107 }
108 virtual bool SXTH_2(Reg Rn, Reg Rd) {
109 return false;
110 }
111 virtual bool SXTW(Reg Rn, Reg Rd) {
112 return false;
113 }
114
115 // Data processing - Immediate - Extract
116 virtual bool EXTR(bool sf, bool N, Reg Rm, Imm<6> imms, Reg Rn, Reg Rd) {
117 return false;
118 }
119
120 // Conditional branch
121 virtual bool B_cond(Imm<19> imm19, Cond cond) {
122 return false;
123 }
124
125 // Exception generation
126 virtual bool SVC(Imm<16> imm16) {
127 return false;
128 }
129 virtual bool HVC(Imm<16> imm16) {
130 return false;
131 }
132 virtual bool SMC(Imm<16> imm16) {
133 return false;
134 }
135 virtual bool BRK(Imm<16> imm16) {
136 return false;
137 }
138 virtual bool HLT(Imm<16> imm16) {
139 return false;
140 }
141 virtual bool DCPS1(Imm<16> imm16) {
142 return false;
143 }
144 virtual bool DCPS2(Imm<16> imm16) {
145 return false;
146 }
147 virtual bool DCPS3(Imm<16> imm16) {
148 return false;
149 }
150
151 // System
152 virtual bool MSR_imm(Imm<3> op1, Imm<4> CRm, Imm<3> op2) {
153 return false;
154 }
155 virtual bool HINT(Imm<4> CRm, Imm<3> op2) {
156 return false;
157 }
158 virtual bool NOP() {
159 return false;
160 }
161 virtual bool YIELD() {
162 return false;
163 }
164 virtual bool WFE() {
165 return false;
166 }
167 virtual bool WFI() {
168 return false;
169 }
170 virtual bool SEV() {
171 return false;
172 }
173 virtual bool SEVL() {
174 return false;
175 }
176 virtual bool XPAC_1(bool D, Reg Rd) {
177 return false;
178 }
179 virtual bool XPAC_2() {
180 return false;
181 }
182 virtual bool PACIA_1(bool Z, Reg Rn, Reg Rd) {
183 return false;
184 }
185 virtual bool PACIA_2() {
186 return false;
187 }
188 virtual bool PACIB_1(bool Z, Reg Rn, Reg Rd) {
189 return false;
190 }
191 virtual bool PACIB_2() {
192 return false;
193 }
194 virtual bool AUTIA_1(bool Z, Reg Rn, Reg Rd) {
195 return false;
196 }
197 virtual bool AUTIA_2() {
198 return false;
199 }
200 virtual bool AUTIB_1(bool Z, Reg Rn, Reg Rd) {
201 return false;
202 }
203 virtual bool AUTIB_2() {
204 return false;
205 }
206 virtual bool BTI(Imm<2> upper_op2) {
207 return false;
208 }
209 virtual bool ESB() {
210 return false;
211 }
212 virtual bool PSB() {
213 return false;
214 }
215 virtual bool TSB() {
216 return false;
217 }
218 virtual bool CSDB() {
219 return false;
220 }
221 virtual bool CLREX(Imm<4> CRm) {
222 return false;
223 }
224 virtual bool DSB(Imm<4> CRm) {
225 return false;
226 }
227 virtual bool SSBB() {
228 return false;
229 }
230 virtual bool PSSBB() {
231 return false;
232 }
233 virtual bool DMB(Imm<4> CRm) {
234 return false;
235 }
236 virtual bool ISB(Imm<4> CRm) {
237 return false;
238 }
239 virtual bool SYS(Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt) {
240 return false;
241 }
242 virtual bool SB() {
243 return false;
244 }
245 virtual bool MSR_reg(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt) {
246 return false;
247 }
248 virtual bool SYSL(Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt) {
249 return false;
250 }
251 virtual bool MRS(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt) {
252 return false;
253 }
254
255 // System - Flag manipulation instructions
256 virtual bool CFINV() {
257 return false;
258 }
259 virtual bool RMIF(Imm<6> lsb, Reg Rn, Imm<4> mask) {
260 return false;
261 }
262 virtual bool SETF8(Reg Rn) {
263 return false;
264 }
265 virtual bool SETF16(Reg Rn) {
266 return false;
267 }
268
269 // System - Flag format instructions
270 virtual bool XAFlag() {
271 return false;
272 }
273 virtual bool AXFlag() {
274 return false;
275 }
276
277 // SYS: Data Cache
278 virtual bool DC_IVAC(Reg Rt) {
279 return false;
280 }
281 virtual bool DC_ISW(Reg Rt) {
282 return false;
283 }
284 virtual bool DC_CSW(Reg Rt) {
285 return false;
286 }
287 virtual bool DC_CISW(Reg Rt) {
288 return false;
289 }
290 virtual bool DC_ZVA(Reg Rt) {
291 return false;
292 }
293 virtual bool DC_CVAC(Reg Rt) {
294 return false;
295 }
296 virtual bool DC_CVAU(Reg Rt) {
297 return false;
298 }
299 virtual bool DC_CVAP(Reg Rt) {
300 return false;
301 }
302 virtual bool DC_CIVAC(Reg Rt) {
303 return false;
304 }
305
306 // SYS: Instruction Cache
307 virtual bool IC_IALLU() {
308 return false;
309 }
310 virtual bool IC_IALLUIS() {
311 return false;
312 }
313 virtual bool IC_IVAU(Reg Rt) {
314 return false;
315 }
316
317 // Unconditional branch (Register)
318 virtual bool BR(Reg Rn) {
319 return false;
320 }
321 virtual bool BRA(bool Z, bool M, Reg Rn, Reg Rm) {
322 return false;
323 }
324 virtual bool BLR(Reg Rn) {
325 return false;
326 }
327 virtual bool BLRA(bool Z, bool M, Reg Rn, Reg Rm) {
328 return false;
329 }
330 virtual bool RET(Reg Rn) {
331 return false;
332 }
333 virtual bool RETA(bool M) {
334 return false;
335 }
336 virtual bool ERET() {
337 return false;
338 }
339 virtual bool ERETA(bool M) {
340 return false;
341 }
342 virtual bool DRPS() {
343 return false;
344 }
345
346 // Unconditional branch (immediate)
347 virtual bool B_uncond(Imm<26> imm26) {
348 return false;
349 }
350 virtual bool BL(Imm<26> imm26) {
351 return false;
352 }
353
354 // Compare and branch (immediate)
355 virtual bool CBZ(bool sf, Imm<19> imm19, Reg Rt) {
356 return false;
357 }
358 virtual bool CBNZ(bool sf, Imm<19> imm19, Reg Rt) {
359 return false;
360 }
361 virtual bool TBZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt) {
362 return false;
363 }
364 virtual bool TBNZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt) {
365 return false;
366 }
367
368 // Loads and stores - Advanced SIMD Load/Store multiple structures
369 virtual bool STx_mult_1(bool Q, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt) {
370 return false;
371 }
372 virtual bool STx_mult_2(bool Q, Reg Rm, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt) {
373 return false;
374 }
375 virtual bool LDx_mult_1(bool Q, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt) {
376 return false;
377 }
378 virtual bool LDx_mult_2(bool Q, Reg Rm, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt) {
379 return false;
380 }
381
382 // Loads and stores - Advanced SIMD Load/Store single structures
383 virtual bool ST1_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
384 return false;
385 }
386 virtual bool ST1_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn,
387 Vec Vt) {
388 return false;
389 }
390 virtual bool ST3_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
391 return false;
392 }
393 virtual bool ST3_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn,
394 Vec Vt) {
395 return false;
396 }
397 virtual bool ST2_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
398 return false;
399 }
400 virtual bool ST2_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn,
401 Vec Vt) {
402 return false;
403 }
404 virtual bool ST4_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
405 return false;
406 }
407 virtual bool ST4_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn,
408 Vec Vt) {
409 return false;
410 }
411 virtual bool LD1_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
412 return false;
413 }
414 virtual bool LD1_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn,
415 Vec Vt) {
416 return false;
417 }
418 virtual bool LD3_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
419 return false;
420 }
421 virtual bool LD3_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn,
422 Vec Vt) {
423 return false;
424 }
425 virtual bool LD1R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt) {
426 return false;
427 }
428 virtual bool LD1R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt) {
429 return false;
430 }
431 virtual bool LD3R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt) {
432 return false;
433 }
434 virtual bool LD3R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt) {
435 return false;
436 }
437 virtual bool LD2_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
438 return false;
439 }
440 virtual bool LD2_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn,
441 Vec Vt) {
442 return false;
443 }
444 virtual bool LD4_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
445 return false;
446 }
447 virtual bool LD4_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn,
448 Vec Vt) {
449 return false;
450 }
451 virtual bool LD2R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt) {
452 return false;
453 }
454 virtual bool LD2R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt) {
455 return false;
456 }
457 virtual bool LD4R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt) {
458 return false;
459 }
460 virtual bool LD4R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt) {
461 return false;
462 }
463
464 // Loads and stores - Load/Store Exclusive
465 virtual bool STXR(Imm<2> size, Reg Rs, Reg Rn, Reg Rt) {
466 return false;
467 }
468 virtual bool STLXR(Imm<2> size, Reg Rs, Reg Rn, Reg Rt) {
469 return false;
470 }
471 virtual bool STXP(Imm<1> size, Reg Rs, Reg Rt2, Reg Rn, Reg Rt) {
472 return false;
473 }
474 virtual bool STLXP(Imm<1> size, Reg Rs, Reg Rt2, Reg Rn, Reg Rt) {
475 return false;
476 }
477 virtual bool LDXR(Imm<2> size, Reg Rn, Reg Rt) {
478 return false;
479 }
480 virtual bool LDAXR(Imm<2> size, Reg Rn, Reg Rt) {
481 return false;
482 }
483 virtual bool LDXP(Imm<1> size, Reg Rt2, Reg Rn, Reg Rt) {
484 return false;
485 }
486 virtual bool LDAXP(Imm<1> size, Reg Rt2, Reg Rn, Reg Rt) {
487 return false;
488 }
489 virtual bool STLLR(Imm<2> size, Reg Rn, Reg Rt) {
490 return false;
491 }
492 virtual bool STLR(Imm<2> size, Reg Rn, Reg Rt) {
493 return false;
494 }
495 virtual bool LDLAR(Imm<2> size, Reg Rn, Reg Rt) {
496 return false;
497 }
498 virtual bool LDAR(Imm<2> size, Reg Rn, Reg Rt) {
499 return false;
500 }
501 virtual bool CASP(bool sz, bool L, Reg Rs, bool o0, Reg Rn, Reg Rt) {
502 return false;
503 }
504 virtual bool CASB(bool L, Reg Rs, bool o0, Reg Rn, Reg Rt) {
505 return false;
506 }
507 virtual bool CASH(bool L, Reg Rs, bool o0, Reg Rn, Reg Rt) {
508 return false;
509 }
510 virtual bool CAS(bool sz, bool L, Reg Rs, bool o0, Reg Rn, Reg Rt) {
511 return false;
512 }
513
514 // Loads and stores - Load register (literal)
515 virtual bool LDR_lit_gen(bool opc_0, Imm<19> imm19, Reg Rt) {
516 return false;
517 }
518 virtual bool LDR_lit_fpsimd(Imm<2> opc, Imm<19> imm19, Vec Vt) {
519 return false;
520 }
521 virtual bool LDRSW_lit(Imm<19> imm19, Reg Rt) {
522 return false;
523 }
524 virtual bool PRFM_lit(Imm<19> imm19, Imm<5> prfop) {
525 return false;
526 }
527
528 // Loads and stores - Load/Store no-allocate pair
529 virtual bool STNP_LDNP_gen(Imm<1> upper_opc, Imm<1> L, Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt) {
530 return false;
531 }
532 virtual bool STNP_LDNP_fpsimd(Imm<2> opc, Imm<1> L, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt) {
533 return false;
534 }
535
536 // Loads and stores - Load/Store register pair
537 virtual bool STP_LDP_gen(Imm<2> opc, bool not_postindex, bool wback, Imm<1> L, Imm<7> imm7,
538 Reg Rt2, Reg Rn, Reg Rt) {
539 return false;
540 }
541 virtual bool STP_LDP_fpsimd(Imm<2> opc, bool not_postindex, bool wback, Imm<1> L, Imm<7> imm7,
542 Vec Vt2, Reg Rn, Vec Vt) {
543 return false;
544 }
545 virtual bool STGP_1(Imm<7> offset_imm, Reg Rt2, Reg Rn, Reg Rt) {
546 return false;
547 }
548 virtual bool STGP_2(Imm<7> offset_imm, Reg Rt2, Reg Rn, Reg Rt) {
549 return false;
550 }
551 virtual bool STGP_3(Imm<7> offset_imm, Reg Rt2, Reg Rn, Reg Rt) {
552 return false;
553 }
554
555 // Loads and stores - Load/Store register (immediate)
556 virtual bool STRx_LDRx_imm_1(Imm<2> size, Imm<2> opc, Imm<9> imm9, bool not_postindex, Reg Rn,
557 Reg Rt) {
558 return false;
559 }
560 virtual bool STRx_LDRx_imm_2(Imm<2> size, Imm<2> opc, Imm<12> imm12, Reg Rn, Reg Rt) {
561 return false;
562 }
563 virtual bool STURx_LDURx(Imm<2> size, Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) {
564 return false;
565 }
566 virtual bool PRFM_imm(Imm<12> imm12, Reg Rn, Reg Rt) {
567 return false;
568 }
569 virtual bool PRFM_unscaled_imm(Imm<9> imm9, Reg Rn, Reg Rt) {
570 return false;
571 }
572 virtual bool STR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, bool not_postindex,
573 Reg Rn, Vec Vt) {
574 return false;
575 }
576 virtual bool STR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn, Vec Vt) {
577 return false;
578 }
579 virtual bool LDR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, bool not_postindex,
580 Reg Rn, Vec Vt) {
581 return false;
582 }
583 virtual bool LDR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn, Vec Vt) {
584 return false;
585 }
586 virtual bool STUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) {
587 return false;
588 }
589 virtual bool LDUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) {
590 return false;
591 }
592
593 // Loads and stores - Load/Store register (unprivileged)
594 virtual bool STTRB(Imm<9> imm9, Reg Rn, Reg Rt) {
595 return false;
596 }
597 virtual bool LDTRB(Imm<9> imm9, Reg Rn, Reg Rt) {
598 return false;
599 }
600 virtual bool LDTRSB(Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) {
601 return false;
602 }
603 virtual bool STTRH(Imm<9> imm9, Reg Rn, Reg Rt) {
604 return false;
605 }
606 virtual bool LDTRH(Imm<9> imm9, Reg Rn, Reg Rt) {
607 return false;
608 }
609 virtual bool LDTRSH(Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) {
610 return false;
611 }
612 virtual bool STTR(Imm<2> size, Imm<9> imm9, Reg Rn, Reg Rt) {
613 return false;
614 }
615 virtual bool LDTR(Imm<2> size, Imm<9> imm9, Reg Rn, Reg Rt) {
616 return false;
617 }
618 virtual bool LDTRSW(Imm<9> imm9, Reg Rn, Reg Rt) {
619 return false;
620 }
621
622 // Loads and stores - Atomic memory options
623 virtual bool LDADDB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
624 return false;
625 }
626 virtual bool LDCLRB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
627 return false;
628 }
629 virtual bool LDEORB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
630 return false;
631 }
632 virtual bool LDSETB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
633 return false;
634 }
635 virtual bool LDSMAXB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
636 return false;
637 }
638 virtual bool LDSMINB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
639 return false;
640 }
641 virtual bool LDUMAXB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
642 return false;
643 }
644 virtual bool LDUMINB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
645 return false;
646 }
647 virtual bool SWPB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
648 return false;
649 }
650 virtual bool LDAPRB(Reg Rn, Reg Rt) {
651 return false;
652 }
653 virtual bool LDADDH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
654 return false;
655 }
656 virtual bool LDCLRH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
657 return false;
658 }
659 virtual bool LDEORH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
660 return false;
661 }
662 virtual bool LDSETH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
663 return false;
664 }
665 virtual bool LDSMAXH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
666 return false;
667 }
668 virtual bool LDSMINH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
669 return false;
670 }
671 virtual bool LDUMAXH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
672 return false;
673 }
674 virtual bool LDUMINH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
675 return false;
676 }
677 virtual bool SWPH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
678 return false;
679 }
680 virtual bool LDAPRH(Reg Rn, Reg Rt) {
681 return false;
682 }
683 virtual bool LDADD(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
684 return false;
685 }
686 virtual bool LDCLR(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
687 return false;
688 }
689 virtual bool LDEOR(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
690 return false;
691 }
692 virtual bool LDSET(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
693 return false;
694 }
695 virtual bool LDSMAX(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
696 return false;
697 }
698 virtual bool LDSMIN(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
699 return false;
700 }
701 virtual bool LDUMAX(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
702 return false;
703 }
704 virtual bool LDUMIN(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
705 return false;
706 }
707 virtual bool SWP(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
708 return false;
709 }
710 virtual bool LDAPR(Reg Rn, Reg Rt) {
711 return false;
712 }
713
714 // Loads and stores - Load/Store register (register offset)
715 virtual bool STRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn,
716 Reg Rt) {
717 return false;
718 }
719 virtual bool LDRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn,
720 Reg Rt) {
721 return false;
722 }
723 virtual bool STR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn,
724 Vec Vt) {
725 return false;
726 }
727 virtual bool LDR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn,
728 Vec Vt) {
729 return false;
730 }
731
732 // Loads and stores - Load/Store memory tags
733 virtual bool STG_1(Imm<9> imm9, Reg Rn) {
734 return false;
735 }
736 virtual bool STG_2(Imm<9> imm9, Reg Rn) {
737 return false;
738 }
739 virtual bool STG_3(Imm<9> imm9, Reg Rn) {
740 return false;
741 }
742 virtual bool LDG(Imm<9> offset_imm, Reg Rn, Reg Rt) {
743 return false;
744 }
745 virtual bool STZG_1(Imm<9> offset_imm, Reg Rn) {
746 return false;
747 }
748 virtual bool STZG_2(Imm<9> offset_imm, Reg Rn) {
749 return false;
750 }
751 virtual bool STZG_3(Imm<9> offset_imm, Reg Rn) {
752 return false;
753 }
754 virtual bool ST2G_1(Imm<9> offset_imm, Reg Rn) {
755 return false;
756 }
757 virtual bool ST2G_2(Imm<9> offset_imm, Reg Rn) {
758 return false;
759 }
760 virtual bool ST2G_3(Imm<9> offset_imm, Reg Rn) {
761 return false;
762 }
763 virtual bool STGV(Reg Rn, Reg Rt) {
764 return false;
765 }
766 virtual bool STZ2G_1(Imm<9> offset_imm, Reg Rn) {
767 return false;
768 }
769 virtual bool STZ2G_2(Imm<9> offset_imm, Reg Rn) {
770 return false;
771 }
772 virtual bool STZ2G_3(Imm<9> offset_imm, Reg Rn) {
773 return false;
774 }
775 virtual bool LDGV(Reg Rn, Reg Rt) {
776 return false;
777 }
778
779 // Loads and stores - Load/Store register (pointer authentication)
780 virtual bool LDRA(bool M, bool S, Imm<9> imm9, bool W, Reg Rn, Reg Rt) {
781 return false;
782 }
783
784 // Data Processing - Register - 2 source
785 virtual bool UDIV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
786 return false;
787 }
788 virtual bool SDIV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
789 return false;
790 }
791 virtual bool LSLV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
792 return false;
793 }
794 virtual bool LSRV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
795 return false;
796 }
797 virtual bool ASRV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
798 return false;
799 }
800 virtual bool RORV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
801 return false;
802 }
803 virtual bool CRC32(bool sf, Reg Rm, Imm<2> sz, Reg Rn, Reg Rd) {
804 return false;
805 }
806 virtual bool CRC32C(bool sf, Reg Rm, Imm<2> sz, Reg Rn, Reg Rd) {
807 return false;
808 }
809 virtual bool PACGA(Reg Rm, Reg Rn, Reg Rd) {
810 return false;
811 }
812 virtual bool SUBP(Reg Rm, Reg Rn, Reg Rd) {
813 return false;
814 }
815 virtual bool IRG(Reg Rm, Reg Rn, Reg Rd) {
816 return false;
817 }
818 virtual bool GMI(Reg Rm, Reg Rn, Reg Rd) {
819 return false;
820 }
821 virtual bool SUBPS(Reg Rm, Reg Rn, Reg Rd) {
822 return false;
823 }
824
825 // Data Processing - Register - 1 source
826 virtual bool RBIT_int(bool sf, Reg Rn, Reg Rd) {
827 return false;
828 }
829 virtual bool REV16_int(bool sf, Reg Rn, Reg Rd) {
830 return false;
831 }
832 virtual bool REV(bool sf, bool opc_0, Reg Rn, Reg Rd) {
833 return false;
834 }
835 virtual bool CLZ_int(bool sf, Reg Rn, Reg Rd) {
836 return false;
837 }
838 virtual bool CLS_int(bool sf, Reg Rn, Reg Rd) {
839 return false;
840 }
841 virtual bool REV32_int(Reg Rn, Reg Rd) {
842 return false;
843 }
844 virtual bool PACDA(bool Z, Reg Rn, Reg Rd) {
845 return false;
846 }
847 virtual bool PACDB(bool Z, Reg Rn, Reg Rd) {
848 return false;
849 }
850 virtual bool AUTDA(bool Z, Reg Rn, Reg Rd) {
851 return false;
852 }
853 virtual bool AUTDB(bool Z, Reg Rn, Reg Rd) {
854 return false;
855 }
856
857 // Data Processing - Register - Logical (shifted register)
858 virtual bool AND_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
859 return false;
860 }
861 virtual bool BIC_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
862 return false;
863 }
864 virtual bool ORR_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
865 return false;
866 }
867 virtual bool ORN_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
868 return false;
869 }
870 virtual bool EOR_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
871 return false;
872 }
873 virtual bool EON(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
874 return false;
875 }
876 virtual bool ANDS_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
877 return false;
878 }
879 virtual bool BICS(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
880 return false;
881 }
882
883 // Data Processing - Register - Add/Sub (shifted register)
884 virtual bool ADD_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
885 return false;
886 }
887 virtual bool ADDS_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
888 return false;
889 }
890 virtual bool SUB_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
891 return false;
892 }
893 virtual bool SUBS_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
894 return false;
895 }
896
897 // Data Processing - Register - Add/Sub (shifted register)
898 virtual bool ADD_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd) {
899 return false;
900 }
901 virtual bool ADDS_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd) {
902 return false;
903 }
904 virtual bool SUB_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd) {
905 return false;
906 }
907 virtual bool SUBS_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd) {
908 return false;
909 }
910
911 // Data Processing - Register - Add/Sub (with carry)
912 virtual bool ADC(bool sf, Reg Rm, Reg Rn, Reg Rd) {
913 return false;
914 }
915 virtual bool ADCS(bool sf, Reg Rm, Reg Rn, Reg Rd) {
916 return false;
917 }
918 virtual bool SBC(bool sf, Reg Rm, Reg Rn, Reg Rd) {
919 return false;
920 }
921 virtual bool SBCS(bool sf, Reg Rm, Reg Rn, Reg Rd) {
922 return false;
923 }
924
925 // Data Processing - Register - Conditional compare
926 virtual bool CCMN_reg(bool sf, Reg Rm, Cond cond, Reg Rn, Imm<4> nzcv) {
927 return false;
928 }
929 virtual bool CCMP_reg(bool sf, Reg Rm, Cond cond, Reg Rn, Imm<4> nzcv) {
930 return false;
931 }
932 virtual bool CCMN_imm(bool sf, Imm<5> imm5, Cond cond, Reg Rn, Imm<4> nzcv) {
933 return false;
934 }
935 virtual bool CCMP_imm(bool sf, Imm<5> imm5, Cond cond, Reg Rn, Imm<4> nzcv) {
936 return false;
937 }
938
939 // Data Processing - Register - Conditional select
940 virtual bool CSEL(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd) {
941 return false;
942 }
943 virtual bool CSINC(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd) {
944 return false;
945 }
946 virtual bool CSINV(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd) {
947 return false;
948 }
949 virtual bool CSNEG(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd) {
950 return false;
951 }
952
953 // Data Processing - Register - 3 source
954 virtual bool MADD(bool sf, Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
955 return false;
956 }
957 virtual bool MSUB(bool sf, Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
958 return false;
959 }
960 virtual bool SMADDL(Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
961 return false;
962 }
963 virtual bool SMSUBL(Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
964 return false;
965 }
966 virtual bool SMULH(Reg Rm, Reg Rn, Reg Rd) {
967 return false;
968 }
969 virtual bool UMADDL(Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
970 return false;
971 }
972 virtual bool UMSUBL(Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
973 return false;
974 }
975 virtual bool UMULH(Reg Rm, Reg Rn, Reg Rd) {
976 return false;
977 }
978
979 // Data Processing - FP and SIMD - AES
980 virtual bool AESE(Vec Vn, Vec Vd) {
981 return false;
982 }
983 virtual bool AESD(Vec Vn, Vec Vd) {
984 return false;
985 }
986 virtual bool AESMC(Vec Vn, Vec Vd) {
987 return false;
988 }
989 virtual bool AESIMC(Vec Vn, Vec Vd) {
990 return false;
991 }
992
993 // Data Processing - FP and SIMD - SHA
994 virtual bool SHA1C(Vec Vm, Vec Vn, Vec Vd) {
995 return false;
996 }
997 virtual bool SHA1P(Vec Vm, Vec Vn, Vec Vd) {
998 return false;
999 }
1000 virtual bool SHA1M(Vec Vm, Vec Vn, Vec Vd) {
1001 return false;
1002 }
1003 virtual bool SHA1SU0(Vec Vm, Vec Vn, Vec Vd) {
1004 return false;
1005 }
1006 virtual bool SHA256H(Vec Vm, Vec Vn, Vec Vd) {
1007 return false;
1008 }
1009 virtual bool SHA256H2(Vec Vm, Vec Vn, Vec Vd) {
1010 return false;
1011 }
1012 virtual bool SHA256SU1(Vec Vm, Vec Vn, Vec Vd) {
1013 return false;
1014 }
1015 virtual bool SHA1H(Vec Vn, Vec Vd) {
1016 return false;
1017 }
1018 virtual bool SHA1SU1(Vec Vn, Vec Vd) {
1019 return false;
1020 }
1021 virtual bool SHA256SU0(Vec Vn, Vec Vd) {
1022 return false;
1023 }
1024
1025 // Data Processing - FP and SIMD - Scalar copy
1026 virtual bool DUP_elt_1(Imm<5> imm5, Vec Vn, Vec Vd) {
1027 return false;
1028 }
1029
1030 // Data Processing - FP and SIMD - Scalar three
1031 virtual bool FMULX_vec_1(Vec Vm, Vec Vn, Vec Vd) {
1032 return false;
1033 }
1034 virtual bool FMULX_vec_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
1035 return false;
1036 }
1037 virtual bool FCMEQ_reg_1(Vec Vm, Vec Vn, Vec Vd) {
1038 return false;
1039 }
1040 virtual bool FCMEQ_reg_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
1041 return false;
1042 }
1043 virtual bool FRECPS_1(Vec Vm, Vec Vn, Vec Vd) {
1044 return false;
1045 }
1046 virtual bool FRECPS_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
1047 return false;
1048 }
1049 virtual bool FRSQRTS_1(Vec Vm, Vec Vn, Vec Vd) {
1050 return false;
1051 }
1052 virtual bool FRSQRTS_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
1053 return false;
1054 }
1055 virtual bool FCMGE_reg_1(Vec Vm, Vec Vn, Vec Vd) {
1056 return false;
1057 }
1058 virtual bool FCMGE_reg_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
1059 return false;
1060 }
1061 virtual bool FACGE_1(Vec Vm, Vec Vn, Vec Vd) {
1062 return false;
1063 }
1064 virtual bool FACGE_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
1065 return false;
1066 }
1067 virtual bool FABD_1(Vec Vm, Vec Vn, Vec Vd) {
1068 return false;
1069 }
1070 virtual bool FABD_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
1071 return false;
1072 }
1073 virtual bool FCMGT_reg_1(Vec Vm, Vec Vn, Vec Vd) {
1074 return false;
1075 }
1076 virtual bool FCMGT_reg_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
1077 return false;
1078 }
1079 virtual bool FACGT_1(Vec Vm, Vec Vn, Vec Vd) {
1080 return false;
1081 }
1082 virtual bool FACGT_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
1083 return false;
1084 }
1085
1086 // Data Processing - FP and SIMD - Two register misc FP16
1087 virtual bool FCVTNS_1(Vec Vn, Vec Vd) {
1088 return false;
1089 }
1090 virtual bool FCVTMS_1(Vec Vn, Vec Vd) {
1091 return false;
1092 }
1093 virtual bool FCVTAS_1(Vec Vn, Vec Vd) {
1094 return false;
1095 }
1096 virtual bool SCVTF_int_1(Vec Vn, Vec Vd) {
1097 return false;
1098 }
1099 virtual bool FCMGT_zero_1(Vec Vn, Vec Vd) {
1100 return false;
1101 }
1102 virtual bool FCMEQ_zero_1(Vec Vn, Vec Vd) {
1103 return false;
1104 }
1105 virtual bool FCMLT_1(Vec Vn, Vec Vd) {
1106 return false;
1107 }
1108 virtual bool FCVTPS_1(Vec Vn, Vec Vd) {
1109 return false;
1110 }
1111 virtual bool FCVTZS_int_1(Vec Vn, Vec Vd) {
1112 return false;
1113 }
1114 virtual bool FRECPE_1(Vec Vn, Vec Vd) {
1115 return false;
1116 }
1117 virtual bool FRECPX_1(Vec Vn, Vec Vd) {
1118 return false;
1119 }
1120 virtual bool FCVTNU_1(Vec Vn, Vec Vd) {
1121 return false;
1122 }
1123 virtual bool FCVTMU_1(Vec Vn, Vec Vd) {
1124 return false;
1125 }
1126 virtual bool FCVTAU_1(Vec Vn, Vec Vd) {
1127 return false;
1128 }
1129 virtual bool UCVTF_int_1(Vec Vn, Vec Vd) {
1130 return false;
1131 }
1132 virtual bool FCMGE_zero_1(Vec Vn, Vec Vd) {
1133 return false;
1134 }
1135 virtual bool FCMLE_1(Vec Vn, Vec Vd) {
1136 return false;
1137 }
1138 virtual bool FCVTPU_1(Vec Vn, Vec Vd) {
1139 return false;
1140 }
1141 virtual bool FCVTZU_int_1(Vec Vn, Vec Vd) {
1142 return false;
1143 }
1144 virtual bool FRSQRTE_1(Vec Vn, Vec Vd) {
1145 return false;
1146 }
1147
1148 // Data Processing - FP and SIMD - Two register misc
1149 virtual bool FCVTNS_2(bool sz, Vec Vn, Vec Vd) {
1150 return false;
1151 }
1152 virtual bool FCVTMS_2(bool sz, Vec Vn, Vec Vd) {
1153 return false;
1154 }
1155 virtual bool FCVTAS_2(bool sz, Vec Vn, Vec Vd) {
1156 return false;
1157 }
1158 virtual bool SCVTF_int_2(bool sz, Vec Vn, Vec Vd) {
1159 return false;
1160 }
1161 virtual bool FCMGT_zero_2(bool sz, Vec Vn, Vec Vd) {
1162 return false;
1163 }
1164 virtual bool FCMEQ_zero_2(bool sz, Vec Vn, Vec Vd) {
1165 return false;
1166 }
1167 virtual bool FCMLT_2(bool sz, Vec Vn, Vec Vd) {
1168 return false;
1169 }
1170 virtual bool FCVTPS_2(bool sz, Vec Vn, Vec Vd) {
1171 return false;
1172 }
1173 virtual bool FCVTZS_int_2(bool sz, Vec Vn, Vec Vd) {
1174 return false;
1175 }
1176 virtual bool FRECPE_2(bool sz, Vec Vn, Vec Vd) {
1177 return false;
1178 }
1179 virtual bool FRECPX_2(bool sz, Vec Vn, Vec Vd) {
1180 return false;
1181 }
1182 virtual bool FCVTNU_2(bool sz, Vec Vn, Vec Vd) {
1183 return false;
1184 }
1185 virtual bool FCVTMU_2(bool sz, Vec Vn, Vec Vd) {
1186 return false;
1187 }
1188 virtual bool FCVTAU_2(bool sz, Vec Vn, Vec Vd) {
1189 return false;
1190 }
1191 virtual bool UCVTF_int_2(bool sz, Vec Vn, Vec Vd) {
1192 return false;
1193 }
1194 virtual bool FCMGE_zero_2(bool sz, Vec Vn, Vec Vd) {
1195 return false;
1196 }
1197 virtual bool FCMLE_2(bool sz, Vec Vn, Vec Vd) {
1198 return false;
1199 }
1200 virtual bool FCVTPU_2(bool sz, Vec Vn, Vec Vd) {
1201 return false;
1202 }
1203 virtual bool FCVTZU_int_2(bool sz, Vec Vn, Vec Vd) {
1204 return false;
1205 }
1206 virtual bool FRSQRTE_2(bool sz, Vec Vn, Vec Vd) {
1207 return false;
1208 }
1209
1210 // Data Processing - FP and SIMD - Scalar two register misc FP16
1211 virtual bool FCVTNS_3(bool Q, Vec Vn, Vec Vd) {
1212 return false;
1213 }
1214 virtual bool FCVTMS_3(bool Q, Vec Vn, Vec Vd) {
1215 return false;
1216 }
1217 virtual bool FCVTAS_3(bool Q, Vec Vn, Vec Vd) {
1218 return false;
1219 }
1220 virtual bool SCVTF_int_3(bool Q, Vec Vn, Vec Vd) {
1221 return false;
1222 }
1223 virtual bool FCMGT_zero_3(bool Q, Vec Vn, Vec Vd) {
1224 return false;
1225 }
1226 virtual bool FCMEQ_zero_3(bool Q, Vec Vn, Vec Vd) {
1227 return false;
1228 }
1229 virtual bool FCMLT_3(bool Q, Vec Vn, Vec Vd) {
1230 return false;
1231 }
1232 virtual bool FCVTPS_3(bool Q, Vec Vn, Vec Vd) {
1233 return false;
1234 }
1235 virtual bool FCVTZS_int_3(bool Q, Vec Vn, Vec Vd) {
1236 return false;
1237 }
1238 virtual bool FRECPE_3(bool Q, Vec Vn, Vec Vd) {
1239 return false;
1240 }
1241 virtual bool FCVTNU_3(bool Q, Vec Vn, Vec Vd) {
1242 return false;
1243 }
1244 virtual bool FCVTMU_3(bool Q, Vec Vn, Vec Vd) {
1245 return false;
1246 }
1247 virtual bool FCVTAU_3(bool Q, Vec Vn, Vec Vd) {
1248 return false;
1249 }
1250 virtual bool UCVTF_int_3(bool Q, Vec Vn, Vec Vd) {
1251 return false;
1252 }
1253 virtual bool FCMGE_zero_3(bool Q, Vec Vn, Vec Vd) {
1254 return false;
1255 }
1256 virtual bool FCMLE_3(bool Q, Vec Vn, Vec Vd) {
1257 return false;
1258 }
1259 virtual bool FCVTPU_3(bool Q, Vec Vn, Vec Vd) {
1260 return false;
1261 }
1262 virtual bool FCVTZU_int_3(bool Q, Vec Vn, Vec Vd) {
1263 return false;
1264 }
1265 virtual bool FRSQRTE_3(bool Q, Vec Vn, Vec Vd) {
1266 return false;
1267 }
1268
1269 // Data Processing - FP and SIMD - Scalar two register misc
1270 virtual bool FCVTNS_4(bool Q, bool sz, Vec Vn, Vec Vd) {
1271 return false;
1272 }
1273 virtual bool FCVTMS_4(bool Q, bool sz, Vec Vn, Vec Vd) {
1274 return false;
1275 }
1276 virtual bool FCVTAS_4(bool Q, bool sz, Vec Vn, Vec Vd) {
1277 return false;
1278 }
1279 virtual bool SCVTF_int_4(bool Q, bool sz, Vec Vn, Vec Vd) {
1280 return false;
1281 }
1282 virtual bool FCMGT_zero_4(bool Q, bool sz, Vec Vn, Vec Vd) {
1283 return false;
1284 }
1285 virtual bool FCMEQ_zero_4(bool Q, bool sz, Vec Vn, Vec Vd) {
1286 return false;
1287 }
1288 virtual bool FCMLT_4(bool Q, bool sz, Vec Vn, Vec Vd) {
1289 return false;
1290 }
1291 virtual bool FCVTPS_4(bool Q, bool sz, Vec Vn, Vec Vd) {
1292 return false;
1293 }
1294 virtual bool FCVTZS_int_4(bool Q, bool sz, Vec Vn, Vec Vd) {
1295 return false;
1296 }
1297 virtual bool FRECPE_4(bool Q, bool sz, Vec Vn, Vec Vd) {
1298 return false;
1299 }
1300 virtual bool FCVTNU_4(bool Q, bool sz, Vec Vn, Vec Vd) {
1301 return false;
1302 }
1303 virtual bool FCVTMU_4(bool Q, bool sz, Vec Vn, Vec Vd) {
1304 return false;
1305 }
1306 virtual bool FCVTAU_4(bool Q, bool sz, Vec Vn, Vec Vd) {
1307 return false;
1308 }
1309 virtual bool UCVTF_int_4(bool Q, bool sz, Vec Vn, Vec Vd) {
1310 return false;
1311 }
1312 virtual bool FCMGE_zero_4(bool Q, bool sz, Vec Vn, Vec Vd) {
1313 return false;
1314 }
1315 virtual bool FCMLE_4(bool Q, bool sz, Vec Vn, Vec Vd) {
1316 return false;
1317 }
1318 virtual bool FCVTPU_4(bool Q, bool sz, Vec Vn, Vec Vd) {
1319 return false;
1320 }
1321 virtual bool FCVTZU_int_4(bool Q, bool sz, Vec Vn, Vec Vd) {
1322 return false;
1323 }
1324 virtual bool FRSQRTE_4(bool Q, bool sz, Vec Vn, Vec Vd) {
1325 return false;
1326 }
1327
1328 // Data Processing - FP and SIMD - Scalar three same extra
1329 virtual bool SQRDMLAH_vec_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1330 return false;
1331 }
1332 virtual bool SQRDMLAH_vec_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1333 return false;
1334 }
1335 virtual bool SQRDMLSH_vec_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1336 return false;
1337 }
1338 virtual bool SQRDMLSH_vec_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1339 return false;
1340 }
1341
1342 // Data Processing - FP and SIMD - Scalar two-register misc
1343 virtual bool SUQADD_1(Imm<2> size, Vec Vn, Vec Vd) {
1344 return false;
1345 }
1346 virtual bool SQABS_1(Imm<2> size, Vec Vn, Vec Vd) {
1347 return false;
1348 }
1349 virtual bool CMGT_zero_1(Imm<2> size, Vec Vn, Vec Vd) {
1350 return false;
1351 }
1352 virtual bool CMEQ_zero_1(Imm<2> size, Vec Vn, Vec Vd) {
1353 return false;
1354 }
1355 virtual bool CMLT_1(Imm<2> size, Vec Vn, Vec Vd) {
1356 return false;
1357 }
1358 virtual bool ABS_1(Imm<2> size, Vec Vn, Vec Vd) {
1359 return false;
1360 }
1361 virtual bool SQXTN_1(Imm<2> size, Vec Vn, Vec Vd) {
1362 return false;
1363 }
1364 virtual bool USQADD_1(Imm<2> size, Vec Vn, Vec Vd) {
1365 return false;
1366 }
1367 virtual bool SQNEG_1(Imm<2> size, Vec Vn, Vec Vd) {
1368 return false;
1369 }
1370 virtual bool CMGE_zero_1(Imm<2> size, Vec Vn, Vec Vd) {
1371 return false;
1372 }
1373 virtual bool CMLE_1(Imm<2> size, Vec Vn, Vec Vd) {
1374 return false;
1375 }
1376 virtual bool NEG_1(Imm<2> size, Vec Vn, Vec Vd) {
1377 return false;
1378 }
1379 virtual bool SQXTUN_1(Imm<2> size, Vec Vn, Vec Vd) {
1380 return false;
1381 }
1382 virtual bool UQXTN_1(Imm<2> size, Vec Vn, Vec Vd) {
1383 return false;
1384 }
1385 virtual bool FCVTXN_1(bool sz, Vec Vn, Vec Vd) {
1386 return false;
1387 }
1388
1389 // Data Processing - FP and SIMD - SIMD Scalar pairwise
1390 virtual bool ADDP_pair(Imm<2> size, Vec Vn, Vec Vd) {
1391 return false;
1392 }
1393 virtual bool FMAXNMP_pair_1(Vec Vn, Vec Vd) {
1394 return false;
1395 }
1396 virtual bool FMAXNMP_pair_2(bool sz, Vec Vn, Vec Vd) {
1397 return false;
1398 }
1399 virtual bool FADDP_pair_1(Vec Vn, Vec Vd) {
1400 return false;
1401 }
1402 virtual bool FADDP_pair_2(bool sz, Vec Vn, Vec Vd) {
1403 return false;
1404 }
1405 virtual bool FMAXP_pair_1(Vec Vn, Vec Vd) {
1406 return false;
1407 }
1408 virtual bool FMAXP_pair_2(bool sz, Vec Vn, Vec Vd) {
1409 return false;
1410 }
1411 virtual bool FMINNMP_pair_1(Vec Vn, Vec Vd) {
1412 return false;
1413 }
1414 virtual bool FMINNMP_pair_2(bool sz, Vec Vn, Vec Vd) {
1415 return false;
1416 }
1417 virtual bool FMINP_pair_1(Vec Vn, Vec Vd) {
1418 return false;
1419 }
1420 virtual bool FMINP_pair_2(bool sz, Vec Vn, Vec Vd) {
1421 return false;
1422 }
1423
1424 // Data Processing - FP and SIMD - SIMD Scalar three different
1425 virtual bool SQDMLAL_vec_1(Imm<2> size, Reg Rm, Reg Rn, Vec Vd) {
1426 return false;
1427 }
1428 virtual bool SQDMLSL_vec_1(Imm<2> size, Reg Rm, Reg Rn, Vec Vd) {
1429 return false;
1430 }
1431 virtual bool SQDMULL_vec_1(Imm<2> size, Reg Rm, Reg Rn, Vec Vd) {
1432 return false;
1433 }
1434
1435 // Data Processing - FP and SIMD - SIMD Scalar three same
1436 virtual bool SQADD_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1437 return false;
1438 }
1439 virtual bool SQSUB_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1440 return false;
1441 }
1442 virtual bool CMGT_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1443 return false;
1444 }
1445 virtual bool CMGE_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1446 return false;
1447 }
1448 virtual bool SSHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1449 return false;
1450 }
1451 virtual bool SQSHL_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1452 return false;
1453 }
1454 virtual bool SRSHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1455 return false;
1456 }
1457 virtual bool SQRSHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1458 return false;
1459 }
1460 virtual bool ADD_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1461 return false;
1462 }
1463 virtual bool CMTST_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1464 return false;
1465 }
1466 virtual bool SQDMULH_vec_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1467 return false;
1468 }
1469 virtual bool UQADD_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1470 return false;
1471 }
1472 virtual bool UQSUB_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1473 return false;
1474 }
1475 virtual bool CMHI_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1476 return false;
1477 }
1478 virtual bool CMHS_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1479 return false;
1480 }
1481 virtual bool USHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1482 return false;
1483 }
1484 virtual bool UQSHL_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1485 return false;
1486 }
1487 virtual bool URSHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1488 return false;
1489 }
1490 virtual bool UQRSHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1491 return false;
1492 }
1493 virtual bool SUB_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1494 return false;
1495 }
1496 virtual bool CMEQ_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1497 return false;
1498 }
1499 virtual bool SQRDMULH_vec_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1500 return false;
1501 }
1502
1503 // Data Processing - FP and SIMD - SIMD Scalar shift by immediate
1504 virtual bool SSHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1505 return false;
1506 }
1507 virtual bool SSRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1508 return false;
1509 }
1510 virtual bool SRSHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1511 return false;
1512 }
1513 virtual bool SRSRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1514 return false;
1515 }
1516 virtual bool SHL_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1517 return false;
1518 }
1519 virtual bool SQSHL_imm_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1520 return false;
1521 }
1522 virtual bool SQSHRN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1523 return false;
1524 }
1525 virtual bool SQRSHRN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1526 return false;
1527 }
1528 virtual bool SCVTF_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1529 return false;
1530 }
1531 virtual bool FCVTZS_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1532 return false;
1533 }
1534 virtual bool USHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1535 return false;
1536 }
1537 virtual bool USRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1538 return false;
1539 }
1540 virtual bool URSHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1541 return false;
1542 }
1543 virtual bool URSRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1544 return false;
1545 }
1546 virtual bool SRI_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1547 return false;
1548 }
1549 virtual bool SLI_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1550 return false;
1551 }
1552 virtual bool SQSHLU_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1553 return false;
1554 }
1555 virtual bool UQSHL_imm_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1556 return false;
1557 }
1558 virtual bool SQSHRUN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1559 return false;
1560 }
1561 virtual bool SQRSHRUN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1562 return false;
1563 }
1564 virtual bool UQSHRN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1565 return false;
1566 }
1567 virtual bool UQRSHRN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1568 return false;
1569 }
1570 virtual bool UCVTF_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1571 return false;
1572 }
1573 virtual bool FCVTZU_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
1574 return false;
1575 }
1576
1577 // Data Processing - FP and SIMD - SIMD Scalar x indexed element
1578 virtual bool SQDMLAL_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
1579 Vec Vd) {
1580 return false;
1581 }
1582 virtual bool SQDMLSL_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
1583 Vec Vd) {
1584 return false;
1585 }
1586 virtual bool SQDMULL_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
1587 Vec Vd) {
1588 return false;
1589 }
1590 virtual bool SQDMULH_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
1591 Vec Vd) {
1592 return false;
1593 }
1594 virtual bool SQRDMULH_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
1595 Vec Vd) {
1596 return false;
1597 }
1598 virtual bool FMLA_elt_1(Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) {
1599 return false;
1600 }
1601 virtual bool FMLA_elt_2(bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) {
1602 return false;
1603 }
1604 virtual bool FMLS_elt_1(Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) {
1605 return false;
1606 }
1607 virtual bool FMLS_elt_2(bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) {
1608 return false;
1609 }
1610 virtual bool FMUL_elt_1(Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) {
1611 return false;
1612 }
1613 virtual bool FMUL_elt_2(bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) {
1614 return false;
1615 }
1616 virtual bool SQRDMLAH_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
1617 Vec Vd) {
1618 return false;
1619 }
1620 virtual bool SQRDMLSH_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
1621 Vec Vd) {
1622 return false;
1623 }
1624 virtual bool FMULX_elt_1(Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) {
1625 return false;
1626 }
1627 virtual bool FMULX_elt_2(bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) {
1628 return false;
1629 }
1630
1631 // Data Processing - FP and SIMD - SIMD Table Lookup
1632 virtual bool TBL(bool Q, Vec Vm, Imm<2> len, size_t Vn, Vec Vd) {
1633 return false;
1634 }
1635 virtual bool TBX(bool Q, Vec Vm, Imm<2> len, size_t Vn, Vec Vd) {
1636 return false;
1637 }
1638
1639 // Data Processing - FP and SIMD - SIMD Permute
1640 virtual bool UZP1(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1641 return false;
1642 }
1643 virtual bool TRN1(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1644 return false;
1645 }
1646 virtual bool ZIP1(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1647 return false;
1648 }
1649 virtual bool UZP2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1650 return false;
1651 }
1652 virtual bool TRN2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1653 return false;
1654 }
1655 virtual bool ZIP2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1656 return false;
1657 }
1658
1659 // Data Processing - FP and SIMD - SIMD Extract
1660 virtual bool EXT(bool Q, Vec Vm, Imm<4> imm4, Vec Vn, Vec Vd) {
1661 return false;
1662 }
1663
1664 // Data Processing - FP and SIMD - SIMD Copy
1665 virtual bool DUP_elt_2(bool Q, Imm<5> imm5, Vec Vn, Vec Vd) {
1666 return false;
1667 }
1668 virtual bool DUP_gen(bool Q, Imm<5> imm5, Reg Rn, Vec Vd) {
1669 return false;
1670 }
1671 virtual bool SMOV(bool Q, Imm<5> imm5, Vec Vn, Reg Rd) {
1672 return false;
1673 }
1674 virtual bool UMOV(bool Q, Imm<5> imm5, Vec Vn, Reg Rd) {
1675 return false;
1676 }
1677 virtual bool INS_gen(Imm<5> imm5, Reg Rn, Vec Vd) {
1678 return false;
1679 }
1680 virtual bool INS_elt(Imm<5> imm5, Imm<4> imm4, Vec Vn, Vec Vd) {
1681 return false;
1682 }
1683
1684 // Data Processing - FP and SIMD - SIMD Three same
1685 virtual bool FMULX_vec_3(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1686 return false;
1687 }
1688 virtual bool FCMEQ_reg_3(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1689 return false;
1690 }
1691 virtual bool FRECPS_3(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1692 return false;
1693 }
1694 virtual bool FRSQRTS_3(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1695 return false;
1696 }
1697 virtual bool FCMGE_reg_3(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1698 return false;
1699 }
1700 virtual bool FACGE_3(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1701 return false;
1702 }
1703 virtual bool FABD_3(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1704 return false;
1705 }
1706 virtual bool FCMGT_reg_3(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1707 return false;
1708 }
1709 virtual bool FACGT_3(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1710 return false;
1711 }
1712 virtual bool FMAXNM_1(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1713 return false;
1714 }
1715 virtual bool FMLA_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1716 return false;
1717 }
1718 virtual bool FADD_1(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1719 return false;
1720 }
1721 virtual bool FMAX_1(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1722 return false;
1723 }
1724 virtual bool FMINNM_1(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1725 return false;
1726 }
1727 virtual bool FMLS_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1728 return false;
1729 }
1730 virtual bool FSUB_1(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1731 return false;
1732 }
1733 virtual bool FMIN_1(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1734 return false;
1735 }
1736 virtual bool FMAXNMP_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1737 return false;
1738 }
1739 virtual bool FADDP_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1740 return false;
1741 }
1742 virtual bool FMUL_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1743 return false;
1744 }
1745 virtual bool FMAXP_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1746 return false;
1747 }
1748 virtual bool FDIV_1(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1749 return false;
1750 }
1751 virtual bool FMINNMP_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1752 return false;
1753 }
1754 virtual bool FMINP_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd) {
1755 return false;
1756 }
1757
1758 // Data Processing - FP and SIMD - SIMD Three same extra
1759 virtual bool SDOT_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1760 return false;
1761 }
1762 virtual bool UDOT_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1763 return false;
1764 }
1765 virtual bool FCMLA_vec(bool Q, Imm<2> size, Vec Vm, Imm<2> rot, Vec Vn, Vec Vd) {
1766 return false;
1767 }
1768 virtual bool FCADD_vec(bool Q, Imm<2> size, Vec Vm, Imm<1> rot, Vec Vn, Vec Vd) {
1769 return false;
1770 }
1771
1772 // Data Processing - FP and SIMD - SIMD Two register misc
1773 virtual bool REV64_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1774 return false;
1775 }
1776 virtual bool REV16_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1777 return false;
1778 }
1779 virtual bool SADDLP(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1780 return false;
1781 }
1782 virtual bool CLS_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1783 return false;
1784 }
1785 virtual bool CNT(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1786 return false;
1787 }
1788 virtual bool SADALP(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1789 return false;
1790 }
1791 virtual bool XTN(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1792 return false;
1793 }
1794 virtual bool FCVTN(bool Q, bool sz, Vec Vn, Vec Vd) {
1795 return false;
1796 }
1797 virtual bool FCVTL(bool Q, bool sz, Vec Vn, Vec Vd) {
1798 return false;
1799 }
1800 virtual bool URECPE(bool Q, bool sz, Vec Vn, Vec Vd) {
1801 return false;
1802 }
1803 virtual bool REV32_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1804 return false;
1805 }
1806 virtual bool UADDLP(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1807 return false;
1808 }
1809 virtual bool CLZ_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1810 return false;
1811 }
1812 virtual bool UADALP(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1813 return false;
1814 }
1815 virtual bool SHLL(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1816 return false;
1817 }
1818 virtual bool NOT(bool Q, Vec Vn, Vec Vd) {
1819 return false;
1820 }
1821 virtual bool RBIT_asimd(bool Q, Vec Vn, Vec Vd) {
1822 return false;
1823 }
1824 virtual bool URSQRTE(bool Q, bool sz, Vec Vn, Vec Vd) {
1825 return false;
1826 }
1827 virtual bool SUQADD_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1828 return false;
1829 }
1830 virtual bool SQABS_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1831 return false;
1832 }
1833 virtual bool CMGT_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1834 return false;
1835 }
1836 virtual bool CMEQ_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1837 return false;
1838 }
1839 virtual bool CMLT_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1840 return false;
1841 }
1842 virtual bool ABS_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1843 return false;
1844 }
1845 virtual bool SQXTN_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1846 return false;
1847 }
1848 virtual bool USQADD_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1849 return false;
1850 }
1851 virtual bool SQNEG_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1852 return false;
1853 }
1854 virtual bool CMGE_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1855 return false;
1856 }
1857 virtual bool CMLE_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1858 return false;
1859 }
1860 virtual bool NEG_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1861 return false;
1862 }
1863 virtual bool SQXTUN_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1864 return false;
1865 }
1866 virtual bool UQXTN_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1867 return false;
1868 }
1869 virtual bool FCVTXN_2(bool Q, bool sz, Vec Vn, Vec Vd) {
1870 return false;
1871 }
1872 virtual bool FRINTN_1(bool Q, Vec Vn, Vec Vd) {
1873 return false;
1874 }
1875 virtual bool FRINTN_2(bool Q, bool sz, Vec Vn, Vec Vd) {
1876 return false;
1877 }
1878 virtual bool FRINTM_1(bool Q, Vec Vn, Vec Vd) {
1879 return false;
1880 }
1881 virtual bool FRINTM_2(bool Q, bool sz, Vec Vn, Vec Vd) {
1882 return false;
1883 }
1884 virtual bool FABS_1(bool Q, Vec Vn, Vec Vd) {
1885 return false;
1886 }
1887 virtual bool FABS_2(bool Q, bool sz, Vec Vn, Vec Vd) {
1888 return false;
1889 }
1890 virtual bool FRINTP_1(bool Q, Vec Vn, Vec Vd) {
1891 return false;
1892 }
1893 virtual bool FRINTP_2(bool Q, bool sz, Vec Vn, Vec Vd) {
1894 return false;
1895 }
1896 virtual bool FRINTZ_1(bool Q, Vec Vn, Vec Vd) {
1897 return false;
1898 }
1899 virtual bool FRINTZ_2(bool Q, bool sz, Vec Vn, Vec Vd) {
1900 return false;
1901 }
1902 virtual bool FRINTA_1(bool Q, Vec Vn, Vec Vd) {
1903 return false;
1904 }
1905 virtual bool FRINTA_2(bool Q, bool sz, Vec Vn, Vec Vd) {
1906 return false;
1907 }
1908 virtual bool FRINTX_1(bool Q, Vec Vn, Vec Vd) {
1909 return false;
1910 }
1911 virtual bool FRINTX_2(bool Q, bool sz, Vec Vn, Vec Vd) {
1912 return false;
1913 }
1914 virtual bool FNEG_1(bool Q, Vec Vn, Vec Vd) {
1915 return false;
1916 }
1917 virtual bool FNEG_2(bool Q, bool sz, Vec Vn, Vec Vd) {
1918 return false;
1919 }
1920 virtual bool FRINTI_1(bool Q, Vec Vn, Vec Vd) {
1921 return false;
1922 }
1923 virtual bool FRINTI_2(bool Q, bool sz, Vec Vn, Vec Vd) {
1924 return false;
1925 }
1926 virtual bool FSQRT_1(bool Q, Vec Vn, Vec Vd) {
1927 return false;
1928 }
1929 virtual bool FSQRT_2(bool Q, bool sz, Vec Vn, Vec Vd) {
1930 return false;
1931 }
1932 virtual bool FRINT32X_1(bool Q, bool sz, Vec Vn, Vec Vd) {
1933 return false;
1934 }
1935 virtual bool FRINT64X_1(bool Q, bool sz, Vec Vn, Vec Vd) {
1936 return false;
1937 }
1938 virtual bool FRINT32Z_1(bool Q, bool sz, Vec Vn, Vec Vd) {
1939 return false;
1940 }
1941 virtual bool FRINT64Z_1(bool Q, bool sz, Vec Vn, Vec Vd) {
1942 return false;
1943 }
1944
1945 // Data Processing - FP and SIMD - SIMD across lanes
1946 virtual bool SADDLV(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1947 return false;
1948 }
1949 virtual bool SMAXV(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1950 return false;
1951 }
1952 virtual bool SMINV(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1953 return false;
1954 }
1955 virtual bool ADDV(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1956 return false;
1957 }
1958 virtual bool FMAXNMV_1(bool Q, Vec Vn, Vec Vd) {
1959 return false;
1960 }
1961 virtual bool FMAXNMV_2(bool Q, bool sz, Vec Vn, Vec Vd) {
1962 return false;
1963 }
1964 virtual bool FMAXV_1(bool Q, Vec Vn, Vec Vd) {
1965 return false;
1966 }
1967 virtual bool FMAXV_2(bool Q, bool sz, Vec Vn, Vec Vd) {
1968 return false;
1969 }
1970 virtual bool FMINNMV_1(bool Q, Vec Vn, Vec Vd) {
1971 return false;
1972 }
1973 virtual bool FMINNMV_2(bool Q, bool sz, Vec Vn, Vec Vd) {
1974 return false;
1975 }
1976 virtual bool FMINV_1(bool Q, Vec Vn, Vec Vd) {
1977 return false;
1978 }
1979 virtual bool FMINV_2(bool Q, bool sz, Vec Vn, Vec Vd) {
1980 return false;
1981 }
1982 virtual bool UADDLV(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1983 return false;
1984 }
1985 virtual bool UMAXV(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1986 return false;
1987 }
1988 virtual bool UMINV(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
1989 return false;
1990 }
1991
1992 // Data Processing - FP and SIMD - SIMD three different
1993 virtual bool SADDL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1994 return false;
1995 }
1996 virtual bool SADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
1997 return false;
1998 }
1999 virtual bool SSUBL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2000 return false;
2001 }
2002 virtual bool SSUBW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2003 return false;
2004 }
2005 virtual bool ADDHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2006 return false;
2007 }
2008 virtual bool SABAL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2009 return false;
2010 }
2011 virtual bool SUBHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2012 return false;
2013 }
2014 virtual bool SABDL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2015 return false;
2016 }
2017 virtual bool SMLAL_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2018 return false;
2019 }
2020 virtual bool SMLSL_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2021 return false;
2022 }
2023 virtual bool SMULL_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2024 return false;
2025 }
2026 virtual bool PMULL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2027 return false;
2028 }
2029 virtual bool UADDL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2030 return false;
2031 }
2032 virtual bool UADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2033 return false;
2034 }
2035 virtual bool USUBL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2036 return false;
2037 }
2038 virtual bool USUBW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2039 return false;
2040 }
2041 virtual bool RADDHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2042 return false;
2043 }
2044 virtual bool UABAL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2045 return false;
2046 }
2047 virtual bool RSUBHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2048 return false;
2049 }
2050 virtual bool UABDL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2051 return false;
2052 }
2053 virtual bool UMLAL_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2054 return false;
2055 }
2056 virtual bool UMLSL_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2057 return false;
2058 }
2059 virtual bool UMULL_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2060 return false;
2061 }
2062 virtual bool SQDMLAL_vec_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2063 return false;
2064 }
2065 virtual bool SQDMLSL_vec_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2066 return false;
2067 }
2068 virtual bool SQDMULL_vec_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2069 return false;
2070 }
2071
2072 // Data Processing - FP and SIMD - SIMD three same
2073 virtual bool SHADD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2074 return false;
2075 }
2076 virtual bool SRHADD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2077 return false;
2078 }
2079 virtual bool SHSUB(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2080 return false;
2081 }
2082 virtual bool SMAX(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2083 return false;
2084 }
2085 virtual bool SMIN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2086 return false;
2087 }
2088 virtual bool SABD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2089 return false;
2090 }
2091 virtual bool SABA(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2092 return false;
2093 }
2094 virtual bool MLA_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2095 return false;
2096 }
2097 virtual bool MUL_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2098 return false;
2099 }
2100 virtual bool SMAXP(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2101 return false;
2102 }
2103 virtual bool SMINP(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2104 return false;
2105 }
2106 virtual bool ADDP_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2107 return false;
2108 }
2109 virtual bool FMLAL_vec_1(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2110 return false;
2111 }
2112 virtual bool FMLAL_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2113 return false;
2114 }
2115 virtual bool AND_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) {
2116 return false;
2117 }
2118 virtual bool BIC_asimd_reg(bool Q, Vec Vm, Vec Vn, Vec Vd) {
2119 return false;
2120 }
2121 virtual bool FMLSL_vec_1(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2122 return false;
2123 }
2124 virtual bool FMLSL_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2125 return false;
2126 }
2127 virtual bool ORR_asimd_reg(bool Q, Vec Vm, Vec Vn, Vec Vd) {
2128 return false;
2129 }
2130 virtual bool ORN_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) {
2131 return false;
2132 }
2133 virtual bool UHADD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2134 return false;
2135 }
2136 virtual bool URHADD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2137 return false;
2138 }
2139 virtual bool UHSUB(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2140 return false;
2141 }
2142 virtual bool UMAX(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2143 return false;
2144 }
2145 virtual bool UMIN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2146 return false;
2147 }
2148 virtual bool UABD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2149 return false;
2150 }
2151 virtual bool UABA(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2152 return false;
2153 }
2154 virtual bool MLS_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2155 return false;
2156 }
2157 virtual bool PMUL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2158 return false;
2159 }
2160 virtual bool UMAXP(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2161 return false;
2162 }
2163 virtual bool UMINP(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2164 return false;
2165 }
2166 virtual bool EOR_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) {
2167 return false;
2168 }
2169 virtual bool BSL(bool Q, Vec Vm, Vec Vn, Vec Vd) {
2170 return false;
2171 }
2172 virtual bool BIT(bool Q, Vec Vm, Vec Vn, Vec Vd) {
2173 return false;
2174 }
2175 virtual bool BIF(bool Q, Vec Vm, Vec Vn, Vec Vd) {
2176 return false;
2177 }
2178 virtual bool FMAXNM_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2179 return false;
2180 }
2181 virtual bool FMLA_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2182 return false;
2183 }
2184 virtual bool FADD_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2185 return false;
2186 }
2187 virtual bool FMAX_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2188 return false;
2189 }
2190 virtual bool FMINNM_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2191 return false;
2192 }
2193 virtual bool FMLS_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2194 return false;
2195 }
2196 virtual bool FSUB_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2197 return false;
2198 }
2199 virtual bool FMIN_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2200 return false;
2201 }
2202 virtual bool FMAXNMP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2203 return false;
2204 }
2205 virtual bool FADDP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2206 return false;
2207 }
2208 virtual bool FMUL_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2209 return false;
2210 }
2211 virtual bool FMAXP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2212 return false;
2213 }
2214 virtual bool FDIV_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2215 return false;
2216 }
2217 virtual bool FMINNMP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2218 return false;
2219 }
2220 virtual bool FMINP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2221 return false;
2222 }
2223 virtual bool FMULX_vec_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2224 return false;
2225 }
2226 virtual bool FCMEQ_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2227 return false;
2228 }
2229 virtual bool FRECPS_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2230 return false;
2231 }
2232 virtual bool FRSQRTS_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2233 return false;
2234 }
2235 virtual bool FCMGE_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2236 return false;
2237 }
2238 virtual bool FACGE_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2239 return false;
2240 }
2241 virtual bool FABD_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2242 return false;
2243 }
2244 virtual bool FCMGT_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2245 return false;
2246 }
2247 virtual bool FACGT_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
2248 return false;
2249 }
2250 virtual bool SQADD_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2251 return false;
2252 }
2253 virtual bool SQSUB_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2254 return false;
2255 }
2256 virtual bool CMGT_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2257 return false;
2258 }
2259 virtual bool CMGE_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2260 return false;
2261 }
2262 virtual bool SSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2263 return false;
2264 }
2265 virtual bool SQSHL_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2266 return false;
2267 }
2268 virtual bool SRSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2269 return false;
2270 }
2271 virtual bool SQRSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2272 return false;
2273 }
2274 virtual bool ADD_vector(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2275 return false;
2276 }
2277 virtual bool CMTST_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2278 return false;
2279 }
2280 virtual bool SQDMULH_vec_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2281 return false;
2282 }
2283 virtual bool UQADD_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2284 return false;
2285 }
2286 virtual bool UQSUB_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2287 return false;
2288 }
2289 virtual bool CMHI_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2290 return false;
2291 }
2292 virtual bool CMHS_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2293 return false;
2294 }
2295 virtual bool USHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2296 return false;
2297 }
2298 virtual bool UQSHL_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2299 return false;
2300 }
2301 virtual bool URSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2302 return false;
2303 }
2304 virtual bool UQRSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2305 return false;
2306 }
2307 virtual bool SUB_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2308 return false;
2309 }
2310 virtual bool CMEQ_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2311 return false;
2312 }
2313 virtual bool SQRDMULH_vec_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
2314 return false;
2315 }
2316
2317 // Data Processing - FP and SIMD - SIMD modified immediate
2318 virtual bool MOVI(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<4> cmode, Imm<1> d,
2319 Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Vec Vd) {
2320 return false;
2321 }
2322 virtual bool FMOV_2(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f,
2323 Imm<1> g, Imm<1> h, Vec Vd) {
2324 return false;
2325 }
2326 virtual bool FMOV_3(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f,
2327 Imm<1> g, Imm<1> h, Vec Vd) {
2328 return false;
2329 }
2330
2331 // Data Processing - FP and SIMD - SIMD Shift by immediate
2332 virtual bool SSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2333 return false;
2334 }
2335 virtual bool SSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2336 return false;
2337 }
2338 virtual bool SRSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2339 return false;
2340 }
2341 virtual bool SRSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2342 return false;
2343 }
2344 virtual bool SHL_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2345 return false;
2346 }
2347 virtual bool SQSHL_imm_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2348 return false;
2349 }
2350 virtual bool SHRN(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2351 return false;
2352 }
2353 virtual bool RSHRN(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2354 return false;
2355 }
2356 virtual bool SQSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2357 return false;
2358 }
2359 virtual bool SQRSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2360 return false;
2361 }
2362 virtual bool SSHLL(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2363 return false;
2364 }
2365 virtual bool SCVTF_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2366 return false;
2367 }
2368 virtual bool FCVTZS_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2369 return false;
2370 }
2371 virtual bool USHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2372 return false;
2373 }
2374 virtual bool USRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2375 return false;
2376 }
2377 virtual bool URSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2378 return false;
2379 }
2380 virtual bool URSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2381 return false;
2382 }
2383 virtual bool SRI_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2384 return false;
2385 }
2386 virtual bool SLI_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2387 return false;
2388 }
2389 virtual bool SQSHLU_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2390 return false;
2391 }
2392 virtual bool UQSHL_imm_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2393 return false;
2394 }
2395 virtual bool SQSHRUN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2396 return false;
2397 }
2398 virtual bool SQRSHRUN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2399 return false;
2400 }
2401 virtual bool UQSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2402 return false;
2403 }
2404 virtual bool UQRSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2405 return false;
2406 }
2407 virtual bool USHLL(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2408 return false;
2409 }
2410 virtual bool UCVTF_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2411 return false;
2412 }
2413 virtual bool FCVTZU_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
2414 return false;
2415 }
2416
2417 // Data Processing - FP and SIMD - SIMD vector x indexed element
2418 virtual bool SMLAL_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
2419 Vec Vd) {
2420 return false;
2421 }
2422 virtual bool SQDMLAL_elt_2(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H,
2423 Vec Vn, Vec Vd) {
2424 return false;
2425 }
2426 virtual bool SMLSL_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
2427 Vec Vd) {
2428 return false;
2429 }
2430 virtual bool SQDMLSL_elt_2(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H,
2431 Vec Vn, Vec Vd) {
2432 return false;
2433 }
2434 virtual bool MUL_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
2435 Vec Vd) {
2436 return false;
2437 }
2438 virtual bool SMULL_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vm, Imm<1> H, Vec Vn,
2439 Vec Vd) {
2440 return false;
2441 }
2442 virtual bool SQDMULL_elt_2(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H,
2443 Vec Vn, Vec Vd) {
2444 return false;
2445 }
2446 virtual bool SQDMULH_elt_2(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H,
2447 Vec Vn, Vec Vd) {
2448 return false;
2449 }
2450 virtual bool SQRDMULH_elt_2(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H,
2451 Vec Vn, Vec Vd) {
2452 return false;
2453 }
2454 virtual bool SDOT_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
2455 Vec Vd) {
2456 return false;
2457 }
2458 virtual bool FMLA_elt_3(bool Q, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) {
2459 return false;
2460 }
2461 virtual bool FMLA_elt_4(bool Q, bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
2462 Vec Vd) {
2463 return false;
2464 }
2465 virtual bool FMLS_elt_3(bool Q, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) {
2466 return false;
2467 }
2468 virtual bool FMLS_elt_4(bool Q, bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
2469 Vec Vd) {
2470 return false;
2471 }
2472 virtual bool FMUL_elt_3(bool Q, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) {
2473 return false;
2474 }
2475 virtual bool FMUL_elt_4(bool Q, bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
2476 Vec Vd) {
2477 return false;
2478 }
2479 virtual bool FMLAL_elt_1(bool Q, bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
2480 Vec Vd) {
2481 return false;
2482 }
2483 virtual bool FMLAL_elt_2(bool Q, bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
2484 Vec Vd) {
2485 return false;
2486 }
2487 virtual bool FMLSL_elt_1(bool Q, bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
2488 Vec Vd) {
2489 return false;
2490 }
2491 virtual bool FMLSL_elt_2(bool Q, bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
2492 Vec Vd) {
2493 return false;
2494 }
2495 virtual bool MLA_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
2496 Vec Vd) {
2497 return false;
2498 }
2499 virtual bool UMLAL_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
2500 Vec Vd) {
2501 return false;
2502 }
2503 virtual bool MLS_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
2504 Vec Vd) {
2505 return false;
2506 }
2507 virtual bool UMLSL_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
2508 Vec Vd) {
2509 return false;
2510 }
2511 virtual bool UMULL_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
2512 Vec Vd) {
2513 return false;
2514 }
2515 virtual bool SQRDMLAH_elt_2(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H,
2516 Vec Vn, Vec Vd) {
2517 return false;
2518 }
2519 virtual bool UDOT_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
2520 Vec Vd) {
2521 return false;
2522 }
2523 virtual bool SQRDMLSH_elt_2(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H,
2524 Vec Vn, Vec Vd) {
2525 return false;
2526 }
2527 virtual bool FMULX_elt_3(bool Q, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) {
2528 return false;
2529 }
2530 virtual bool FMULX_elt_4(bool Q, bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn,
2531 Vec Vd) {
2532 return false;
2533 }
2534 virtual bool FCMLA_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<2> rot,
2535 Imm<1> H, Vec Vn, Vec Vd) {
2536 return false;
2537 }
2538
2539 // Data Processing - FP and SIMD - Cryptographic three register
2540 virtual bool SM3TT1A(Vec Vm, Imm<2> imm2, Vec Vn, Vec Vd) {
2541 return false;
2542 }
2543 virtual bool SM3TT1B(Vec Vm, Imm<2> imm2, Vec Vn, Vec Vd) {
2544 return false;
2545 }
2546 virtual bool SM3TT2A(Vec Vm, Imm<2> imm2, Vec Vn, Vec Vd) {
2547 return false;
2548 }
2549 virtual bool SM3TT2B(Vec Vm, Imm<2> imm2, Vec Vn, Vec Vd) {
2550 return false;
2551 }
2552
2553 // Data Processing - FP and SIMD - SHA512 three register
2554 virtual bool SHA512H(Vec Vm, Vec Vn, Vec Vd) {
2555 return false;
2556 }
2557 virtual bool SHA512H2(Vec Vm, Vec Vn, Vec Vd) {
2558 return false;
2559 }
2560 virtual bool SHA512SU1(Vec Vm, Vec Vn, Vec Vd) {
2561 return false;
2562 }
2563 virtual bool RAX1(Vec Vm, Vec Vn, Vec Vd) {
2564 return false;
2565 }
2566 virtual bool XAR(Vec Vm, Imm<6> imm6, Vec Vn, Vec Vd) {
2567 return false;
2568 }
2569 virtual bool SM3PARTW1(Vec Vm, Vec Vn, Vec Vd) {
2570 return false;
2571 }
2572 virtual bool SM3PARTW2(Vec Vm, Vec Vn, Vec Vd) {
2573 return false;
2574 }
2575 virtual bool SM4EKEY(Vec Vm, Vec Vn, Vec Vd) {
2576 return false;
2577 }
2578
2579 // Data Processing - FP and SIMD - Cryptographic four register
2580 virtual bool EOR3(Vec Vm, Vec Va, Vec Vn, Vec Vd) {
2581 return false;
2582 }
2583 virtual bool BCAX(Vec Vm, Vec Va, Vec Vn, Vec Vd) {
2584 return false;
2585 }
2586 virtual bool SM3SS1(Vec Vm, Vec Va, Vec Vn, Vec Vd) {
2587 return false;
2588 }
2589
2590 // Data Processing - FP and SIMD - SHA512 two register
2591 virtual bool SHA512SU0(Vec Vn, Vec Vd) {
2592 return false;
2593 }
2594 virtual bool SM4E(Vec Vn, Vec Vd) {
2595 return false;
2596 }
2597
2598 // Data Processing - FP and SIMD - Conversion between floating point and fixed point
2599 virtual bool SCVTF_float_fix(bool sf, Imm<2> type, Imm<6> scale, Reg Rn, Vec Vd) {
2600 return false;
2601 }
2602 virtual bool UCVTF_float_fix(bool sf, Imm<2> type, Imm<6> scale, Reg Rn, Vec Vd) {
2603 return false;
2604 }
2605 virtual bool FCVTZS_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec Vn, Reg Rd) {
2606 return false;
2607 }
2608 virtual bool FCVTZU_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec Vn, Reg Rd) {
2609 return false;
2610 }
2611
2612 // Data Processing - FP and SIMD - Conversion between floating point and integer
2613 virtual bool FCVTNS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
2614 return false;
2615 }
2616 virtual bool FCVTNU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
2617 return false;
2618 }
2619 virtual bool SCVTF_float_int(bool sf, Imm<2> type, Reg Rn, Vec Vd) {
2620 return false;
2621 }
2622 virtual bool UCVTF_float_int(bool sf, Imm<2> type, Reg Rn, Vec Vd) {
2623 return false;
2624 }
2625 virtual bool FCVTAS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
2626 return false;
2627 }
2628 virtual bool FCVTAU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
2629 return false;
2630 }
2631 virtual bool FMOV_float_gen(bool sf, Imm<2> type, Imm<1> rmode_0, Imm<1> opc_0, size_t n,
2632 size_t d) {
2633 return false;
2634 }
2635 virtual bool FCVTPS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
2636 return false;
2637 }
2638 virtual bool FCVTPU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
2639 return false;
2640 }
2641 virtual bool FCVTMS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
2642 return false;
2643 }
2644 virtual bool FCVTMU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
2645 return false;
2646 }
2647 virtual bool FCVTZS_float_int(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
2648 return false;
2649 }
2650 virtual bool FCVTZU_float_int(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
2651 return false;
2652 }
2653 virtual bool FJCVTZS(Vec Vn, Reg Rd) {
2654 return false;
2655 }
2656
2657 // Data Processing - FP and SIMD - Floating point data processing
2658 virtual bool FMOV_float(Imm<2> type, Vec Vn, Vec Vd) {
2659 return false;
2660 }
2661 virtual bool FABS_float(Imm<2> type, Vec Vn, Vec Vd) {
2662 return false;
2663 }
2664 virtual bool FNEG_float(Imm<2> type, Vec Vn, Vec Vd) {
2665 return false;
2666 }
2667 virtual bool FSQRT_float(Imm<2> type, Vec Vn, Vec Vd) {
2668 return false;
2669 }
2670 virtual bool FCVT_float(Imm<2> type, Imm<2> opc, Vec Vn, Vec Vd) {
2671 return false;
2672 }
2673 virtual bool FRINTN_float(Imm<2> type, Vec Vn, Vec Vd) {
2674 return false;
2675 }
2676 virtual bool FRINTP_float(Imm<2> type, Vec Vn, Vec Vd) {
2677 return false;
2678 }
2679 virtual bool FRINTM_float(Imm<2> type, Vec Vn, Vec Vd) {
2680 return false;
2681 }
2682 virtual bool FRINTZ_float(Imm<2> type, Vec Vn, Vec Vd) {
2683 return false;
2684 }
2685 virtual bool FRINTA_float(Imm<2> type, Vec Vn, Vec Vd) {
2686 return false;
2687 }
2688 virtual bool FRINTX_float(Imm<2> type, Vec Vn, Vec Vd) {
2689 return false;
2690 }
2691 virtual bool FRINTI_float(Imm<2> type, Vec Vn, Vec Vd) {
2692 return false;
2693 }
2694 virtual bool FRINT32X_float(Imm<2> type, Vec Vn, Vec Vd) {
2695 return false;
2696 }
2697 virtual bool FRINT64X_float(Imm<2> type, Vec Vn, Vec Vd) {
2698 return false;
2699 }
2700 virtual bool FRINT32Z_float(Imm<2> type, Vec Vn, Vec Vd) {
2701 return false;
2702 }
2703 virtual bool FRINT64Z_float(Imm<2> type, Vec Vn, Vec Vd) {
2704 return false;
2705 }
2706
2707 // Data Processing - FP and SIMD - Floating point compare
2708 virtual bool FCMP_float(Imm<2> type, Vec Vm, Vec Vn, bool cmp_with_zero) {
2709 return false;
2710 }
2711 virtual bool FCMPE_float(Imm<2> type, Vec Vm, Vec Vn, bool cmp_with_zero) {
2712 return false;
2713 }
2714
2715 // Data Processing - FP and SIMD - Floating point immediate
2716 virtual bool FMOV_float_imm(Imm<2> type, Imm<8> imm8, Vec Vd) {
2717 return false;
2718 }
2719
2720 // Data Processing - FP and SIMD - Floating point conditional compare
2721 virtual bool FCCMP_float(Imm<2> type, Vec Vm, Cond cond, Vec Vn, Imm<4> nzcv) {
2722 return false;
2723 }
2724 virtual bool FCCMPE_float(Imm<2> type, Vec Vm, Cond cond, Vec Vn, Imm<4> nzcv) {
2725 return false;
2726 }
2727
2728 // Data Processing - FP and SIMD - Floating point data processing two register
2729 virtual bool FMUL_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) {
2730 return false;
2731 }
2732 virtual bool FDIV_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) {
2733 return false;
2734 }
2735 virtual bool FADD_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) {
2736 return false;
2737 }
2738 virtual bool FSUB_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) {
2739 return false;
2740 }
2741 virtual bool FMAX_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) {
2742 return false;
2743 }
2744 virtual bool FMIN_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) {
2745 return false;
2746 }
2747 virtual bool FMAXNM_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) {
2748 return false;
2749 }
2750 virtual bool FMINNM_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) {
2751 return false;
2752 }
2753 virtual bool FNMUL_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) {
2754 return false;
2755 }
2756
2757 // Data Processing - FP and SIMD - Floating point conditional select
2758 virtual bool FCSEL_float(Imm<2> type, Vec Vm, Cond cond, Vec Vn, Vec Vd) {
2759 return false;
2760 }
2761
2762 // Data Processing - FP and SIMD - Floating point data processing three register
2763 virtual bool FMADD_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) {
2764 return false;
2765 }
2766 virtual bool FMSUB_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) {
2767 return false;
2768 }
2769 virtual bool FNMADD_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) {
2770 return false;
2771 }
2772 virtual bool FNMSUB_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) {
2773 return false;
2774 }
2775};
2776
2777} // namespace Core
HIC SVNT DRACONES