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Diffstat (limited to 'src/video_core/shader_cache.cpp')
-rw-r--r--src/video_core/shader_cache.cpp12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/video_core/shader_cache.cpp b/src/video_core/shader_cache.cpp
index f53066579..d9482371b 100644
--- a/src/video_core/shader_cache.cpp
+++ b/src/video_core/shader_cache.cpp
@@ -43,14 +43,14 @@ bool ShaderCache::RefreshStages(std::array<u64, 6>& unique_hashes) {
43 } 43 }
44 dirty[VideoCommon::Dirty::Shaders] = false; 44 dirty[VideoCommon::Dirty::Shaders] = false;
45 45
46 const GPUVAddr base_addr{maxwell3d->regs.code_address.CodeAddress()}; 46 const GPUVAddr base_addr{maxwell3d->regs.program_region.Address()};
47 for (size_t index = 0; index < Tegra::Engines::Maxwell3D::Regs::MaxShaderProgram; ++index) { 47 for (size_t index = 0; index < Tegra::Engines::Maxwell3D::Regs::MaxShaderProgram; ++index) {
48 if (!maxwell3d->regs.IsShaderConfigEnabled(index)) { 48 if (!maxwell3d->regs.IsShaderConfigEnabled(index)) {
49 unique_hashes[index] = 0; 49 unique_hashes[index] = 0;
50 continue; 50 continue;
51 } 51 }
52 const auto& shader_config{maxwell3d->regs.shader_config[index]}; 52 const auto& shader_config{maxwell3d->regs.pipelines[index]};
53 const auto program{static_cast<Tegra::Engines::Maxwell3D::Regs::ShaderProgram>(index)}; 53 const auto program{static_cast<Tegra::Engines::Maxwell3D::Regs::ShaderType>(index)};
54 const GPUVAddr shader_addr{base_addr + shader_config.offset}; 54 const GPUVAddr shader_addr{base_addr + shader_config.offset};
55 const std::optional<VAddr> cpu_shader_addr{gpu_memory->GpuToCpuAddress(shader_addr)}; 55 const std::optional<VAddr> cpu_shader_addr{gpu_memory->GpuToCpuAddress(shader_addr)};
56 if (!cpu_shader_addr) { 56 if (!cpu_shader_addr) {
@@ -90,14 +90,14 @@ const ShaderInfo* ShaderCache::ComputeShader() {
90void ShaderCache::GetGraphicsEnvironments(GraphicsEnvironments& result, 90void ShaderCache::GetGraphicsEnvironments(GraphicsEnvironments& result,
91 const std::array<u64, NUM_PROGRAMS>& unique_hashes) { 91 const std::array<u64, NUM_PROGRAMS>& unique_hashes) {
92 size_t env_index{}; 92 size_t env_index{};
93 const GPUVAddr base_addr{maxwell3d->regs.code_address.CodeAddress()}; 93 const GPUVAddr base_addr{maxwell3d->regs.program_region.Address()};
94 for (size_t index = 0; index < NUM_PROGRAMS; ++index) { 94 for (size_t index = 0; index < NUM_PROGRAMS; ++index) {
95 if (unique_hashes[index] == 0) { 95 if (unique_hashes[index] == 0) {
96 continue; 96 continue;
97 } 97 }
98 const auto program{static_cast<Tegra::Engines::Maxwell3D::Regs::ShaderProgram>(index)}; 98 const auto program{static_cast<Tegra::Engines::Maxwell3D::Regs::ShaderType>(index)};
99 auto& env{result.envs[index]}; 99 auto& env{result.envs[index]};
100 const u32 start_address{maxwell3d->regs.shader_config[index].offset}; 100 const u32 start_address{maxwell3d->regs.pipelines[index].offset};
101 env = GraphicsEnvironment{*maxwell3d, *gpu_memory, program, base_addr, start_address}; 101 env = GraphicsEnvironment{*maxwell3d, *gpu_memory, program, base_addr, start_address};
102 env.SetCachedSize(shader_infos[index]->size_bytes); 102 env.SetCachedSize(shader_infos[index]->size_bytes);
103 result.env_ptrs[env_index++] = &env; 103 result.env_ptrs[env_index++] = &env;