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1// SPDX-FileCopyrightText: 2022 yuzu Emulator Project
2// SPDX-License-Identifier: GPL-3.0-or-later
3
4#pragma once
5
6#include <array>
7#include <cstddef>
8#include <vector>
9#include "common/bit_field.h"
10#include "common/common_funcs.h"
11#include "common/common_types.h"
12#include "video_core/engines/engine_interface.h"
13
14namespace Core {
15class System;
16}
17
18namespace Tegra {
19class MemoryManager;
20class DmaPusher;
21
22enum class EngineID {
23 FERMI_TWOD_A = 0x902D, // 2D Engine
24 MAXWELL_B = 0xB197, // 3D Engine
25 KEPLER_COMPUTE_B = 0xB1C0,
26 KEPLER_INLINE_TO_MEMORY_B = 0xA140,
27 MAXWELL_DMA_COPY_A = 0xB0B5,
28};
29
30namespace Control {
31struct ChannelState;
32}
33} // namespace Tegra
34
35namespace VideoCore {
36class RasterizerInterface;
37}
38
39namespace Tegra::Engines {
40
41class Puller final {
42public:
43 struct MethodCall {
44 u32 method{};
45 u32 argument{};
46 u32 subchannel{};
47 u32 method_count{};
48
49 explicit MethodCall(u32 method_, u32 argument_, u32 subchannel_ = 0, u32 method_count_ = 0)
50 : method(method_), argument(argument_), subchannel(subchannel_),
51 method_count(method_count_) {}
52
53 [[nodiscard]] bool IsLastCall() const {
54 return method_count <= 1;
55 }
56 };
57
58 enum class FenceOperation : u32 {
59 Acquire = 0,
60 Increment = 1,
61 };
62
63 union FenceAction {
64 u32 raw;
65 BitField<0, 1, FenceOperation> op;
66 BitField<8, 24, u32> syncpoint_id;
67 };
68
69 explicit Puller(GPU& gpu_, MemoryManager& memory_manager_, DmaPusher& dma_pusher,
70 Control::ChannelState& channel_state);
71 ~Puller();
72
73 void CallMethod(const MethodCall& method_call);
74
75 void CallMultiMethod(u32 method, u32 subchannel, const u32* base_start, u32 amount,
76 u32 methods_pending);
77
78 void BindRasterizer(VideoCore::RasterizerInterface* rasterizer);
79
80 void CallPullerMethod(const MethodCall& method_call);
81
82 void CallEngineMethod(const MethodCall& method_call);
83
84 void CallEngineMultiMethod(u32 method, u32 subchannel, const u32* base_start, u32 amount,
85 u32 methods_pending);
86
87private:
88 Tegra::GPU& gpu;
89
90 MemoryManager& memory_manager;
91 DmaPusher& dma_pusher;
92 Control::ChannelState& channel_state;
93 VideoCore::RasterizerInterface* rasterizer = nullptr;
94
95 static constexpr std::size_t NUM_REGS = 0x800;
96 struct Regs {
97 static constexpr size_t NUM_REGS = 0x40;
98
99 union {
100 struct {
101 INSERT_PADDING_WORDS_NOINIT(0x4);
102 struct {
103 u32 address_high;
104 u32 address_low;
105
106 [[nodiscard]] GPUVAddr SemaphoreAddress() const {
107 return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
108 address_low);
109 }
110 } semaphore_address;
111
112 u32 semaphore_sequence;
113 u32 semaphore_trigger;
114 INSERT_PADDING_WORDS_NOINIT(0xC);
115
116 // The pusher and the puller share the reference counter, the pusher only has read
117 // access
118 u32 reference_count;
119 INSERT_PADDING_WORDS_NOINIT(0x5);
120
121 u32 semaphore_acquire;
122 u32 semaphore_release;
123 u32 fence_value;
124 FenceAction fence_action;
125 INSERT_PADDING_WORDS_NOINIT(0xE2);
126
127 // Puller state
128 u32 acquire_mode;
129 u32 acquire_source;
130 u32 acquire_active;
131 u32 acquire_timeout;
132 u32 acquire_value;
133 };
134 std::array<u32, NUM_REGS> reg_array;
135 };
136 } regs{};
137
138 void ProcessBindMethod(const MethodCall& method_call);
139 void ProcessFenceActionMethod();
140 void ProcessSemaphoreAcquire();
141 void ProcessSemaphoreRelease();
142 void ProcessSemaphoreTriggerMethod();
143 [[nodiscard]] bool ExecuteMethodOnEngine(u32 method);
144
145 /// Mapping of command subchannels to their bound engine ids
146 std::array<EngineID, 8> bound_engines{};
147
148 enum class GpuSemaphoreOperation {
149 AcquireEqual = 0x1,
150 WriteLong = 0x2,
151 AcquireGequal = 0x4,
152 AcquireMask = 0x8,
153 };
154
155#define ASSERT_REG_POSITION(field_name, position) \
156 static_assert(offsetof(Regs, field_name) == position * 4, \
157 "Field " #field_name " has invalid position")
158
159 ASSERT_REG_POSITION(semaphore_address, 0x4);
160 ASSERT_REG_POSITION(semaphore_sequence, 0x6);
161 ASSERT_REG_POSITION(semaphore_trigger, 0x7);
162 ASSERT_REG_POSITION(reference_count, 0x14);
163 ASSERT_REG_POSITION(semaphore_acquire, 0x1A);
164 ASSERT_REG_POSITION(semaphore_release, 0x1B);
165 ASSERT_REG_POSITION(fence_value, 0x1C);
166 ASSERT_REG_POSITION(fence_action, 0x1D);
167
168 ASSERT_REG_POSITION(acquire_mode, 0x100);
169 ASSERT_REG_POSITION(acquire_source, 0x101);
170 ASSERT_REG_POSITION(acquire_active, 0x102);
171 ASSERT_REG_POSITION(acquire_timeout, 0x103);
172 ASSERT_REG_POSITION(acquire_value, 0x104);
173
174#undef ASSERT_REG_POSITION
175};
176
177} // namespace Tegra::Engines