5 files changed, 6 insertions, 6 deletions

diff --git a/src/shader_recompiler/backend/glsl/emit_glsl_integer.cpp b/src/shader_recompiler/backend/glsl/emit_glsl_integer.cpp
index 06599c1b0..49397c9b2 100644
--- a/src/shader_recompiler/backend/glsl/emit_glsl_integer.cpp
+++ b/src/shader_recompiler/backend/glsl/emit_glsl_integer.cpp
@@ -39,7 +39,7 @@ void EmitIAdd32(EmitContext& ctx, IR::Inst& inst, std::string_view a, std::strin
     // which may be overwritten by the result of the addition
     if (IR::Inst * overflow{inst.GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp)}) {
         // https://stackoverflow.com/questions/55468823/how-to-detect-integer-overflow-in-c
-        constexpr static u32 s32_max{static_cast<u32>(std::numeric_limits<s32>::max())};
+        constexpr u32 s32_max{static_cast<u32>(std::numeric_limits<s32>::max())};
         const auto sub_a{fmt::format("{}u-{}", s32_max, a)};
         const auto positive_result{fmt::format("int({})>int({})", b, sub_a)};
         const auto negative_result{fmt::format("int({})<int({})", b, sub_a)};
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index f6492dffd..960bdea6f 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -42,7 +42,7 @@ Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
     SetSignFlag(ctx, inst, result);
     if (IR::Inst * overflow{inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp)}) {
         // https://stackoverflow.com/questions/55468823/how-to-detect-integer-overflow-in-c
-        constexpr static u32 s32_max{static_cast<u32>(std::numeric_limits<s32>::max())};
+        constexpr u32 s32_max{static_cast<u32>(std::numeric_limits<s32>::max())};
         const Id is_positive{ctx.OpSGreaterThanEqual(ctx.U1, a, ctx.u32_zero_value)};
         const Id sub_a{ctx.OpISub(ctx.U32[1], ctx.Const(s32_max), a)};
 
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_conversion_floating_point.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_conversion_floating_point.cpp
index 15ad55a43..7f3dccc52 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_conversion_floating_point.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_conversion_floating_point.cpp
@@ -48,7 +48,7 @@ void F2F(TranslatorVisitor& v, u64 insn, const IR::F16F32F64& src_a, bool abs) {
         BitField<8, 2, FloatFormat> dst_size;
 
         [[nodiscard]] RoundingOp RoundingOperation() const {
-            constexpr static u64 rounding_mask = 0x0B;
+            constexpr u64 rounding_mask = 0x0B;
             return static_cast<RoundingOp>(rounding_op.Value() & rounding_mask);
         }
     } const f2f{insn};
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_conversion_integer.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_conversion_integer.cpp
index 429733187..85c18d942 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_conversion_integer.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_conversion_integer.cpp
@@ -176,11 +176,11 @@ void TranslateF2I(TranslatorVisitor& v, u64 insn, const IR::F16F32F64& src_a) {
         (f2i.src_format == SrcFormat::F64) != (f2i.dest_format == DestFormat::I64);
     if (special_nan_cases) {
         if (f2i.dest_format == DestFormat::I32) {
-            constexpr static u32 nan_value = 0x8000'0000U;
+            constexpr u32 nan_value = 0x8000'0000U;
             handled_special_case = true;
             result = IR::U32{v.ir.Select(v.ir.FPIsNan(op_a), v.ir.Imm32(nan_value), result)};
         } else if (f2i.dest_format == DestFormat::I64) {
-            constexpr static u64 nan_value = 0x8000'0000'0000'0000ULL;
+            constexpr u64 nan_value = 0x8000'0000'0000'0000ULL;
             handled_special_case = true;
             result = IR::U64{v.ir.Select(v.ir.FPIsNan(op_a), v.ir.Imm64(nan_value), result)};
         }
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_add_three_input.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_add_three_input.cpp
index 3c8ef62e2..3d9877359 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_add_three_input.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_add_three_input.cpp
@@ -19,7 +19,7 @@ enum class Half : u64 {
 };
 
 [[nodiscard]] IR::U32 IntegerHalf(IR::IREmitter& ir, const IR::U32& value, Half half) {
-    constexpr static bool is_signed{false};
+    constexpr bool is_signed{false};
     switch (half) {
     case Half::All:
         return value;