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-rw-r--r--src/shader_recompiler/frontend/ir/ir_emitter.cpp20
-rw-r--r--src/shader_recompiler/frontend/ir/ir_emitter.h5
-rw-r--r--src/shader_recompiler/frontend/ir/opcodes.inc5
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp110
4 files changed, 105 insertions, 35 deletions
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.cpp b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
index 246c3b9ef..ed1e0dd3b 100644
--- a/src/shader_recompiler/frontend/ir/ir_emitter.cpp
+++ b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
@@ -1628,6 +1628,26 @@ U32 IREmitter::SubgroupBallot(const U1& value) {
1628 return Inst<U32>(Opcode::SubgroupBallot, value); 1628 return Inst<U32>(Opcode::SubgroupBallot, value);
1629} 1629}
1630 1630
1631U32 IREmitter::SubgroupEqMask() {
1632 return Inst<U32>(Opcode::SubgroupEqMask);
1633}
1634
1635U32 IREmitter::SubgroupLtMask() {
1636 return Inst<U32>(Opcode::SubgroupLtMask);
1637}
1638
1639U32 IREmitter::SubgroupLeMask() {
1640 return Inst<U32>(Opcode::SubgroupLeMask);
1641}
1642
1643U32 IREmitter::SubgroupGtMask() {
1644 return Inst<U32>(Opcode::SubgroupGtMask);
1645}
1646
1647U32 IREmitter::SubgroupGeMask() {
1648 return Inst<U32>(Opcode::SubgroupGeMask);
1649}
1650
1631U32 IREmitter::ShuffleIndex(const IR::U32& value, const IR::U32& index, const IR::U32& clamp, 1651U32 IREmitter::ShuffleIndex(const IR::U32& value, const IR::U32& index, const IR::U32& clamp,
1632 const IR::U32& seg_mask) { 1652 const IR::U32& seg_mask) {
1633 return Inst<U32>(Opcode::ShuffleIndex, value, index, clamp, seg_mask); 1653 return Inst<U32>(Opcode::ShuffleIndex, value, index, clamp, seg_mask);
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.h b/src/shader_recompiler/frontend/ir/ir_emitter.h
index 1b00c548d..42756af43 100644
--- a/src/shader_recompiler/frontend/ir/ir_emitter.h
+++ b/src/shader_recompiler/frontend/ir/ir_emitter.h
@@ -281,6 +281,11 @@ public:
281 [[nodiscard]] U1 VoteAny(const U1& value); 281 [[nodiscard]] U1 VoteAny(const U1& value);
282 [[nodiscard]] U1 VoteEqual(const U1& value); 282 [[nodiscard]] U1 VoteEqual(const U1& value);
283 [[nodiscard]] U32 SubgroupBallot(const U1& value); 283 [[nodiscard]] U32 SubgroupBallot(const U1& value);
284 [[nodiscard]] U32 SubgroupEqMask();
285 [[nodiscard]] U32 SubgroupLtMask();
286 [[nodiscard]] U32 SubgroupLeMask();
287 [[nodiscard]] U32 SubgroupGtMask();
288 [[nodiscard]] U32 SubgroupGeMask();
284 [[nodiscard]] U32 ShuffleIndex(const IR::U32& value, const IR::U32& index, const IR::U32& clamp, 289 [[nodiscard]] U32 ShuffleIndex(const IR::U32& value, const IR::U32& index, const IR::U32& clamp,
285 const IR::U32& seg_mask); 290 const IR::U32& seg_mask);
286 [[nodiscard]] U32 ShuffleUp(const IR::U32& value, const IR::U32& index, const IR::U32& clamp, 291 [[nodiscard]] U32 ShuffleUp(const IR::U32& value, const IR::U32& index, const IR::U32& clamp,
diff --git a/src/shader_recompiler/frontend/ir/opcodes.inc b/src/shader_recompiler/frontend/ir/opcodes.inc
index dcd54bcf7..1697de965 100644
--- a/src/shader_recompiler/frontend/ir/opcodes.inc
+++ b/src/shader_recompiler/frontend/ir/opcodes.inc
@@ -417,6 +417,11 @@ OPCODE(VoteAll, U1, U1,
417OPCODE(VoteAny, U1, U1, ) 417OPCODE(VoteAny, U1, U1, )
418OPCODE(VoteEqual, U1, U1, ) 418OPCODE(VoteEqual, U1, U1, )
419OPCODE(SubgroupBallot, U32, U1, ) 419OPCODE(SubgroupBallot, U32, U1, )
420OPCODE(SubgroupEqMask, U32, )
421OPCODE(SubgroupLtMask, U32, )
422OPCODE(SubgroupLeMask, U32, )
423OPCODE(SubgroupGtMask, U32, )
424OPCODE(SubgroupGeMask, U32, )
420OPCODE(ShuffleIndex, U32, U32, U32, U32, U32, ) 425OPCODE(ShuffleIndex, U32, U32, U32, U32, U32, )
421OPCODE(ShuffleUp, U32, U32, U32, U32, U32, ) 426OPCODE(ShuffleUp, U32, U32, U32, U32, U32, )
422OPCODE(ShuffleDown, U32, U32, U32, U32, U32, ) 427OPCODE(ShuffleDown, U32, U32, U32, U32, U32, )
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp
index 7d9c42a83..be1f21e7b 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp
@@ -10,6 +10,7 @@ namespace Shader::Maxwell {
10namespace { 10namespace {
11enum class SpecialRegister : u64 { 11enum class SpecialRegister : u64 {
12 SR_LANEID = 0, 12 SR_LANEID = 0,
13 SR_CLOCK = 1,
13 SR_VIRTCFG = 2, 14 SR_VIRTCFG = 2,
14 SR_VIRTID = 3, 15 SR_VIRTID = 3,
15 SR_PM0 = 4, 16 SR_PM0 = 4,
@@ -20,6 +21,9 @@ enum class SpecialRegister : u64 {
20 SR_PM5 = 9, 21 SR_PM5 = 9,
21 SR_PM6 = 10, 22 SR_PM6 = 10,
22 SR_PM7 = 11, 23 SR_PM7 = 11,
24 SR12 = 12,
25 SR13 = 13,
26 SR14 = 14,
23 SR_ORDERING_TICKET = 15, 27 SR_ORDERING_TICKET = 15,
24 SR_PRIM_TYPE = 16, 28 SR_PRIM_TYPE = 16,
25 SR_INVOCATION_ID = 17, 29 SR_INVOCATION_ID = 17,
@@ -41,44 +45,70 @@ enum class SpecialRegister : u64 {
41 SR_TID_X = 33, 45 SR_TID_X = 33,
42 SR_TID_Y = 34, 46 SR_TID_Y = 34,
43 SR_TID_Z = 35, 47 SR_TID_Z = 35,
48 SR_CTA_PARAM = 36,
44 SR_CTAID_X = 37, 49 SR_CTAID_X = 37,
45 SR_CTAID_Y = 38, 50 SR_CTAID_Y = 38,
46 SR_CTAID_Z = 39, 51 SR_CTAID_Z = 39,
47 SR_NTID = 49, 52 SR_NTID = 40,
48 SR_CirQueueIncrMinusOne = 50, 53 SR_CirQueueIncrMinusOne = 41,
49 SR_NLATC = 51, 54 SR_NLATC = 42,
50 SR_SWINLO = 57, 55 SR43 = 43,
51 SR_SWINSZ = 58, 56 SR_SM_SPA_VERSION = 44,
52 SR_SMEMSZ = 59, 57 SR_MULTIPASSSHADERINFO = 45,
53 SR_SMEMBANKS = 60, 58 SR_LWINHI = 46,
54 SR_LWINLO = 61, 59 SR_SWINHI = 47,
55 SR_LWINSZ = 62, 60 SR_SWINLO = 48,
56 SR_LMEMLOSZ = 63, 61 SR_SWINSZ = 49,
57 SR_LMEMHIOFF = 64, 62 SR_SMEMSZ = 50,
58 SR_EQMASK = 65, 63 SR_SMEMBANKS = 51,
59 SR_LTMASK = 66, 64 SR_LWINLO = 52,
60 SR_LEMASK = 67, 65 SR_LWINSZ = 53,
61 SR_GTMASK = 68, 66 SR_LMEMLOSZ = 54,
62 SR_GEMASK = 69, 67 SR_LMEMHIOFF = 55,
63 SR_REGALLOC = 70, 68 SR_EQMASK = 56,
64 SR_GLOBALERRORSTATUS = 73, 69 SR_LTMASK = 57,
65 SR_WARPERRORSTATUS = 75, 70 SR_LEMASK = 58,
66 SR_PM_HI0 = 81, 71 SR_GTMASK = 59,
67 SR_PM_HI1 = 82, 72 SR_GEMASK = 60,
68 SR_PM_HI2 = 83, 73 SR_REGALLOC = 61,
69 SR_PM_HI3 = 84, 74 SR_BARRIERALLOC = 62,
70 SR_PM_HI4 = 85, 75 SR63 = 63,
71 SR_PM_HI5 = 86, 76 SR_GLOBALERRORSTATUS = 64,
72 SR_PM_HI6 = 87, 77 SR65 = 65,
73 SR_PM_HI7 = 88, 78 SR_WARPERRORSTATUS = 66,
74 SR_CLOCKLO = 89, 79 SR_WARPERRORSTATUSCLEAR = 67,
75 SR_CLOCKHI = 90, 80 SR68 = 68,
76 SR_GLOBALTIMERLO = 91, 81 SR69 = 69,
77 SR_GLOBALTIMERHI = 92, 82 SR70 = 70,
78 SR_HWTASKID = 105, 83 SR71 = 71,
79 SR_CIRCULARQUEUEENTRYINDEX = 106, 84 SR_PM_HI0 = 72,
80 SR_CIRCULARQUEUEENTRYADDRESSLOW = 107, 85 SR_PM_HI1 = 73,
81 SR_CIRCULARQUEUEENTRYADDRESSHIGH = 108, 86 SR_PM_HI2 = 74,
87 SR_PM_HI3 = 75,
88 SR_PM_HI4 = 76,
89 SR_PM_HI5 = 77,
90 SR_PM_HI6 = 78,
91 SR_PM_HI7 = 79,
92 SR_CLOCKLO = 80,
93 SR_CLOCKHI = 81,
94 SR_GLOBALTIMERLO = 82,
95 SR_GLOBALTIMERHI = 83,
96 SR84 = 84,
97 SR85 = 85,
98 SR86 = 86,
99 SR87 = 87,
100 SR88 = 88,
101 SR89 = 89,
102 SR90 = 90,
103 SR91 = 91,
104 SR92 = 92,
105 SR93 = 93,
106 SR94 = 94,
107 SR95 = 95,
108 SR_HWTASKID = 96,
109 SR_CIRCULARQUEUEENTRYINDEX = 97,
110 SR_CIRCULARQUEUEENTRYADDRESSLOW = 98,
111 SR_CIRCULARQUEUEENTRYADDRESSHIGH = 99,
82}; 112};
83 113
84[[nodiscard]] IR::U32 Read(IR::IREmitter& ir, SpecialRegister special_register) { 114[[nodiscard]] IR::U32 Read(IR::IREmitter& ir, SpecialRegister special_register) {
@@ -103,6 +133,16 @@ enum class SpecialRegister : u64 {
103 return ir.Imm32(Common::BitCast<u32>(1.0f)); 133 return ir.Imm32(Common::BitCast<u32>(1.0f));
104 case SpecialRegister::SR_LANEID: 134 case SpecialRegister::SR_LANEID:
105 return ir.LaneId(); 135 return ir.LaneId();
136 case SpecialRegister::SR_EQMASK:
137 return ir.SubgroupEqMask();
138 case SpecialRegister::SR_LTMASK:
139 return ir.SubgroupLtMask();
140 case SpecialRegister::SR_LEMASK:
141 return ir.SubgroupLeMask();
142 case SpecialRegister::SR_GTMASK:
143 return ir.SubgroupGtMask();
144 case SpecialRegister::SR_GEMASK:
145 return ir.SubgroupGeMask();
106 default: 146 default:
107 throw NotImplementedException("S2R special register {}", special_register); 147 throw NotImplementedException("S2R special register {}", special_register);
108 } 148 }
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