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-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/integer_add_three_input.cpp27
1 files changed, 13 insertions, 14 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_add_three_input.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_add_three_input.cpp
index 259a6e6ac..33e2a51ae 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_add_three_input.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_add_three_input.cpp
@@ -42,14 +42,10 @@ enum class Half : u64 {
42 } 42 }
43} 43}
44 44
45void IADD3(TranslatorVisitor& v, u64 insn, IR::U32 op_b, IR::U32 op_c) { 45void IADD3(TranslatorVisitor& v, u64 insn, IR::U32 op_a, IR::U32 op_b, IR::U32 op_c) {
46 union { 46 union {
47 u64 insn; 47 u64 insn;
48 BitField<0, 8, IR::Reg> dest_reg; 48 BitField<0, 8, IR::Reg> dest_reg;
49 BitField<8, 8, IR::Reg> src_a;
50 BitField<31, 2, Half> half_c;
51 BitField<33, 2, Half> half_b;
52 BitField<35, 2, Half> half_a;
53 BitField<37, 2, Shift> shift; 49 BitField<37, 2, Shift> shift;
54 BitField<47, 1, u64> cc; 50 BitField<47, 1, u64> cc;
55 BitField<48, 1, u64> x; 51 BitField<48, 1, u64> x;
@@ -58,11 +54,6 @@ void IADD3(TranslatorVisitor& v, u64 insn, IR::U32 op_b, IR::U32 op_c) {
58 BitField<51, 1, u64> neg_a; 54 BitField<51, 1, u64> neg_a;
59 } iadd3{insn}; 55 } iadd3{insn};
60 56
61 IR::U32 op_a{v.X(iadd3.src_a)};
62 op_a = IntegerHalf(v.ir, op_a, iadd3.half_a);
63 op_b = IntegerHalf(v.ir, op_b, iadd3.half_b);
64 op_c = IntegerHalf(v.ir, op_c, iadd3.half_c);
65
66 if (iadd3.neg_a != 0) { 57 if (iadd3.neg_a != 0) {
67 op_a = v.ir.INeg(op_a); 58 op_a = v.ir.INeg(op_a);
68 } 59 }
@@ -72,7 +63,6 @@ void IADD3(TranslatorVisitor& v, u64 insn, IR::U32 op_b, IR::U32 op_c) {
72 if (iadd3.neg_c != 0) { 63 if (iadd3.neg_c != 0) {
73 op_c = v.ir.INeg(op_c); 64 op_c = v.ir.INeg(op_c);
74 } 65 }
75
76 IR::U32 lhs_1{v.ir.IAdd(op_a, op_b)}; 66 IR::U32 lhs_1{v.ir.IAdd(op_a, op_b)};
77 if (iadd3.x != 0) { 67 if (iadd3.x != 0) {
78 const IR::U32 carry{v.ir.Select(v.ir.GetCFlag(), v.ir.Imm32(1), v.ir.Imm32(0))}; 68 const IR::U32 carry{v.ir.Select(v.ir.GetCFlag(), v.ir.Imm32(1), v.ir.Imm32(0))};
@@ -97,15 +87,24 @@ void IADD3(TranslatorVisitor& v, u64 insn, IR::U32 op_b, IR::U32 op_c) {
97} // Anonymous namespace 87} // Anonymous namespace
98 88
99void TranslatorVisitor::IADD3_reg(u64 insn) { 89void TranslatorVisitor::IADD3_reg(u64 insn) {
100 IADD3(*this, insn, GetReg20(insn), GetReg39(insn)); 90 union {
91 u64 insn;
92 BitField<35, 2, Half> half_a;
93 BitField<31, 2, Half> half_c;
94 BitField<33, 2, Half> half_b;
95 } iadd3{insn};
96 const auto op_a{IntegerHalf(ir, GetReg8(insn), iadd3.half_a)};
97 const auto op_b{IntegerHalf(ir, GetReg20(insn), iadd3.half_b)};
98 const auto op_c{IntegerHalf(ir, GetReg39(insn), iadd3.half_c)};
99 IADD3(*this, insn, op_a, op_b, op_c);
101} 100}
102 101
103void TranslatorVisitor::IADD3_cbuf(u64 insn) { 102void TranslatorVisitor::IADD3_cbuf(u64 insn) {
104 IADD3(*this, insn, GetCbuf(insn), GetReg39(insn)); 103 IADD3(*this, insn, GetReg8(insn), GetCbuf(insn), GetReg39(insn));
105} 104}
106 105
107void TranslatorVisitor::IADD3_imm(u64 insn) { 106void TranslatorVisitor::IADD3_imm(u64 insn) {
108 IADD3(*this, insn, GetImm20(insn), GetReg39(insn)); 107 IADD3(*this, insn, GetReg8(insn), GetImm20(insn), GetReg39(insn));
109} 108}
110 109
111} // namespace Shader::Maxwell 110} // namespace Shader::Maxwell