diff options
Diffstat (limited to 'src/shader_recompiler/frontend')
4 files changed, 7 insertions, 7 deletions
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.cpp b/src/shader_recompiler/frontend/ir/ir_emitter.cpp index 6c37af5e7..d2ac2acac 100644 --- a/src/shader_recompiler/frontend/ir/ir_emitter.cpp +++ b/src/shader_recompiler/frontend/ir/ir_emitter.cpp | |||
| @@ -270,7 +270,7 @@ static U1 GetFlowTest(IREmitter& ir, FlowTest flow_test) { | |||
| 270 | case FlowTest::RGT: | 270 | case FlowTest::RGT: |
| 271 | return ir.LogicalAnd(ir.LogicalNot(ir.GetSFlag()), ir.LogicalNot(ir.GetZFlag())); | 271 | return ir.LogicalAnd(ir.LogicalNot(ir.GetSFlag()), ir.LogicalNot(ir.GetZFlag())); |
| 272 | case FlowTest::FCSM_TR: | 272 | case FlowTest::FCSM_TR: |
| 273 | // LOG_WARNING(ShaderDecompiler, "FCSM_TR CC State (Stubbed)"); | 273 | LOG_WARNING(Shader, "(STUBBED) FCSM_TR"); |
| 274 | return ir.Imm1(false); | 274 | return ir.Imm1(false); |
| 275 | case FlowTest::CSM_TA: | 275 | case FlowTest::CSM_TA: |
| 276 | case FlowTest::CSM_TR: | 276 | case FlowTest::CSM_TR: |
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/internal_stage_buffer_entry_read.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/internal_stage_buffer_entry_read.cpp index edd6220a8..9b85f8059 100644 --- a/src/shader_recompiler/frontend/maxwell/translate/impl/internal_stage_buffer_entry_read.cpp +++ b/src/shader_recompiler/frontend/maxwell/translate/impl/internal_stage_buffer_entry_read.cpp | |||
| @@ -46,7 +46,7 @@ void TranslatorVisitor::ISBERD(u64 insn) { | |||
| 46 | if (isberd.shift != Shift::Default) { | 46 | if (isberd.shift != Shift::Default) { |
| 47 | throw NotImplementedException("Shift {}", isberd.shift.Value()); | 47 | throw NotImplementedException("Shift {}", isberd.shift.Value()); |
| 48 | } | 48 | } |
| 49 | // LOG_WARNING(..., "ISBERD is stubbed"); | 49 | LOG_WARNING(Shader, "(STUBBED) called"); |
| 50 | X(isberd.dest_reg, X(isberd.src_reg)); | 50 | X(isberd.dest_reg, X(isberd.src_reg)); |
| 51 | } | 51 | } |
| 52 | 52 | ||
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp index fe3cdfa96..20cb2674e 100644 --- a/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp +++ b/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp | |||
| @@ -118,7 +118,7 @@ enum class SpecialRegister : u64 { | |||
| 118 | case SpecialRegister::SR_THREAD_KILL: | 118 | case SpecialRegister::SR_THREAD_KILL: |
| 119 | return IR::U32{ir.Select(ir.IsHelperInvocation(), ir.Imm32(-1), ir.Imm32(0))}; | 119 | return IR::U32{ir.Select(ir.IsHelperInvocation(), ir.Imm32(-1), ir.Imm32(0))}; |
| 120 | case SpecialRegister::SR_INVOCATION_INFO: | 120 | case SpecialRegister::SR_INVOCATION_INFO: |
| 121 | // LOG_WARNING(..., "SR_INVOCATION_INFO is stubbed"); | 121 | LOG_WARNING(Shader, "(STUBBED) SR_INVOCATION_INFO"); |
| 122 | return ir.Imm32(0x00ff'0000); | 122 | return ir.Imm32(0x00ff'0000); |
| 123 | case SpecialRegister::SR_TID: { | 123 | case SpecialRegister::SR_TID: { |
| 124 | const IR::Value tid{ir.LocalInvocationId()}; | 124 | const IR::Value tid{ir.LocalInvocationId()}; |
| @@ -140,10 +140,10 @@ enum class SpecialRegister : u64 { | |||
| 140 | case SpecialRegister::SR_CTAID_Z: | 140 | case SpecialRegister::SR_CTAID_Z: |
| 141 | return ir.WorkgroupIdZ(); | 141 | return ir.WorkgroupIdZ(); |
| 142 | case SpecialRegister::SR_WSCALEFACTOR_XY: | 142 | case SpecialRegister::SR_WSCALEFACTOR_XY: |
| 143 | // LOG_WARNING(..., "SR_WSCALEFACTOR_XY is stubbed"); | 143 | LOG_WARNING(Shader, "(STUBBED) SR_WSCALEFACTOR_XY"); |
| 144 | return ir.Imm32(Common::BitCast<u32>(1.0f)); | 144 | return ir.Imm32(Common::BitCast<u32>(1.0f)); |
| 145 | case SpecialRegister::SR_WSCALEFACTOR_Z: | 145 | case SpecialRegister::SR_WSCALEFACTOR_Z: |
| 146 | // LOG_WARNING(..., "SR_WSCALEFACTOR_Z is stubbed"); | 146 | LOG_WARNING(Shader, "(STUBBED) SR_WSCALEFACTOR_Z"); |
| 147 | return ir.Imm32(Common::BitCast<u32>(1.0f)); | 147 | return ir.Imm32(Common::BitCast<u32>(1.0f)); |
| 148 | case SpecialRegister::SR_LANEID: | 148 | case SpecialRegister::SR_LANEID: |
| 149 | return ir.LaneId(); | 149 | return ir.LaneId(); |
| @@ -160,7 +160,7 @@ enum class SpecialRegister : u64 { | |||
| 160 | case SpecialRegister::SR_Y_DIRECTION: | 160 | case SpecialRegister::SR_Y_DIRECTION: |
| 161 | return ir.BitCast<IR::U32>(ir.YDirection()); | 161 | return ir.BitCast<IR::U32>(ir.YDirection()); |
| 162 | case SpecialRegister::SR_AFFINITY: | 162 | case SpecialRegister::SR_AFFINITY: |
| 163 | // LOG_WARNING(..., "SR_AFFINITY is stubbed"); | 163 | LOG_WARNING(Shader, "(STUBBED) SR_AFFINITY"); |
| 164 | return ir.Imm32(0); // This is the default value hardware returns. | 164 | return ir.Imm32(0); // This is the default value hardware returns. |
| 165 | default: | 165 | default: |
| 166 | throw NotImplementedException("S2R special register {}", special_register); | 166 | throw NotImplementedException("S2R special register {}", special_register); |
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/vote.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/vote.cpp index 0793611ff..7ce370f09 100644 --- a/src/shader_recompiler/frontend/maxwell/translate/impl/vote.cpp +++ b/src/shader_recompiler/frontend/maxwell/translate/impl/vote.cpp | |||
| @@ -48,7 +48,7 @@ void TranslatorVisitor::VOTE(u64 insn) { | |||
| 48 | } | 48 | } |
| 49 | 49 | ||
| 50 | void TranslatorVisitor::VOTE_vtg(u64) { | 50 | void TranslatorVisitor::VOTE_vtg(u64) { |
| 51 | // LOG_WARNING(ShaderDecompiler, "VOTE.VTG: Stubbed!"); | 51 | LOG_WARNING(Shader, "(STUBBED) called"); |
| 52 | } | 52 | } |
| 53 | 53 | ||
| 54 | } // namespace Shader::Maxwell | 54 | } // namespace Shader::Maxwell |