diff options
Diffstat (limited to 'src/shader_recompiler/frontend/maxwell')
| -rw-r--r-- | src/shader_recompiler/frontend/maxwell/translate/impl/integer_add_three_input.cpp | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_add_three_input.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_add_three_input.cpp index b50017536..040cfc10f 100644 --- a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_add_three_input.cpp +++ b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_add_three_input.cpp | |||
| @@ -36,8 +36,12 @@ enum class Half : u64 { | |||
| 36 | switch (shift) { | 36 | switch (shift) { |
| 37 | case Shift::None: | 37 | case Shift::None: |
| 38 | return value; | 38 | return value; |
| 39 | case Shift::Right: | 39 | case Shift::Right: { |
| 40 | return ir.ShiftRightLogical(value, ir.Imm32(16)); | 40 | // 33-bit RS IADD3 edge case |
| 41 | const IR::U1 edge_case{ir.GetCarryFromOp(value)}; | ||
| 42 | const IR::U32 shifted{ir.ShiftRightLogical(value, ir.Imm32(16))}; | ||
| 43 | return IR::U32{ir.Select(edge_case, ir.IAdd(shifted, ir.Imm32(0x10000)), shifted)}; | ||
| 44 | } | ||
| 41 | case Shift::Left: | 45 | case Shift::Left: |
| 42 | return ir.ShiftLeftLogical(value, ir.Imm32(16)); | 46 | return ir.ShiftLeftLogical(value, ir.Imm32(16)); |
| 43 | } | 47 | } |
| @@ -67,6 +71,10 @@ void IADD3(TranslatorVisitor& v, u64 insn, IR::U32 op_a, IR::U32 op_b, IR::U32 o | |||
| 67 | } | 71 | } |
| 68 | IR::U32 lhs_1{v.ir.IAdd(op_a, op_b)}; | 72 | IR::U32 lhs_1{v.ir.IAdd(op_a, op_b)}; |
| 69 | if (iadd3.x != 0) { | 73 | if (iadd3.x != 0) { |
| 74 | // TODO: How does RS behave when X is set? | ||
| 75 | if (shift == Shift::Right) { | ||
| 76 | throw NotImplementedException("IADD3 X+RS"); | ||
| 77 | } | ||
| 70 | const IR::U32 carry{v.ir.Select(v.ir.GetCFlag(), v.ir.Imm32(1), v.ir.Imm32(0))}; | 78 | const IR::U32 carry{v.ir.Select(v.ir.GetCFlag(), v.ir.Imm32(1), v.ir.Imm32(0))}; |
| 71 | lhs_1 = v.ir.IAdd(lhs_1, carry); | 79 | lhs_1 = v.ir.IAdd(lhs_1, carry); |
| 72 | } | 80 | } |