4 files changed, 8 insertions, 5 deletions

diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_swizzled_add.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_swizzled_add.cpp
index ef4ffa54b..f00e20023 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_swizzled_add.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_swizzled_add.cpp
@@ -19,7 +19,7 @@ void TranslatorVisitor::FSWZADD(u64 insn) {
     } const fswzadd{insn};
 
     if (fswzadd.ndv != 0) {
-        throw NotImplementedException("FSWZADD NDV");
+        LOG_WARNING(Shader, "(STUBBED) FSWZADD - NDV mode");
     }
 
     const IR::F32 src_a{GetFloatReg8(insn)};
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp
index 82aec3b73..1ddfeab06 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp
@@ -16,8 +16,10 @@ void MOV(TranslatorVisitor& v, u64 insn, const IR::U32& src, bool is_mov32i = fa
         BitField<12, 4, u64> mov32i_mask;
     } const mov{insn};
 
-    if ((is_mov32i ? mov.mov32i_mask : mov.mask) != 0xf) {
-        throw NotImplementedException("Non-full move mask");
+    u64 mask = is_mov32i ? mov.mov32i_mask : mov.mask;
+    if (mask != 0xf && mask != 0x1) {
+        LOG_WARNING(Shader, "(STUBBED) Masked Mov");
+        return;
     }
     v.X(mov.dest_reg, src);
 }
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
index 2f930f1ea..6203003b3 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
@@ -209,7 +209,7 @@ void TranslatorVisitor::R2B(u64) {
 }
 
 void TranslatorVisitor::RAM(u64) {
-    ThrowNotImplemented(Opcode::RAM);
+    LOG_WARNING(Shader, "(STUBBED) RAM Instruction");
 }
 
 void TranslatorVisitor::RET(u64) {
@@ -221,7 +221,7 @@ void TranslatorVisitor::RTT(u64) {
 }
 
 void TranslatorVisitor::SAM(u64) {
-    ThrowNotImplemented(Opcode::SAM);
+    LOG_WARNING(Shader, "(STUBBED) SAM Instruction");
 }
 
 void TranslatorVisitor::SETCRSPTR(u64) {
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/texture_fetch.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/texture_fetch.cpp
index 2459fc30d..7a9b7fff8 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/texture_fetch.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/texture_fetch.cpp
@@ -172,6 +172,7 @@ void Impl(TranslatorVisitor& v, u64 insn, bool aoffi, Blod blod, bool lc,
     info.is_depth.Assign(tex.dc != 0 ? 1 : 0);
     info.has_bias.Assign(blod == Blod::LB || blod == Blod::LBA ? 1 : 0);
     info.has_lod_clamp.Assign(lc ? 1 : 0);
+    info.ndv_is_active.Assign(tex.ndv != 0 ? 1 : 0);
 
     const IR::Value sample{[&]() -> IR::Value {
         if (tex.dc == 0) {