2 files changed, 54 insertions, 8 deletions

diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/condition_code_set.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/condition_code_set.cpp
new file mode 100644
index 000000000..ea0c40a54
--- /dev/null
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/condition_code_set.cpp
@@ -0,0 +1,54 @@
+// Copyright 2021 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include "common/bit_field.h"
+#include "common/common_types.h"
+#include "shader_recompiler/frontend/maxwell/translate/impl/common_funcs.h"
+#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
+
+namespace Shader::Maxwell {
+
+void TranslatorVisitor::CSET(u64 insn) {
+    union {
+        u64 raw;
+        BitField<0, 8, IR::Reg> dest_reg;
+        BitField<8, 5, IR::FlowTest> cc_test;
+        BitField<39, 3, IR::Pred> bop_pred;
+        BitField<42, 1, u64> neg_bop_pred;
+        BitField<44, 1, u64> bf;
+        BitField<45, 2, BooleanOp> bop;
+    } const cset{insn};
+
+    const IR::U32 one_mask{ir.Imm32(-1)};
+    const IR::U32 fp_one{ir.Imm32(0x3f800000)};
+    const IR::U32 fail_result{ir.Imm32(0)};
+    const IR::U32 pass_result{cset.bf == 0 ? one_mask : fp_one};
+    const IR::U1 cc_test_result{ir.GetFlowTestResult(cset.cc_test)};
+    const IR::U1 bop_pred{ir.GetPred(cset.bop_pred, cset.neg_bop_pred != 0)};
+    const IR::U1 pred_result{PredicateCombine(ir, cc_test_result, bop_pred, cset.bop)};
+    const IR::U32 result{ir.Select(pred_result, pass_result, fail_result)};
+    X(cset.dest_reg, result);
+}
+
+void TranslatorVisitor::CSETP(u64 insn) {
+    union {
+        u64 raw;
+        BitField<0, 3, IR::Pred> dest_pred_b;
+        BitField<3, 3, IR::Pred> dest_pred_a;
+        BitField<8, 5, IR::FlowTest> cc_test;
+        BitField<39, 3, IR::Pred> bop_pred;
+        BitField<42, 1, u64> neg_bop_pred;
+        BitField<45, 2, BooleanOp> bop;
+    } const csetp{insn};
+
+    const BooleanOp bop{csetp.bop};
+    const IR::U1 bop_pred{ir.GetPred(csetp.bop_pred, csetp.neg_bop_pred != 0)};
+    const IR::U1 cc_test_result{ir.GetFlowTestResult(csetp.cc_test)};
+    const IR::U1 result_a{PredicateCombine(ir, cc_test_result, bop_pred, bop)};
+    const IR::U1 result_b{PredicateCombine(ir, ir.LogicalNot(cc_test_result), bop_pred, bop)};
+    ir.SetPred(csetp.dest_pred_a, result_a);
+    ir.SetPred(csetp.dest_pred_b, result_b);
+}
+
+} // namespace Shader::Maxwell
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
index b31928370..0325f14ea 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
@@ -85,14 +85,6 @@ void TranslatorVisitor::CS2R(u64) {
     ThrowNotImplemented(Opcode::CS2R);
 }
 
-void TranslatorVisitor::CSET(u64) {
-    ThrowNotImplemented(Opcode::CSET);
-}
-
-void TranslatorVisitor::CSETP(u64) {
-    ThrowNotImplemented(Opcode::CSETP);
-}
-
 void TranslatorVisitor::DADD_reg(u64) {
     ThrowNotImplemented(Opcode::DADD_reg);
 }