diff options
Diffstat (limited to 'src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp')
| -rw-r--r-- | src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp new file mode 100644 index 000000000..7bc7ce9f2 --- /dev/null +++ b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp | |||
| @@ -0,0 +1,79 @@ | |||
| 1 | // Copyright 2021 yuzu Emulator Project | ||
| 2 | // Licensed under GPLv2 or any later version | ||
| 3 | // Refer to the license.txt file included. | ||
| 4 | |||
| 5 | #include "common/bit_field.h" | ||
| 6 | #include "shader_recompiler/frontend/ir/ir_emitter.h" | ||
| 7 | #include "shader_recompiler/frontend/maxwell/translate/impl/impl.h" | ||
| 8 | |||
| 9 | namespace Shader::Maxwell { | ||
| 10 | |||
| 11 | IR::U32 TranslatorVisitor::X(IR::Reg reg) { | ||
| 12 | return ir.GetReg(reg); | ||
| 13 | } | ||
| 14 | |||
| 15 | void TranslatorVisitor::X(IR::Reg dest_reg, const IR::U32& value) { | ||
| 16 | ir.SetReg(dest_reg, value); | ||
| 17 | } | ||
| 18 | |||
| 19 | IR::U32 TranslatorVisitor::GetCbuf(u64 insn) { | ||
| 20 | union { | ||
| 21 | u64 raw; | ||
| 22 | BitField<20, 14, s64> offset; | ||
| 23 | BitField<34, 5, u64> binding; | ||
| 24 | } const cbuf{insn}; | ||
| 25 | if (cbuf.binding >= 18) { | ||
| 26 | throw NotImplementedException("Out of bounds constant buffer binding {}", cbuf.binding); | ||
| 27 | } | ||
| 28 | if (cbuf.offset >= 0x10'000 || cbuf.offset < 0) { | ||
| 29 | throw NotImplementedException("Out of bounds constant buffer offset {}", cbuf.offset); | ||
| 30 | } | ||
| 31 | const IR::U32 binding{ir.Imm32(static_cast<u32>(cbuf.binding))}; | ||
| 32 | const IR::U32 byte_offset{ir.Imm32(static_cast<u32>(cbuf.offset) * 4)}; | ||
| 33 | return ir.GetCbuf(binding, byte_offset); | ||
| 34 | } | ||
| 35 | |||
| 36 | IR::U32 TranslatorVisitor::GetImm(u64 insn) { | ||
| 37 | union { | ||
| 38 | u64 raw; | ||
| 39 | BitField<20, 19, u64> value; | ||
| 40 | BitField<56, 1, u64> is_negative; | ||
| 41 | } const imm{insn}; | ||
| 42 | const s32 positive_value{static_cast<s32>(imm.value)}; | ||
| 43 | const s32 value{imm.is_negative != 0 ? -positive_value : positive_value}; | ||
| 44 | return ir.Imm32(value); | ||
| 45 | } | ||
| 46 | |||
| 47 | void TranslatorVisitor::SetZFlag(const IR::U1& value) { | ||
| 48 | ir.SetZFlag(value); | ||
| 49 | } | ||
| 50 | |||
| 51 | void TranslatorVisitor::SetSFlag(const IR::U1& value) { | ||
| 52 | ir.SetSFlag(value); | ||
| 53 | } | ||
| 54 | |||
| 55 | void TranslatorVisitor::SetCFlag(const IR::U1& value) { | ||
| 56 | ir.SetCFlag(value); | ||
| 57 | } | ||
| 58 | |||
| 59 | void TranslatorVisitor::SetOFlag(const IR::U1& value) { | ||
| 60 | ir.SetOFlag(value); | ||
| 61 | } | ||
| 62 | |||
| 63 | void TranslatorVisitor::ResetZero() { | ||
| 64 | SetZFlag(ir.Imm1(false)); | ||
| 65 | } | ||
| 66 | |||
| 67 | void TranslatorVisitor::ResetSFlag() { | ||
| 68 | SetSFlag(ir.Imm1(false)); | ||
| 69 | } | ||
| 70 | |||
| 71 | void TranslatorVisitor::ResetCFlag() { | ||
| 72 | SetCFlag(ir.Imm1(false)); | ||
| 73 | } | ||
| 74 | |||
| 75 | void TranslatorVisitor::ResetOFlag() { | ||
| 76 | SetOFlag(ir.Imm1(false)); | ||
| 77 | } | ||
| 78 | |||
| 79 | } // namespace Shader::Maxwell | ||