diff options
Diffstat (limited to 'src/shader_recompiler/backend/glsl/reg_alloc.cpp')
| -rw-r--r-- | src/shader_recompiler/backend/glsl/reg_alloc.cpp | 52 |
1 files changed, 34 insertions, 18 deletions
diff --git a/src/shader_recompiler/backend/glsl/reg_alloc.cpp b/src/shader_recompiler/backend/glsl/reg_alloc.cpp index 5fdad5acb..5ad1872db 100644 --- a/src/shader_recompiler/backend/glsl/reg_alloc.cpp +++ b/src/shader_recompiler/backend/glsl/reg_alloc.cpp | |||
| @@ -13,7 +13,6 @@ | |||
| 13 | #pragma optimize("", off) | 13 | #pragma optimize("", off) |
| 14 | namespace Shader::Backend::GLSL { | 14 | namespace Shader::Backend::GLSL { |
| 15 | namespace { | 15 | namespace { |
| 16 | constexpr std::string_view SWIZZLE = "xyzw"; | ||
| 17 | 16 | ||
| 18 | std::string Representation(Id id) { | 17 | std::string Representation(Id id) { |
| 19 | if (id.is_condition_code != 0) { | 18 | if (id.is_condition_code != 0) { |
| @@ -22,7 +21,6 @@ std::string Representation(Id id) { | |||
| 22 | if (id.is_spill != 0) { | 21 | if (id.is_spill != 0) { |
| 23 | throw NotImplementedException("Spilling"); | 22 | throw NotImplementedException("Spilling"); |
| 24 | } | 23 | } |
| 25 | const u32 num_elements{id.num_elements_minus_one + 1}; | ||
| 26 | const u32 index{static_cast<u32>(id.index)}; | 24 | const u32 index{static_cast<u32>(id.index)}; |
| 27 | return fmt::format("R{}", index); | 25 | return fmt::format("R{}", index); |
| 28 | } | 26 | } |
| @@ -45,10 +43,11 @@ std::string MakeImm(const IR::Value& value) { | |||
| 45 | } | 43 | } |
| 46 | } // Anonymous namespace | 44 | } // Anonymous namespace |
| 47 | 45 | ||
| 48 | std::string RegAlloc::Define(IR::Inst& inst, u32 num_elements, u32 alignment) { | 46 | std::string RegAlloc::Define(IR::Inst& inst, Type type) { |
| 49 | const Id id{Alloc(num_elements, alignment)}; | 47 | const Id id{Alloc()}; |
| 48 | const auto type_str{GetType(type, id.index)}; | ||
| 50 | inst.SetDefinition<Id>(id); | 49 | inst.SetDefinition<Id>(id); |
| 51 | return Representation(id); | 50 | return type_str + Representation(id); |
| 52 | } | 51 | } |
| 53 | 52 | ||
| 54 | std::string RegAlloc::Consume(const IR::Value& value) { | 53 | std::string RegAlloc::Consume(const IR::Value& value) { |
| @@ -65,20 +64,37 @@ std::string RegAlloc::Consume(IR::Inst& inst) { | |||
| 65 | return Representation(inst.Definition<Id>()); | 64 | return Representation(inst.Definition<Id>()); |
| 66 | } | 65 | } |
| 67 | 66 | ||
| 68 | Id RegAlloc::Alloc(u32 num_elements, [[maybe_unused]] u32 alignment) { | 67 | std::string RegAlloc::GetType(Type type, u32 index) { |
| 69 | for (size_t reg = 0; reg < NUM_REGS; ++reg) { | 68 | if (register_defined[index]) { |
| 70 | if (register_use[reg]) { | 69 | return ""; |
| 71 | continue; | 70 | } |
| 71 | register_defined[index] = true; | ||
| 72 | switch (type) { | ||
| 73 | case Type::U32: | ||
| 74 | return "uint "; | ||
| 75 | case Type::S32: | ||
| 76 | return "int "; | ||
| 77 | case Type::F32: | ||
| 78 | return "float "; | ||
| 79 | default: | ||
| 80 | return ""; | ||
| 81 | } | ||
| 82 | } | ||
| 83 | |||
| 84 | Id RegAlloc::Alloc() { | ||
| 85 | if (num_used_registers < NUM_REGS) { | ||
| 86 | for (size_t reg = 0; reg < NUM_REGS; ++reg) { | ||
| 87 | if (register_use[reg]) { | ||
| 88 | continue; | ||
| 89 | } | ||
| 90 | register_use[reg] = true; | ||
| 91 | Id ret{}; | ||
| 92 | ret.index.Assign(static_cast<u32>(reg)); | ||
| 93 | ret.is_long.Assign(0); | ||
| 94 | ret.is_spill.Assign(0); | ||
| 95 | ret.is_condition_code.Assign(0); | ||
| 96 | return ret; | ||
| 72 | } | 97 | } |
| 73 | num_used_registers = std::max(num_used_registers, reg + 1); | ||
| 74 | register_use[reg] = true; | ||
| 75 | return Id{ | ||
| 76 | .base_element = 0, | ||
| 77 | .num_elements_minus_one = num_elements - 1, | ||
| 78 | .index = static_cast<u32>(reg), | ||
| 79 | .is_spill = 0, | ||
| 80 | .is_condition_code = 0, | ||
| 81 | }; | ||
| 82 | } | 98 | } |
| 83 | throw NotImplementedException("Register spilling"); | 99 | throw NotImplementedException("Register spilling"); |
| 84 | } | 100 | } |