diff options
Diffstat (limited to 'src/shader_recompiler/backend/glsl/reg_alloc.cpp')
| -rw-r--r-- | src/shader_recompiler/backend/glsl/reg_alloc.cpp | 37 |
1 files changed, 30 insertions, 7 deletions
diff --git a/src/shader_recompiler/backend/glsl/reg_alloc.cpp b/src/shader_recompiler/backend/glsl/reg_alloc.cpp index 591a87988..5fdad5acb 100644 --- a/src/shader_recompiler/backend/glsl/reg_alloc.cpp +++ b/src/shader_recompiler/backend/glsl/reg_alloc.cpp | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | #include "shader_recompiler/backend/glsl/reg_alloc.h" | 10 | #include "shader_recompiler/backend/glsl/reg_alloc.h" |
| 11 | #include "shader_recompiler/exception.h" | 11 | #include "shader_recompiler/exception.h" |
| 12 | #include "shader_recompiler/frontend/ir/value.h" | 12 | #include "shader_recompiler/frontend/ir/value.h" |
| 13 | 13 | #pragma optimize("", off) | |
| 14 | namespace Shader::Backend::GLSL { | 14 | namespace Shader::Backend::GLSL { |
| 15 | namespace { | 15 | namespace { |
| 16 | constexpr std::string_view SWIZZLE = "xyzw"; | 16 | constexpr std::string_view SWIZZLE = "xyzw"; |
| @@ -24,11 +24,7 @@ std::string Representation(Id id) { | |||
| 24 | } | 24 | } |
| 25 | const u32 num_elements{id.num_elements_minus_one + 1}; | 25 | const u32 num_elements{id.num_elements_minus_one + 1}; |
| 26 | const u32 index{static_cast<u32>(id.index)}; | 26 | const u32 index{static_cast<u32>(id.index)}; |
| 27 | if (num_elements == 4) { | 27 | return fmt::format("R{}", index); |
| 28 | return fmt::format("R{}", index); | ||
| 29 | } else { | ||
| 30 | return fmt::format("R{}.{}", index, SWIZZLE.substr(id.base_element, num_elements)); | ||
| 31 | } | ||
| 32 | } | 28 | } |
| 33 | 29 | ||
| 34 | std::string MakeImm(const IR::Value& value) { | 30 | std::string MakeImm(const IR::Value& value) { |
| @@ -56,7 +52,8 @@ std::string RegAlloc::Define(IR::Inst& inst, u32 num_elements, u32 alignment) { | |||
| 56 | } | 52 | } |
| 57 | 53 | ||
| 58 | std::string RegAlloc::Consume(const IR::Value& value) { | 54 | std::string RegAlloc::Consume(const IR::Value& value) { |
| 59 | return value.IsImmediate() ? MakeImm(value) : Consume(*value.Inst()); | 55 | const auto result = value.IsImmediate() ? MakeImm(value) : Consume(*value.InstRecursive()); |
| 56 | return result; | ||
| 60 | } | 57 | } |
| 61 | 58 | ||
| 62 | std::string RegAlloc::Consume(IR::Inst& inst) { | 59 | std::string RegAlloc::Consume(IR::Inst& inst) { |
| @@ -93,4 +90,30 @@ void RegAlloc::Free(Id id) { | |||
| 93 | register_use[id.index] = false; | 90 | register_use[id.index] = false; |
| 94 | } | 91 | } |
| 95 | 92 | ||
| 93 | /*static*/ bool RegAlloc::IsAliased(const IR::Inst& inst) { | ||
| 94 | switch (inst.GetOpcode()) { | ||
| 95 | case IR::Opcode::Identity: | ||
| 96 | case IR::Opcode::BitCastU16F16: | ||
| 97 | case IR::Opcode::BitCastU32F32: | ||
| 98 | case IR::Opcode::BitCastU64F64: | ||
| 99 | case IR::Opcode::BitCastF16U16: | ||
| 100 | case IR::Opcode::BitCastF32U32: | ||
| 101 | case IR::Opcode::BitCastF64U64: | ||
| 102 | return true; | ||
| 103 | default: | ||
| 104 | return false; | ||
| 105 | } | ||
| 106 | } | ||
| 107 | |||
| 108 | /*static*/ IR::Inst& RegAlloc::AliasInst(IR::Inst& inst) { | ||
| 109 | IR::Inst* it{&inst}; | ||
| 110 | while (IsAliased(*it)) { | ||
| 111 | const IR::Value arg{it->Arg(0)}; | ||
| 112 | if (arg.IsImmediate()) { | ||
| 113 | break; | ||
| 114 | } | ||
| 115 | it = arg.InstRecursive(); | ||
| 116 | } | ||
| 117 | return *it; | ||
| 118 | } | ||
| 96 | } // namespace Shader::Backend::GLSL | 119 | } // namespace Shader::Backend::GLSL |