diff options
Diffstat (limited to 'src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp')
| -rw-r--r-- | src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp | 42 |
1 files changed, 30 insertions, 12 deletions
diff --git a/src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp b/src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp index 2be91ccfd..15fd23356 100644 --- a/src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp +++ b/src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp | |||
| @@ -87,20 +87,38 @@ void EmitBitwiseXor32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b | |||
| 87 | 87 | ||
| 88 | void EmitBitFieldInsert(EmitContext& ctx, IR::Inst& inst, ScalarS32 base, ScalarS32 insert, | 88 | void EmitBitFieldInsert(EmitContext& ctx, IR::Inst& inst, ScalarS32 base, ScalarS32 insert, |
| 89 | ScalarS32 offset, ScalarS32 count) { | 89 | ScalarS32 offset, ScalarS32 count) { |
| 90 | ctx.Add("MOV.U RC.x,{};MOV.U RC.y,{};", count, offset); | 90 | const Register ret{ctx.reg_alloc.Define(inst)}; |
| 91 | ctx.Add("BFI.S {},RC,{},{};", inst, insert, base); | 91 | if (count.type != Type::Register && offset.type != Type::Register) { |
| 92 | ctx.Add("BFI.S {},{{{},{},0,0}},{},{};", ret, count, offset, insert, base); | ||
| 93 | } else { | ||
| 94 | ctx.Add("MOV.S RC.x,{};MOV.U RC.y,{};" | ||
| 95 | "BFI.S {},RC,{},{};", | ||
| 96 | count, offset, ret, insert, base); | ||
| 97 | } | ||
| 92 | } | 98 | } |
| 93 | 99 | ||
| 94 | void EmitBitFieldSExtract(EmitContext& ctx, IR::Inst& inst, ScalarS32 base, ScalarS32 offset, | 100 | void EmitBitFieldSExtract(EmitContext& ctx, IR::Inst& inst, ScalarS32 base, ScalarS32 offset, |
| 95 | ScalarS32 count) { | 101 | ScalarS32 count) { |
| 96 | ctx.Add("MOV.U RC.x,{};MOV.U RC.y,{};", count, offset); | 102 | const Register ret{ctx.reg_alloc.Define(inst)}; |
| 97 | ctx.Add("BFE.S {},RC,{};", inst, base); | 103 | if (count.type != Type::Register && offset.type != Type::Register) { |
| 104 | ctx.Add("BFE.S {},{{{},{},0,0}},{};", ret, count, offset, base); | ||
| 105 | } else { | ||
| 106 | ctx.Add("MOV.S RC.x,{};MOV.U RC.y,{};" | ||
| 107 | "BFE.S {},RC,{};", | ||
| 108 | count, offset, ret, base); | ||
| 109 | } | ||
| 98 | } | 110 | } |
| 99 | 111 | ||
| 100 | void EmitBitFieldUExtract(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, ScalarU32 offset, | 112 | void EmitBitFieldUExtract(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, ScalarU32 offset, |
| 101 | ScalarU32 count) { | 113 | ScalarU32 count) { |
| 102 | ctx.Add("MOV.U RC.x,{};MOV.U RC.y,{};", count, offset); | 114 | const Register ret{ctx.reg_alloc.Define(inst)}; |
| 103 | ctx.Add("BFE.U {},RC,{};", inst, base); | 115 | if (count.type != Type::Register && offset.type != Type::Register) { |
| 116 | ctx.Add("BFE.U {},{{{},{},0,0}},{};", ret, count, offset, base); | ||
| 117 | } else { | ||
| 118 | ctx.Add("MOV.U RC.x,{};MOV.U RC.y,{};" | ||
| 119 | "BFE.U {},RC,{};", | ||
| 120 | count, offset, ret, base); | ||
| 121 | } | ||
| 104 | } | 122 | } |
| 105 | 123 | ||
| 106 | void EmitBitReverse32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value) { | 124 | void EmitBitReverse32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value) { |
| @@ -141,16 +159,16 @@ void EmitUMax32(EmitContext& ctx, IR::Inst& inst, ScalarU32 a, ScalarU32 b) { | |||
| 141 | 159 | ||
| 142 | void EmitSClamp32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value, ScalarS32 min, ScalarS32 max) { | 160 | void EmitSClamp32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value, ScalarS32 min, ScalarS32 max) { |
| 143 | const Register ret{ctx.reg_alloc.Define(inst)}; | 161 | const Register ret{ctx.reg_alloc.Define(inst)}; |
| 144 | ctx.Add("MIN.S {}.x,{},{};" | 162 | ctx.Add("MIN.S RC.x,{},{};" |
| 145 | "MAX.S {}.x,{},{};", | 163 | "MAX.S {}.x,RC.x,{};", |
| 146 | ret, max, value, ret, ret, min); | 164 | max, value, ret, min); |
| 147 | } | 165 | } |
| 148 | 166 | ||
| 149 | void EmitUClamp32(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, ScalarU32 min, ScalarU32 max) { | 167 | void EmitUClamp32(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, ScalarU32 min, ScalarU32 max) { |
| 150 | const Register ret{ctx.reg_alloc.Define(inst)}; | 168 | const Register ret{ctx.reg_alloc.Define(inst)}; |
| 151 | ctx.Add("MIN.U {}.x,{},{};" | 169 | ctx.Add("MIN.U RC.x,{},{};" |
| 152 | "MAX.U {}.x,{},{};", | 170 | "MAX.U {}.x,RC.x,{};", |
| 153 | ret, max, value, ret, ret, min); | 171 | max, value, ret, min); |
| 154 | } | 172 | } |
| 155 | 173 | ||
| 156 | void EmitSLessThan(EmitContext& ctx, IR::Inst& inst, ScalarS32 lhs, ScalarS32 rhs) { | 174 | void EmitSLessThan(EmitContext& ctx, IR::Inst& inst, ScalarS32 lhs, ScalarS32 rhs) { |