9 files changed, 272 insertions, 93 deletions

diff --git a/src/core/CMakeLists.txt b/src/core/CMakeLists.txt
index f71232c1a..3381524e3 100644
--- a/src/core/CMakeLists.txt
+++ b/src/core/CMakeLists.txt
@@ -20,6 +20,7 @@ set(SRCS
             file_sys/archive_romfs.cpp
             file_sys/archive_savedata.cpp
             file_sys/archive_sdmc.cpp
+            file_sys/archive_systemsavedata.cpp
             file_sys/disk_archive.cpp
             file_sys/file_romfs.cpp
             file_sys/directory_romfs.cpp
@@ -101,6 +102,7 @@ set(HEADERS
             file_sys/archive_romfs.h
             file_sys/archive_savedata.h
             file_sys/archive_sdmc.h
+            file_sys/archive_systemsavedata.h
             file_sys/disk_archive.h
             file_sys/file_backend.h
             file_sys/file_romfs.h
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index 1a589e39c..63cfd03c6 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -1356,7 +1356,13 @@ mainswitch:
                     }
                     break;
 
-                case 0x04:      /* SUB reg */
+                case 0x04: /* SUB reg */
+                    // Signifies UMAAL
+                    if (state->is_v6 && BITS(4, 7) == 0x09) {
+                        if (handle_v6_insn(state, instr))
+                            break;
+                    }
+
 #ifdef MODET
                     if (BITS (4, 7) == 0xB) {
                         /* STRH immediate offset, no write-back, down, post indexed.  */
@@ -3103,12 +3109,18 @@ mainswitch:
                         state->Reg[idest] = (state->Reg[rfis] & 0xFFFF) | ((state->Reg[rlast] << ishi) & 0xFFFF0000);
                         break;
                     } else if ((instr & 0x70) == 0x50) { //pkhtb
-                        u8 idest = BITS(12, 15);
-                        u8 rfis = BITS(16, 19);
-                        u8 rlast = BITS(0, 3);
-                        u8 ishi = BITS(7, 11);
-                        if (ishi == 0)ishi = 0x20;
-                        state->Reg[idest] = (((int)(state->Reg[rlast]) >> (int)(ishi))& 0xFFFF) | ((state->Reg[rfis]) & 0xFFFF0000);
+                        const u8 rd_idx = BITS(12, 15);
+                        const u8 rn_idx = BITS(16, 19);
+                        const u8 rm_idx = BITS(0, 3);
+                        const u8 imm5 = BITS(7, 11);
+
+                        ARMword val;
+                        if (imm5 >= 32)
+                            val = (state->Reg[rm_idx] >> 31);
+                        else
+                            val = (state->Reg[rm_idx] >> imm5);
+
+                        state->Reg[rd_idx] = (val & 0xFFFF) | ((state->Reg[rn_idx]) & 0xFFFF0000);
                         break;
                     } else if (BIT (4)) {
 #ifdef MODE32
@@ -5669,16 +5681,29 @@ L_stm_s_takeabort:
     /* Attempt to emulate an ARMv6 instruction.
        Returns non-zero upon success.  */
 
-    static int
-    handle_v6_insn (ARMul_State * state, ARMword instr) {
-                ARMword lhs, temp;
-
-        switch (BITS (20, 27)) {
+    static int handle_v6_insn(ARMul_State* state, ARMword instr) {
+        switch (BITS(20, 27)) {
         case 0x03:
             printf ("Unhandled v6 insn: ldr\n");
             break;
-        case 0x04:
-            printf ("Unhandled v6 insn: umaal\n");
+        case 0x04: // UMAAL
+            {
+                const u8 rm_idx = BITS(8, 11);
+                const u8 rn_idx = BITS(0, 3);
+                const u8 rd_lo_idx = BITS(12, 15);
+                const u8 rd_hi_idx = BITS(16, 19);
+
+                const u32 rm_val = state->Reg[rm_idx];
+                const u32 rn_val = state->Reg[rn_idx];
+                const u32 rd_lo_val = state->Reg[rd_lo_idx];
+                const u32 rd_hi_val = state->Reg[rd_hi_idx];
+
+                const u64 result = (rn_val * rm_val) + rd_lo_val + rd_hi_val;
+
+                state->Reg[rd_lo_idx] = (result & 0xFFFFFFFF);
+                state->Reg[rd_hi_idx] = ((result >> 32) & 0xFFFFFFFF);
+                return 1;
+            }
             break;
         case 0x06:
             printf ("Unhandled v6 insn: mls/str\n");
@@ -5691,7 +5716,7 @@ L_stm_s_takeabort:
                                 /* strex */
                                 u32 l = LHSReg;
                                 u32 r = RHSReg;
-                                lhs = LHS;
+                                u32 lhs = LHS;
 
                                 bool enter = false;
 
@@ -5716,7 +5741,7 @@ L_stm_s_takeabort:
         case 0x19:
                         /* ldrex */
                         if (BITS(4, 7) == 0x9) {
-                                lhs = LHS;
+                                u32 lhs = LHS;
 
                                 state->currentexaddr = lhs;
                                 state->currentexval = ARMul_ReadWord(state, lhs);
@@ -5735,7 +5760,7 @@ L_stm_s_takeabort:
         case 0x1c:
                         if (BITS(4, 7) == 0x9) {
                                 /* strexb */
-                                lhs = LHS;
+                                u32 lhs = LHS;
 
                                 bool enter = false;
 
@@ -5765,11 +5790,11 @@ L_stm_s_takeabort:
         case 0x1d:
                         if ((BITS(4, 7)) == 0x9) {
                                 /* ldrexb */
-                                temp = LHS;
-                                LoadByte(state, instr, temp, LUNSIGNED);
+                                u32 lhs = LHS;
+                                LoadByte(state, instr, lhs, LUNSIGNED);
 
-                                state->currentexaddr = temp;
-                                state->currentexval = (u32)ARMul_ReadByte(state, temp);
+                                state->currentexaddr = lhs;
+                                state->currentexval = (u32)ARMul_ReadByte(state, lhs);
 
                                 //state->Reg[BITS(12, 15)] = ARMul_LoadByte(state, state->Reg[BITS(16, 19)]);
                                 //printf("ldrexb\n");
@@ -5799,49 +5824,63 @@ L_stm_s_takeabort:
         case 0x3f:
             printf ("Unhandled v6 insn: rbit\n");
             break;
-        case 0x61:
-            if ((instr & 0xFF0) == 0xf70) { //ssub16
-                u8 tar = BITS(12, 15);
-                u8 src1 = BITS(16, 19);
-                u8 src2 = BITS(0, 3);
-                s16 a1 = (state->Reg[src1] & 0xFFFF);
-                s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
-                s16 b1 = (state->Reg[src2] & 0xFFFF);
-                s16 b2 = ((state->Reg[src2] >> 0x10) & 0xFFFF);
-                                state->Reg[tar] = ((a1 - a2) & 0xFFFF) | (((b1 - b2) & 0xFFFF) << 0x10);
-                return 1;
-            } else if ((instr & 0xFF0) == 0xf10) { //sadd16
+        case 0x61: // SSUB16, SADD16, SSAX, and SASX
+            if ((instr & 0xFF0) == 0xf70 || (instr & 0xFF0) == 0xf10 ||
+                (instr & 0xFF0) == 0xf50 || (instr & 0xFF0) == 0xf30)
+            {
                 const u8 rd_idx = BITS(12, 15);
                 const u8 rm_idx = BITS(0, 3);
                 const u8 rn_idx = BITS(16, 19);
-                const s16 rm_lo = (state->Reg[rm_idx] & 0xFFFF);
-                const s16 rm_hi = ((state->Reg[rm_idx] >> 16) & 0xFFFF);
                 const s16 rn_lo = (state->Reg[rn_idx] & 0xFFFF);
                 const s16 rn_hi = ((state->Reg[rn_idx] >> 16) & 0xFFFF);
+                const s16 rm_lo = (state->Reg[rm_idx] & 0xFFFF);
+                const s16 rm_hi = ((state->Reg[rm_idx] >> 16) & 0xFFFF);
 
-                state->Reg[rd_idx] = ((rn_lo + rm_lo) & 0xFFFF) | (((rn_hi + rm_hi) & 0xFFFF) << 16);
-                return 1;
-            } else if ((instr & 0xFF0) == 0xf50) { //ssax
-                u8 tar = BITS(12, 15);
-                u8 src1 = BITS(16, 19);
-                u8 src2 = BITS(0, 3);
-                s16 a1 = (state->Reg[src1] & 0xFFFF);
-                s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
-                s16 b1 = (state->Reg[src2] & 0xFFFF);
-                s16 b2 = ((state->Reg[src2] >> 0x10) & 0xFFFF);
-                                state->Reg[tar] = ((a1 + b2) & 0xFFFF) | (((a2 - b1) & 0xFFFF) << 0x10);
-                return 1;
-            } else if ((instr & 0xFF0) == 0xf30) { //sasx
-                u8 tar = BITS(12, 15);
-                u8 src1 = BITS(16, 19);
-                u8 src2 = BITS(0, 3);
-                s16 a1 = (state->Reg[src1] & 0xFFFF);
-                s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
-                s16 b1 = (state->Reg[src2] & 0xFFFF);
-                s16 b2 = ((state->Reg[src2] >> 0x10) & 0xFFFF);
-                                state->Reg[tar] = ((a1 - b2) & 0xFFFF) | (((a2 + b1) & 0xFFFF) << 0x10);
+                s32 lo_result;
+                s32 hi_result;
+
+                // SSUB16
+                if ((instr & 0xFF0) == 0xf70) {
+                    lo_result = (rn_lo - rm_lo);
+                    hi_result = (rn_hi - rm_hi);
+                }
+                // SADD16
+                else if ((instr & 0xFF0) == 0xf10) {
+                    lo_result = (rn_lo + rm_lo);
+                    hi_result = (rn_hi + rm_hi);
+                }
+                // SSAX
+                else if ((instr & 0xFF0) == 0xf50) {
+                    lo_result = (rn_lo + rm_hi);
+                    hi_result = (rn_hi - rm_lo);
+                }
+                // SASX
+                else {
+                    lo_result = (rn_lo - rm_hi);
+                    hi_result = (rn_hi + rm_lo);
+                }
+
+                state->Reg[rd_idx] = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16);
+
+                if (lo_result >= 0) {
+                    state->Cpsr |= (1 << 16);
+                    state->Cpsr |= (1 << 17);
+                } else {
+                    state->Cpsr &= ~(1 << 16);
+                    state->Cpsr &= ~(1 << 17);
+                }
+
+                if (hi_result >= 0) {
+                    state->Cpsr |= (1 << 18);
+                    state->Cpsr |= (1 << 19);
+                } else {
+                    state->Cpsr &= ~(1 << 18);
+                    state->Cpsr &= ~(1 << 19);
+                }
                 return 1;
-            } else printf ("Unhandled v6 insn: sadd/ssub/ssax/sasx\n");
+            } else {
+                printf("Unhandled v6 insn: %08x", BITS(20, 27));
+            }
             break;
         case 0x62: // QSUB16 and QADD16
             if ((instr & 0xFF0) == 0xf70 || (instr & 0xFF0) == 0xf10) {
@@ -5930,11 +5969,29 @@ L_stm_s_takeabort:
                         b2 = ((u8)(from >> 8) + (u8)(to >> 8));
                         b3 = ((u8)(from >> 16) + (u8)(to >> 16));
                         b4 = ((u8)(from >> 24) + (u8)(to >> 24));
-                        if (b1 & 0xffffff00) state->Cpsr |= (1 << 16);
-                        if (b2 & 0xffffff00) state->Cpsr |= (1 << 17);
-                        if (b3 & 0xffffff00) state->Cpsr |= (1 << 18);
-                        if (b4 & 0xffffff00) state->Cpsr |= (1 << 19);
+
+                        if (b1 & 0xffffff00)
+                            state->Cpsr |= (1 << 16);
+                        else
+                            state->Cpsr &= ~(1 << 16);
+
+                        if (b2 & 0xffffff00)
+                            state->Cpsr |= (1 << 17);
+                        else
+                            state->Cpsr &= ~(1 << 17);
+
+                        if (b3 & 0xffffff00)
+                            state->Cpsr |= (1 << 18);
+                        else
+                            state->Cpsr &= ~(1 << 18);
+
+
+                        if (b4 & 0xffffff00)
+                            state->Cpsr |= (1 << 19);
+                        else
+                            state->Cpsr &= ~(1 << 19);
                     }
+
                     state->Reg[rd] = (u32)(b1 | (b2 & 0xff) << 8 | (b3 & 0xff) << 16 | (b4 & 0xff) << 24);
                     return 1;
                 }
@@ -6049,7 +6106,7 @@ L_stm_s_takeabort:
                                 break;
                         }
 
-                        Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF);
+                        Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF);
                         if (Rm & 0x80)
                                 Rm |= 0xffffff00;
 
@@ -6058,11 +6115,12 @@ L_stm_s_takeabort:
                                 state->Reg[BITS(12, 15)] = Rm;
                         else
                                 /* SXTAB */
-                                state->Reg[BITS(12, 15)] += Rm;
+                                state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + Rm;
 
                         return 1;
                 }
-                case 0x6b: {
+                case 0x6b:
+                {
                         ARMword Rm;
                         int ror = -1;
 
@@ -6080,10 +6138,10 @@ L_stm_s_takeabort:
                                         ror = 24;
                                         break;
 
-                                case 0xf3:
+                                case 0xf3: // REV
                                         DEST = ((RHS & 0xFF) << 24) | ((RHS & 0xFF00)) << 8 | ((RHS & 0xFF0000) >> 8) | ((RHS & 0xFF000000) >> 24);
                                         return 1;
-                                case 0xfb:
+                                case 0xfb: // REV16
                                         DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00)) >> 8 | ((RHS & 0xFF0000) << 8) | ((RHS & 0xFF000000) >> 8);
                                         return 1;
                                 default:
@@ -6093,7 +6151,7 @@ L_stm_s_takeabort:
                         if (ror == -1)
                                 break;
 
-                        Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF);
+                        Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF);
                         if (Rm & 0x8000)
                                 Rm |= 0xffff0000;
 
@@ -6156,18 +6214,27 @@ L_stm_s_takeabort:
                                         //ichfly
                                         //USAT16
                                 {
-                                        u8 tar = BITS(12, 15);
-                                        u8 src = BITS(0, 3);
-                                        u8 val = BITS(16, 19);
-                                        s16 a1 = (state->Reg[src]);
-                                        s16 a2 = (state->Reg[src] >> 0x10);
-                                        s16 max = 0xFFFF >> (16 - val);
-                                        if (max < a1) a1 = max;
-                                        if (max < a2) a2 = max;
-                                        u32 temp2 = ((u32)(a2)) << 0x10;
-                                        state->Reg[tar] = (a1 & 0xFFFF) | (temp2);
+                                        const u8 rd_idx = BITS(12, 15);
+                                        const u8 rn_idx = BITS(0, 3);
+                                        const u8 num_bits = BITS(16, 19);
+                                        const s16 max = 0xFFFF >> (16 - num_bits);
+                                        s16 rn_lo = (state->Reg[rn_idx]);
+                                        s16 rn_hi = (state->Reg[rn_idx] >> 16);
+                                        
+                                        if (max < rn_lo)
+                                                rn_lo = max;
+                                        else if (rn_lo < 0)
+                                                rn_lo = 0;
+
+                                        if (max < rn_hi)
+                                                rn_hi = max;
+                                        else if (rn_hi < 0)
+                                                rn_hi = 0;
+                                        
+                                        state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi << 16) & 0xFFFF);
+                                        return 1;
                                 }
-                                return 1;
+
                                 default:
                                         break;
                         }
@@ -6180,7 +6247,7 @@ L_stm_s_takeabort:
                                 break;
                         }
 
-                        Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF);
+                        Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF);
 
                         if (BITS(16, 19) == 0xf)
                                 /* UXTB */
@@ -6210,9 +6277,13 @@ L_stm_s_takeabort:
                                         ror = 24;
                                         break;
 
-                                case 0xfb:
-                                        printf("Unhandled v6 insn: revsh\n");
-                                        return 0;
+                                case 0xfb: // REVSH
+                                {
+                                        DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00) >> 8);
+                                        if (DEST & 0x8000)
+                                                DEST |= 0xffff0000;
+                                        return 1;
+                                }
                                 default:
                                         break;
                         }
@@ -6220,13 +6291,13 @@ L_stm_s_takeabort:
                         if (ror == -1)
                                 break;
 
-                        Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF);
+                        Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF);
 
                         /* UXT */
                         /* state->Reg[BITS (12, 15)] = Rm; */
                         /* dyf add */
                         if (BITS(16, 19) == 0xf) {
-                                state->Reg[BITS(12, 15)] = (Rm >> (8 * BITS(10, 11))) & 0x0000FFFF;
+                                state->Reg[BITS(12, 15)] = Rm;
                         }
                         else {
                                 /* UXTAH */
@@ -6234,7 +6305,7 @@ L_stm_s_takeabort:
                                 //            printf("rd is %x rn is %x rm is %x rotate is %x\n", state->Reg[BITS (12, 15)], state->Reg[BITS (16, 19)]
                                 //                   , Rm, BITS(10, 11));
                                 //            printf("icounter is %lld\n", state->NumInstrs);
-                                state->Reg[BITS(12, 15)] = (state->Reg[BITS(16, 19)] >> (8 * (BITS(10, 11)))) + Rm;
+                                state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + Rm;
                                 //        printf("rd is %x\n", state->Reg[BITS (12, 15)]);
                                 //        exit(-1);
                         }
diff --git a/src/core/file_sys/archive_savedata.h b/src/core/file_sys/archive_savedata.h
index b3e561130..d394ad37e 100644
--- a/src/core/file_sys/archive_savedata.h
+++ b/src/core/file_sys/archive_savedata.h
@@ -21,8 +21,7 @@ public:
 
     /**
      * Initialize the archive.
-     * @return CreateSaveDataResult AlreadyExists if the SaveData folder already exists,
-     * Success if it was created properly and Failure if there was any error
+     * @return true if it initialized successfully
      */
     bool Initialize();
 
diff --git a/src/core/file_sys/archive_systemsavedata.cpp b/src/core/file_sys/archive_systemsavedata.cpp
new file mode 100644
index 000000000..dc2c23b41
--- /dev/null
+++ b/src/core/file_sys/archive_systemsavedata.cpp
@@ -0,0 +1,33 @@
+// Copyright 2014 Citra Emulator Project
+// Licensed under GPLv2+
+// Refer to the license.txt file included.
+
+#include <sys/stat.h>
+
+#include "common/common_types.h"
+#include "common/file_util.h"
+
+#include "core/file_sys/archive_systemsavedata.h"
+#include "core/file_sys/disk_archive.h"
+#include "core/settings.h"
+
+////////////////////////////////////////////////////////////////////////////////////////////////////
+// FileSys namespace
+
+namespace FileSys {
+
+Archive_SystemSaveData::Archive_SystemSaveData(const std::string& mount_point)
+        : DiskArchive(mount_point) {
+    LOG_INFO(Service_FS, "Directory %s set as SystemSaveData.", this->mount_point.c_str());
+}
+
+bool Archive_SystemSaveData::Initialize() {
+    if (!FileUtil::CreateFullPath(mount_point)) {
+        LOG_ERROR(Service_FS, "Unable to create SystemSaveData path.");
+        return false;
+    }
+
+    return true;
+}
+
+} // namespace FileSys
diff --git a/src/core/file_sys/archive_systemsavedata.h b/src/core/file_sys/archive_systemsavedata.h
new file mode 100644
index 000000000..360ed1e13
--- /dev/null
+++ b/src/core/file_sys/archive_systemsavedata.h
@@ -0,0 +1,33 @@
+// Copyright 2014 Citra Emulator Project
+// Licensed under GPLv2+
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include "common/common_types.h"
+
+#include "core/file_sys/disk_archive.h"
+#include "core/loader/loader.h"
+
+////////////////////////////////////////////////////////////////////////////////////////////////////
+// FileSys namespace
+
+namespace FileSys {
+
+/// File system interface to the SystemSaveData archive
+/// TODO(Subv): This archive should point to a location in the NAND, 
+/// specifically nand:/data/<ID0>/sysdata/<SaveID-Low>/<SaveID-High>
+class Archive_SystemSaveData final : public DiskArchive {
+public:
+    Archive_SystemSaveData(const std::string& mount_point);
+
+    /**
+     * Initialize the archive.
+     * @return true if it initialized successfully
+     */
+    bool Initialize();
+
+    std::string GetName() const override { return "SystemSaveData"; }
+};
+
+} // namespace FileSys
diff --git a/src/core/hle/kernel/shared_memory.h b/src/core/hle/kernel/shared_memory.h
index 304cf5b67..bb778ec26 100644
--- a/src/core/hle/kernel/shared_memory.h
+++ b/src/core/hle/kernel/shared_memory.h
@@ -12,11 +12,15 @@ namespace Kernel {
 
 /// Permissions for mapped shared memory blocks
 enum class MemoryPermission : u32 {
-    None        = 0,
-    Read        = (1u <<  0),
-    Write       = (1u <<  1),
-    ReadWrite   = (Read | Write),
-    DontCare    = (1u << 28)
+    None             = 0,
+    Read             = (1u <<  0),
+    Write            = (1u <<  1),
+    ReadWrite        = (Read | Write),
+    Execute          = (1u <<  2),
+    ReadExecute      = (Read | Execute),
+    WriteExecute     = (Write | Execute),
+    ReadWriteExecute = (Read | Write | Execute),
+    DontCare         = (1u << 28)
 };
 
 /**
diff --git a/src/core/hle/service/fs/archive.cpp b/src/core/hle/service/fs/archive.cpp
index 9c3834733..5ab82729c 100644
--- a/src/core/hle/service/fs/archive.cpp
+++ b/src/core/hle/service/fs/archive.cpp
@@ -419,6 +419,15 @@ void ArchiveInit() {
         CreateArchive(std::move(sdmc_archive), ArchiveIdCode::SDMC);
     else
         LOG_ERROR(Service_FS, "Can't instantiate SDMC archive with path %s", sdmc_directory.c_str());
+
+    std::string systemsavedata_directory = FileUtil::GetUserPath(D_SYSSAVEDATA_IDX);
+    auto systemsavedata_archive = std::make_unique<FileSys::Archive_SDMC>(systemsavedata_directory);
+    if (systemsavedata_archive->Initialize()) {
+        CreateArchive(std::move(systemsavedata_archive), ArchiveIdCode::SystemSaveData);
+    } else {
+        LOG_ERROR(Service_FS, "Can't instantiate SystemSaveData archive with path %s",
+            systemsavedata_directory.c_str());
+    }
 }
 
 /// Shutdown archives
diff --git a/src/core/hle/service/gsp_gpu.cpp b/src/core/hle/service/gsp_gpu.cpp
index db8027142..8c9ad2712 100644
--- a/src/core/hle/service/gsp_gpu.cpp
+++ b/src/core/hle/service/gsp_gpu.cpp
@@ -145,6 +145,30 @@ static void SetBufferSwap(Service::Interface* self) {
 }
 
 /**
+ * GSP_GPU::FlushDataCache service function
+ *
+ * This Function is a no-op, We aren't emulating the CPU cache any time soon.
+ *
+ *  Inputs:
+ *      1 : Address
+ *      2 : Size
+ *      3 : Value 0, some descriptor for the KProcess Handle
+ *      4 : KProcess handle
+ *  Outputs:
+ *      1 : Result of function, 0 on success, otherwise error code
+ */
+static void FlushDataCache(Service::Interface* self) {
+    u32* cmd_buff = Kernel::GetCommandBuffer();
+    u32 address = cmd_buff[1];
+    u32 size    = cmd_buff[2];
+    u32 process = cmd_buff[4];
+
+    // TODO(purpasmart96): Verify return header on HW
+
+    cmd_buff[1] = RESULT_SUCCESS.raw; // No error
+}
+
+/**
  * GSP_GPU::RegisterInterruptRelayQueue service function
  *  Inputs:
  *      1 : "Flags" field, purpose is unknown
@@ -335,7 +359,7 @@ const Interface::FunctionInfo FunctionTable[] = {
     {0x00050200, SetBufferSwap,                 "SetBufferSwap"},
     {0x00060082, nullptr,                       "SetCommandList"},
     {0x000700C2, nullptr,                       "RequestDma"},
-    {0x00080082, nullptr,                       "FlushDataCache"},
+    {0x00080082, FlushDataCache,                "FlushDataCache"},
     {0x00090082, nullptr,                       "InvalidateDataCache"},
     {0x000A0044, nullptr,                       "RegisterInterruptEvents"},
     {0x000B0040, nullptr,                       "SetLcdForceBlack"},
diff --git a/src/core/hle/svc.cpp b/src/core/hle/svc.cpp
index 15cc240f4..47e9bf77e 100644
--- a/src/core/hle/svc.cpp
+++ b/src/core/hle/svc.cpp
@@ -64,6 +64,10 @@ static Result MapMemoryBlock(Handle handle, u32 addr, u32 permissions, u32 other
     case Kernel::MemoryPermission::Read:
     case Kernel::MemoryPermission::Write:
     case Kernel::MemoryPermission::ReadWrite:
+    case Kernel::MemoryPermission::Execute:
+    case Kernel::MemoryPermission::ReadExecute:
+    case Kernel::MemoryPermission::WriteExecute:
+    case Kernel::MemoryPermission::ReadWriteExecute:
     case Kernel::MemoryPermission::DontCare:
         Kernel::MapSharedMemory(handle, addr, permissions_type,
             static_cast<Kernel::MemoryPermission>(other_permissions));