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-rw-r--r--src/core/arm/dyncom/arm_dyncom_dec.cpp8
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp21
2 files changed, 15 insertions, 14 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp
index 12181d0ec..411850f0f 100644
--- a/src/core/arm/dyncom/arm_dyncom_dec.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp
@@ -190,12 +190,12 @@ const ISEITEM arm_instruction[] = {
190 { "cdp", 2, 0, 24, 27, 0x0000000e, 4, 4, 0x00000000 }, 190 { "cdp", 2, 0, 24, 27, 0x0000000e, 4, 4, 0x00000000 },
191 { "stc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000000 }, 191 { "stc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000000 },
192 { "ldc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000001 }, 192 { "ldc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000001 },
193 { "swi", 1, 0, 24, 27, 0x0000000f },
194 { "bbl", 1, 0, 25, 27, 0x00000005 },
195 { "ldrexd", 2, ARMV6K, 20, 27, 0x0000001B, 4, 7, 0x00000009 }, 193 { "ldrexd", 2, ARMV6K, 20, 27, 0x0000001B, 4, 7, 0x00000009 },
196 { "strexd", 2, ARMV6K, 20, 27, 0x0000001A, 4, 7, 0x00000009 }, 194 { "strexd", 2, ARMV6K, 20, 27, 0x0000001A, 4, 7, 0x00000009 },
197 { "ldrexh", 2, ARMV6K, 20, 27, 0x0000001F, 4, 7, 0x00000009 }, 195 { "ldrexh", 2, ARMV6K, 20, 27, 0x0000001F, 4, 7, 0x00000009 },
198 { "strexh", 2, ARMV6K, 20, 27, 0x0000001E, 4, 7, 0x00000009 }, 196 { "strexh", 2, ARMV6K, 20, 27, 0x0000001E, 4, 7, 0x00000009 },
197 { "swi", 1, 0, 24, 27, 0x0000000f },
198 { "bbl", 1, 0, 25, 27, 0x00000005 },
199}; 199};
200 200
201const ISEITEM arm_exclusion_code[] = { 201const ISEITEM arm_exclusion_code[] = {
@@ -383,12 +383,12 @@ const ISEITEM arm_exclusion_code[] = {
383 { "cdp", 0, 0, 0 }, 383 { "cdp", 0, 0, 0 },
384 { "stc", 0, 0, 0 }, 384 { "stc", 0, 0, 0 },
385 { "ldc", 0, 0, 0 }, 385 { "ldc", 0, 0, 0 },
386 { "swi", 0, 0, 0 },
387 { "bbl", 0, 0, 0 },
388 { "ldrexd", 0, ARMV6K, 0 }, 386 { "ldrexd", 0, ARMV6K, 0 },
389 { "strexd", 0, ARMV6K, 0 }, 387 { "strexd", 0, ARMV6K, 0 },
390 { "ldrexh", 0, ARMV6K, 0 }, 388 { "ldrexh", 0, ARMV6K, 0 },
391 { "strexh", 0, ARMV6K, 0 }, 389 { "strexh", 0, ARMV6K, 0 },
390 { "swi", 0, 0, 0 },
391 { "bbl", 0, 0, 0 },
392 392
393 { "bl_1_thumb", 0, INVALID, 0 }, // Should be table[-4] 393 { "bl_1_thumb", 0, INVALID, 0 }, // Should be table[-4]
394 { "bl_2_thumb", 0, INVALID, 0 }, // Should be located at the end of the table[-3] 394 { "bl_2_thumb", 0, INVALID, 0 }, // Should be located at the end of the table[-3]
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 8c52bdb72..8de46294b 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -3544,12 +3544,12 @@ const transop_fp_t arm_instruction_trans[] = {
3544 INTERPRETER_TRANSLATE(cdp), 3544 INTERPRETER_TRANSLATE(cdp),
3545 INTERPRETER_TRANSLATE(stc), 3545 INTERPRETER_TRANSLATE(stc),
3546 INTERPRETER_TRANSLATE(ldc), 3546 INTERPRETER_TRANSLATE(ldc),
3547 INTERPRETER_TRANSLATE(swi),
3548 INTERPRETER_TRANSLATE(bbl),
3549 INTERPRETER_TRANSLATE(ldrexd), 3547 INTERPRETER_TRANSLATE(ldrexd),
3550 INTERPRETER_TRANSLATE(strexd), 3548 INTERPRETER_TRANSLATE(strexd),
3551 INTERPRETER_TRANSLATE(ldrexh), 3549 INTERPRETER_TRANSLATE(ldrexh),
3552 INTERPRETER_TRANSLATE(strexh), 3550 INTERPRETER_TRANSLATE(strexh),
3551 INTERPRETER_TRANSLATE(swi),
3552 INTERPRETER_TRANSLATE(bbl),
3553 3553
3554 // All the thumb instructions should be placed the end of table 3554 // All the thumb instructions should be placed the end of table
3555 INTERPRETER_TRANSLATE(b_2_thumb), 3555 INTERPRETER_TRANSLATE(b_2_thumb),
@@ -3920,12 +3920,12 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
3920 case 180: goto CDP_INST; \ 3920 case 180: goto CDP_INST; \
3921 case 181: goto STC_INST; \ 3921 case 181: goto STC_INST; \
3922 case 182: goto LDC_INST; \ 3922 case 182: goto LDC_INST; \
3923 case 183: goto SWI_INST; \ 3923 case 183: goto LDREXD_INST; \
3924 case 184: goto BBL_INST; \ 3924 case 184: goto STREXD_INST; \
3925 case 185: goto LDREXD_INST; \ 3925 case 185: goto LDREXH_INST; \
3926 case 186: goto STREXD_INST; \ 3926 case 186: goto STREXH_INST; \
3927 case 187: goto LDREXH_INST; \ 3927 case 187: goto SWI_INST; \
3928 case 188: goto STREXH_INST; \ 3928 case 188: goto BBL_INST; \
3929 case 189: goto B_2_THUMB ; \ 3929 case 189: goto B_2_THUMB ; \
3930 case 190: goto B_COND_THUMB ; \ 3930 case 190: goto B_COND_THUMB ; \
3931 case 191: goto BL_1_THUMB ; \ 3931 case 191: goto BL_1_THUMB ; \
@@ -3980,8 +3980,9 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
3980 &&MLA_INST,&&SSAT_INST,&&USAT_INST,&&MRS_INST,&&MSR_INST,&&AND_INST,&&BIC_INST,&&LDM_INST,&&EOR_INST,&&ADD_INST,&&RSB_INST,&&RSC_INST, 3980 &&MLA_INST,&&SSAT_INST,&&USAT_INST,&&MRS_INST,&&MSR_INST,&&AND_INST,&&BIC_INST,&&LDM_INST,&&EOR_INST,&&ADD_INST,&&RSB_INST,&&RSC_INST,
3981 &&SBC_INST,&&ADC_INST,&&SUB_INST,&&ORR_INST,&&MVN_INST,&&MOV_INST,&&STM_INST,&&LDM_INST,&&LDRSH_INST,&&STM_INST,&&LDM_INST,&&LDRSB_INST, 3981 &&SBC_INST,&&ADC_INST,&&SUB_INST,&&ORR_INST,&&MVN_INST,&&MOV_INST,&&STM_INST,&&LDM_INST,&&LDRSH_INST,&&STM_INST,&&LDM_INST,&&LDRSB_INST,
3982 &&STRD_INST,&&LDRH_INST,&&STRH_INST,&&LDRD_INST,&&STRT_INST,&&STRBT_INST,&&LDRBT_INST,&&LDRT_INST,&&MRC_INST,&&MCR_INST,&&MSR_INST, 3982 &&STRD_INST,&&LDRH_INST,&&STRH_INST,&&LDRD_INST,&&STRT_INST,&&STRBT_INST,&&LDRBT_INST,&&LDRT_INST,&&MRC_INST,&&MCR_INST,&&MSR_INST,
3983 &&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST,&&SWI_INST,&&BBL_INST,&&LDREXD_INST, 3983 &&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST, &&LDREXD_INST,
3984 &&STREXD_INST,&&LDREXH_INST,&&STREXH_INST,&&B_2_THUMB, &&B_COND_THUMB,&&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH, 3984 &&STREXD_INST,&&LDREXH_INST,&&STREXH_INST, &&SWI_INST,&&BBL_INST,
3985 &&B_2_THUMB, &&B_COND_THUMB,&&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH,
3985 &&INIT_INST_LENGTH,&&END 3986 &&INIT_INST_LENGTH,&&END
3986 }; 3987 };
3987#endif 3988#endif