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-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_64.cpp18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
index 4e73cc03a..587fffb34 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
@@ -86,6 +86,24 @@ public:
86 num_instructions, MemoryReadCode(pc)); 86 num_instructions, MemoryReadCode(pc));
87 } 87 }
88 88
89 void InstructionCacheOperationRaised(Dynarmic::A64::InstructionCacheOperation op,
90 VAddr value) override {
91 constexpr u64 ICACHE_LINE_SIZE = 64;
92 u64 cache_line_start;
93
94 switch (op) {
95 case Dynarmic::A64::InstructionCacheOperation::InvalidateByVAToPoU:
96 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
97 parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE);
98 return;
99
100 case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
101 case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
102 default:
103 LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation");
104 }
105 }
106
89 void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override { 107 void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {
90 switch (exception) { 108 switch (exception) {
91 case Dynarmic::A64::Exception::WaitForInterrupt: 109 case Dynarmic::A64::Exception::WaitForInterrupt: