diff options
Diffstat (limited to 'src/core')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 32 |
1 files changed, 15 insertions, 17 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index b5e0993ed..6052e4f58 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp | |||
| @@ -1726,25 +1726,21 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(ldrb)(unsigned int inst, int index) | |||
| 1726 | } | 1726 | } |
| 1727 | ARM_INST_PTR INTERPRETER_TRANSLATE(ldrbt)(unsigned int inst, int index) | 1727 | ARM_INST_PTR INTERPRETER_TRANSLATE(ldrbt)(unsigned int inst, int index) |
| 1728 | { | 1728 | { |
| 1729 | arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); | 1729 | arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); |
| 1730 | ldst_inst *inst_cream = (ldst_inst *)inst_base->component; | 1730 | ldst_inst* inst_cream = (ldst_inst*)inst_base->component; |
| 1731 | 1731 | ||
| 1732 | inst_base->cond = BITS(inst, 28, 31); | 1732 | inst_base->cond = BITS(inst, 28, 31); |
| 1733 | inst_base->idx = index; | 1733 | inst_base->idx = index; |
| 1734 | inst_base->br = NON_BRANCH; | 1734 | inst_base->br = NON_BRANCH; |
| 1735 | 1735 | ||
| 1736 | inst_cream->inst = inst; | 1736 | inst_cream->inst = inst; |
| 1737 | if (I_BIT == 0) { | 1737 | if (BITS(inst, 25, 27) == 2) { |
| 1738 | inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed); | 1738 | inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed); |
| 1739 | } else if (BITS(inst, 25, 27) == 3) { | ||
| 1740 | inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed); | ||
| 1739 | } else { | 1741 | } else { |
| 1740 | DEBUG_MSG; | 1742 | DEBUG_MSG; |
| 1741 | } | 1743 | } |
| 1742 | #if 0 | ||
| 1743 | inst_cream->get_addr = get_calc_addr_op(inst); | ||
| 1744 | if(inst == 0x54f13001) { | ||
| 1745 | DEBUG_LOG(ARM11, "get_calc_addr_op:%llx\n", inst_cream->get_addr); | ||
| 1746 | } | ||
| 1747 | #endif | ||
| 1748 | 1744 | ||
| 1749 | if (BITS(inst, 12, 15) == 15) { | 1745 | if (BITS(inst, 12, 15) == 15) { |
| 1750 | inst_base->br = INDIRECT_BRANCH; | 1746 | inst_base->br = INDIRECT_BRANCH; |
| @@ -2712,17 +2708,19 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(strb)(unsigned int inst, int index) | |||
| 2712 | } | 2708 | } |
| 2713 | ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(unsigned int inst, int index) | 2709 | ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(unsigned int inst, int index) |
| 2714 | { | 2710 | { |
| 2715 | arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); | 2711 | arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); |
| 2716 | ldst_inst *inst_cream = (ldst_inst *)inst_base->component; | 2712 | ldst_inst* inst_cream = (ldst_inst*)inst_base->component; |
| 2717 | 2713 | ||
| 2718 | inst_base->cond = BITS(inst, 28, 31); | 2714 | inst_base->cond = BITS(inst, 28, 31); |
| 2719 | inst_base->idx = index; | 2715 | inst_base->idx = index; |
| 2720 | inst_base->br = NON_BRANCH; | 2716 | inst_base->br = NON_BRANCH; |
| 2721 | 2717 | ||
| 2722 | inst_cream->inst = inst; | 2718 | inst_cream->inst = inst; |
| 2723 | // inst_cream->get_addr = get_calc_addr_op(inst); | 2719 | |
| 2724 | if (I_BIT == 0) { | 2720 | if (BITS(inst, 25, 27) == 2) { |
| 2725 | inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed); | 2721 | inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed); |
| 2722 | } else if (BITS(inst, 25, 27) == 3) { | ||
| 2723 | inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed); | ||
| 2726 | } else { | 2724 | } else { |
| 2727 | DEBUG_MSG; | 2725 | DEBUG_MSG; |
| 2728 | } | 2726 | } |