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-rw-r--r--src/core/hw/gpu.cpp9
-rw-r--r--src/core/hw/hw.cpp26
-rw-r--r--src/core/hw/hw.h26
3 files changed, 30 insertions, 31 deletions
diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp
index 424ce2ca7..9942aab1f 100644
--- a/src/core/hw/gpu.cpp
+++ b/src/core/hw/gpu.cpp
@@ -15,12 +15,13 @@
15#include "core/hle/service/gsp_gpu.h" 15#include "core/hle/service/gsp_gpu.h"
16#include "core/hle/service/dsp_dsp.h" 16#include "core/hle/service/dsp_dsp.h"
17 17
18#include "core/hw/hw.h"
18#include "core/hw/gpu.h" 19#include "core/hw/gpu.h"
19 20
20#include "video_core/command_processor.h" 21#include "video_core/command_processor.h"
21#include "video_core/utils.h" 22#include "video_core/utils.h"
22#include "video_core/video_core.h" 23#include "video_core/video_core.h"
23#include <video_core/color.h> 24#include "video_core/color.h"
24 25
25namespace GPU { 26namespace GPU {
26 27
@@ -40,7 +41,7 @@ static bool last_skip_frame = false;
40 41
41template <typename T> 42template <typename T>
42inline void Read(T &var, const u32 raw_addr) { 43inline void Read(T &var, const u32 raw_addr) {
43 u32 addr = raw_addr - 0x1EF00000; 44 u32 addr = raw_addr - HW::VADDR_GPU;
44 u32 index = addr / 4; 45 u32 index = addr / 4;
45 46
46 // Reads other than u32 are untested, so I'd rather have them abort than silently fail 47 // Reads other than u32 are untested, so I'd rather have them abort than silently fail
@@ -54,7 +55,7 @@ inline void Read(T &var, const u32 raw_addr) {
54 55
55template <typename T> 56template <typename T>
56inline void Write(u32 addr, const T data) { 57inline void Write(u32 addr, const T data) {
57 addr -= 0x1EF00000; 58 addr -= HW::VADDR_GPU;
58 u32 index = addr / 4; 59 u32 index = addr / 4;
59 60
60 // Writes other than u32 are untested, so I'd rather have them abort than silently fail 61 // Writes other than u32 are untested, so I'd rather have them abort than silently fail
@@ -313,8 +314,6 @@ void Init() {
313 framebuffer_top.address_right2 = 0x182B9800; 314 framebuffer_top.address_right2 = 0x182B9800;
314 framebuffer_sub.address_left1 = 0x1848F000; 315 framebuffer_sub.address_left1 = 0x1848F000;
315 framebuffer_sub.address_left2 = 0x184C7800; 316 framebuffer_sub.address_left2 = 0x184C7800;
316 //framebuffer_sub.address_right1 = unknown;
317 //framebuffer_sub.address_right2 = unknown;
318 317
319 framebuffer_top.width = 240; 318 framebuffer_top.width = 240;
320 framebuffer_top.height = 400; 319 framebuffer_top.height = 400;
diff --git a/src/core/hw/hw.cpp b/src/core/hw/hw.cpp
index a63ba6eeb..bf4722cf7 100644
--- a/src/core/hw/hw.cpp
+++ b/src/core/hw/hw.cpp
@@ -9,32 +9,6 @@
9 9
10namespace HW { 10namespace HW {
11 11
12enum {
13 VADDR_HASH = 0x1EC01000,
14 VADDR_CSND = 0x1EC03000,
15 VADDR_DSP = 0x1EC40000,
16 VADDR_PDN = 0x1EC41000,
17 VADDR_CODEC = 0x1EC41000,
18 VADDR_SPI = 0x1EC42000,
19 VADDR_SPI_2 = 0x1EC43000, // Only used under TWL_FIRM?
20 VADDR_I2C = 0x1EC44000,
21 VADDR_CODEC_2 = 0x1EC45000,
22 VADDR_HID = 0x1EC46000,
23 VADDR_PAD = 0x1EC46000,
24 VADDR_PTM = 0x1EC46000,
25 VADDR_GPIO = 0x1EC47000,
26 VADDR_I2C_2 = 0x1EC48000,
27 VADDR_SPI_3 = 0x1EC60000,
28 VADDR_I2C_3 = 0x1EC61000,
29 VADDR_MIC = 0x1EC62000,
30 VADDR_PXI = 0x1EC63000, // 0xFFFD2000
31 //VADDR_NTRCARD
32 VADDR_CDMA = 0xFFFDA000, // CoreLink DMA-330? Info
33 VADDR_DSP_2 = 0x1ED03000,
34 VADDR_HASH_2 = 0x1EE01000,
35 VADDR_GPU = 0x1EF00000,
36};
37
38template <typename T> 12template <typename T>
39inline void Read(T &var, const u32 addr) { 13inline void Read(T &var, const u32 addr) {
40 switch (addr & 0xFFFFF000) { 14 switch (addr & 0xFFFFF000) {
diff --git a/src/core/hw/hw.h b/src/core/hw/hw.h
index 991c0a07d..6feeba08c 100644
--- a/src/core/hw/hw.h
+++ b/src/core/hw/hw.h
@@ -8,6 +8,32 @@
8 8
9namespace HW { 9namespace HW {
10 10
11enum {
12 VADDR_IO = 0x1EC00000,
13 VADDR_HASH = 0x1EC01000,
14 VADDR_CSND = 0x1EC03000,
15 VADDR_DSP = 0x1EC40000,
16 VADDR_PDN = 0x1EC41000,
17 VADDR_CODEC = 0x1EC41000,
18 VADDR_SPI = 0x1EC42000,
19 VADDR_SPI_2 = 0x1EC43000, // Only used under TWL_FIRM?
20 VADDR_I2C = 0x1EC44000,
21 VADDR_CODEC_2 = 0x1EC45000,
22 VADDR_HID = 0x1EC46000,
23 VADDR_GPIO = 0x1EC47000,
24 VADDR_I2C_2 = 0x1EC48000,
25 VADDR_SPI_3 = 0x1EC60000,
26 VADDR_I2C_3 = 0x1EC61000,
27 VADDR_MIC = 0x1EC62000,
28 VADDR_PXI = 0x1EC63000, // 0xFFFD2000
29 //VADDR_NTRCARD
30 VADDR_CDMA = 0xFFFDA000, // CoreLink DMA-330? Info
31 VADDR_LCD = 0x1ED02000,
32 VADDR_DSP_2 = 0x1ED03000,
33 VADDR_HASH_2 = 0x1EE01000,
34 VADDR_GPU = 0x1EF00000,
35};
36
11template <typename T> 37template <typename T>
12void Read(T &var, const u32 addr); 38void Read(T &var, const u32 addr);
13 39