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-rw-r--r--src/core/hw/gpu.h334
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diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h
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1// Copyright 2014 Citra Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#pragma once
6
7#include <cstddef>
8#include <type_traits>
9#include "common/assert.h"
10#include "common/bit_field.h"
11#include "common/common_funcs.h"
12#include "common/common_types.h"
13
14namespace GPU {
15
16constexpr float SCREEN_REFRESH_RATE = 60;
17
18// Returns index corresponding to the Regs member labeled by field_name
19// TODO: Due to Visual studio bug 209229, offsetof does not return constant expressions
20// when used with array elements (e.g. GPU_REG_INDEX(memory_fill_config[0])).
21// For details cf.
22// https://connect.microsoft.com/VisualStudio/feedback/details/209229/offsetof-does-not-produce-a-constant-expression-for-array-members
23// Hopefully, this will be fixed sometime in the future.
24// For lack of better alternatives, we currently hardcode the offsets when constant
25// expressions are needed via GPU_REG_INDEX_WORKAROUND (on sane compilers, static_asserts
26// will then make sure the offsets indeed match the automatically calculated ones).
27#define GPU_REG_INDEX(field_name) (offsetof(GPU::Regs, field_name) / sizeof(u32))
28#if defined(_MSC_VER)
29#define GPU_REG_INDEX_WORKAROUND(field_name, backup_workaround_index) (backup_workaround_index)
30#else
31// NOTE: Yeah, hacking in a static_assert here just to workaround the lacking MSVC compiler
32// really is this annoying. This macro just forwards its first argument to GPU_REG_INDEX
33// and then performs a (no-op) cast to size_t iff the second argument matches the expected
34// field offset. Otherwise, the compiler will fail to compile this code.
35#define GPU_REG_INDEX_WORKAROUND(field_name, backup_workaround_index) \
36 ((typename std::enable_if<backup_workaround_index == GPU_REG_INDEX(field_name), size_t>::type) \
37 GPU_REG_INDEX(field_name))
38#endif
39
40// MMIO region 0x1EFxxxxx
41struct Regs {
42
43// helper macro to make sure the defined structures are of the expected size.
44#if defined(_MSC_VER)
45// TODO: MSVC does not support using sizeof() on non-static data members even though this
46// is technically allowed since C++11. This macro should be enabled once MSVC adds
47// support for that.
48#define ASSERT_MEMBER_SIZE(name, size_in_bytes)
49#else
50#define ASSERT_MEMBER_SIZE(name, size_in_bytes) \
51 static_assert(sizeof(name) == size_in_bytes, \
52 "Structure size and register block length don't match")
53#endif
54
55 // Components are laid out in reverse byte order, most significant bits first.
56 enum class PixelFormat : u32 {
57 RGBA8 = 0,
58 RGB8 = 1,
59 RGB565 = 2,
60 RGB5A1 = 3,
61 RGBA4 = 4,
62 };
63
64 /**
65 * Returns the number of bytes per pixel.
66 */
67 static int BytesPerPixel(PixelFormat format) {
68 switch (format) {
69 case PixelFormat::RGBA8:
70 return 4;
71 case PixelFormat::RGB8:
72 return 3;
73 case PixelFormat::RGB565:
74 case PixelFormat::RGB5A1:
75 case PixelFormat::RGBA4:
76 return 2;
77 }
78
79 UNREACHABLE();
80 }
81
82 INSERT_PADDING_WORDS(0x4);
83
84 struct MemoryFillConfig {
85 u32 address_start;
86 u32 address_end;
87
88 union {
89 u32 value_32bit;
90
91 BitField<0, 16, u32> value_16bit;
92
93 // TODO: Verify component order
94 BitField<0, 8, u32> value_24bit_r;
95 BitField<8, 8, u32> value_24bit_g;
96 BitField<16, 8, u32> value_24bit_b;
97 };
98
99 union {
100 u32 control;
101
102 // Setting this field to 1 triggers the memory fill.
103 // This field also acts as a status flag, and gets reset to 0 upon completion.
104 BitField<0, 1, u32> trigger;
105
106 // Set to 1 upon completion.
107 BitField<1, 1, u32> finished;
108
109 // If both of these bits are unset, then it will fill the memory with a 16 bit value
110 // 1: fill with 24-bit wide values
111 BitField<8, 1, u32> fill_24bit;
112 // 1: fill with 32-bit wide values
113 BitField<9, 1, u32> fill_32bit;
114 };
115
116 inline u32 GetStartAddress() const {
117 return DecodeAddressRegister(address_start);
118 }
119
120 inline u32 GetEndAddress() const {
121 return DecodeAddressRegister(address_end);
122 }
123 } memory_fill_config[2];
124 ASSERT_MEMBER_SIZE(memory_fill_config[0], 0x10);
125
126 INSERT_PADDING_WORDS(0x10b);
127
128 struct FramebufferConfig {
129 union {
130 u32 size;
131
132 BitField<0, 16, u32> width;
133 BitField<16, 16, u32> height;
134 };
135
136 INSERT_PADDING_WORDS(0x2);
137
138 u32 address_left1;
139 u32 address_left2;
140
141 union {
142 u32 format;
143
144 BitField<0, 3, PixelFormat> color_format;
145 };
146
147 INSERT_PADDING_WORDS(0x1);
148
149 union {
150 u32 active_fb;
151
152 // 0: Use parameters ending with "1"
153 // 1: Use parameters ending with "2"
154 BitField<0, 1, u32> second_fb_active;
155 };
156
157 INSERT_PADDING_WORDS(0x5);
158
159 // Distance between two pixel rows, in bytes
160 u32 stride;
161
162 u32 address_right1;
163 u32 address_right2;
164
165 INSERT_PADDING_WORDS(0x30);
166 } framebuffer_config[2];
167 ASSERT_MEMBER_SIZE(framebuffer_config[0], 0x100);
168
169 INSERT_PADDING_WORDS(0x169);
170
171 struct DisplayTransferConfig {
172 u32 input_address;
173 u32 output_address;
174
175 inline u32 GetPhysicalInputAddress() const {
176 return DecodeAddressRegister(input_address);
177 }
178
179 inline u32 GetPhysicalOutputAddress() const {
180 return DecodeAddressRegister(output_address);
181 }
182
183 union {
184 u32 output_size;
185
186 BitField<0, 16, u32> output_width;
187 BitField<16, 16, u32> output_height;
188 };
189
190 union {
191 u32 input_size;
192
193 BitField<0, 16, u32> input_width;
194 BitField<16, 16, u32> input_height;
195 };
196
197 enum ScalingMode : u32 {
198 NoScale = 0, // Doesn't scale the image
199 ScaleX = 1, // Downscales the image in half in the X axis and applies a box filter
200 ScaleXY =
201 2, // Downscales the image in half in both the X and Y axes and applies a box filter
202 };
203
204 union {
205 u32 flags;
206
207 BitField<0, 1, u32> flip_vertically; // flips input data vertically
208 BitField<1, 1, u32> input_linear; // Converts from linear to tiled format
209 BitField<2, 1, u32> crop_input_lines;
210 BitField<3, 1, u32> is_texture_copy; // Copies the data without performing any
211 // processing and respecting texture copy fields
212 BitField<5, 1, u32> dont_swizzle;
213 BitField<8, 3, PixelFormat> input_format;
214 BitField<12, 3, PixelFormat> output_format;
215 /// Uses some kind of 32x32 block swizzling mode, instead of the usual 8x8 one.
216 BitField<16, 1, u32> block_32; // TODO(yuriks): unimplemented
217 BitField<24, 2, ScalingMode> scaling; // Determines the scaling mode of the transfer
218 };
219
220 INSERT_PADDING_WORDS(0x1);
221
222 // it seems that writing to this field triggers the display transfer
223 u32 trigger;
224
225 INSERT_PADDING_WORDS(0x1);
226
227 struct {
228 u32 size; // The lower 4 bits are ignored
229
230 union {
231 u32 input_size;
232
233 BitField<0, 16, u32> input_width;
234 BitField<16, 16, u32> input_gap;
235 };
236
237 union {
238 u32 output_size;
239
240 BitField<0, 16, u32> output_width;
241 BitField<16, 16, u32> output_gap;
242 };
243 } texture_copy;
244 } display_transfer_config;
245 ASSERT_MEMBER_SIZE(display_transfer_config, 0x2c);
246
247 INSERT_PADDING_WORDS(0x32D);
248
249 struct {
250 // command list size (in bytes)
251 u32 size;
252
253 INSERT_PADDING_WORDS(0x1);
254
255 // command list address
256 u32 address;
257
258 INSERT_PADDING_WORDS(0x1);
259
260 // it seems that writing to this field triggers command list processing
261 u32 trigger;
262
263 inline u32 GetPhysicalAddress() const {
264 return DecodeAddressRegister(address);
265 }
266 } command_processor_config;
267 ASSERT_MEMBER_SIZE(command_processor_config, 0x14);
268
269 INSERT_PADDING_WORDS(0x9c3);
270
271 static constexpr size_t NumIds() {
272 return sizeof(Regs) / sizeof(u32);
273 }
274
275 const u32& operator[](int index) const {
276 const u32* content = reinterpret_cast<const u32*>(this);
277 return content[index];
278 }
279
280 u32& operator[](int index) {
281 u32* content = reinterpret_cast<u32*>(this);
282 return content[index];
283 }
284
285#undef ASSERT_MEMBER_SIZE
286
287private:
288 /*
289 * Most physical addresses which GPU registers refer to are 8-byte aligned.
290 * This function should be used to get the address from a raw register value.
291 */
292 static inline u32 DecodeAddressRegister(u32 register_value) {
293 return register_value * 8;
294 }
295};
296static_assert(std::is_standard_layout<Regs>::value, "Structure does not use standard layout");
297
298// TODO: MSVC does not support using offsetof() on non-static data members even though this
299// is technically allowed since C++11. This macro should be enabled once MSVC adds
300// support for that.
301#ifndef _MSC_VER
302#define ASSERT_REG_POSITION(field_name, position) \
303 static_assert(offsetof(Regs, field_name) == position * 4, \
304 "Field " #field_name " has invalid position")
305
306ASSERT_REG_POSITION(memory_fill_config[0], 0x00004);
307ASSERT_REG_POSITION(memory_fill_config[1], 0x00008);
308ASSERT_REG_POSITION(framebuffer_config[0], 0x00117);
309ASSERT_REG_POSITION(framebuffer_config[1], 0x00157);
310ASSERT_REG_POSITION(display_transfer_config, 0x00300);
311ASSERT_REG_POSITION(command_processor_config, 0x00638);
312
313#undef ASSERT_REG_POSITION
314#endif // !defined(_MSC_VER)
315
316// The total number of registers is chosen arbitrarily, but let's make sure it's not some odd value
317// anyway.
318static_assert(sizeof(Regs) == 0x1000 * sizeof(u32), "Invalid total size of register set");
319
320extern Regs g_regs;
321
322template <typename T>
323void Read(T& var, const u32 addr);
324
325template <typename T>
326void Write(u32 addr, const T data);
327
328/// Initialize hardware
329void Init();
330
331/// Shutdown hardware
332void Shutdown();
333
334} // namespace
HIC SVNT DRACONES