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-rw-r--r--src/core/hw/gpu.h40
1 files changed, 40 insertions, 0 deletions
diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h
index 58058d732..29eb7ed81 100644
--- a/src/core/hw/gpu.h
+++ b/src/core/hw/gpu.h
@@ -5,6 +5,7 @@
5#pragma once 5#pragma once
6 6
7#include "common/common_types.h" 7#include "common/common_types.h"
8#include "common/bit_field.h"
8 9
9namespace GPU { 10namespace GPU {
10 11
@@ -44,6 +45,45 @@ struct Registers {
44 u32 framebuffer_sub_right_1; 45 u32 framebuffer_sub_right_1;
45 u32 framebuffer_sub_right_2; 46 u32 framebuffer_sub_right_2;
46 47
48 struct {
49 u32 input_address;
50 u32 output_address;
51
52 inline u32 GetPhysicalInputAddress() const {
53 return input_address * 8;
54 }
55
56 inline u32 GetPhysicalOutputAddress() const {
57 return output_address * 8;
58 }
59
60 union {
61 u32 output_size;
62
63 BitField< 0, 16, u32> output_width;
64 BitField<16, 16, u32> output_height;
65 };
66
67 union {
68 u32 input_size;
69
70 BitField< 0, 16, u32> input_width;
71 BitField<16, 16, u32> input_height;
72 };
73
74 union {
75 u32 flags;
76
77 BitField< 0, 1, u32> flip_data;
78 BitField< 8, 3, u32> input_format;
79 BitField<12, 3, u32> output_format;
80 BitField<16, 1, u32> output_tiled;
81 };
82
83 u32 unknown;
84 u32 trigger;
85 } display_transfer;
86
47 u32 command_list_size; 87 u32 command_list_size;
48 u32 command_list_address; 88 u32 command_list_address;
49 u32 command_processing_enabled; 89 u32 command_processing_enabled;