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diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp
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1/* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17
18#include <cstring>
19#include "core/arm/skyeye_common/armdefs.h"
20#include "core/arm/skyeye_common/vfp/vfp.h"
21
22/***************************************************************************\
23* Returns a new instantiation of the ARMulator's state *
24\***************************************************************************/
25ARMul_State* ARMul_NewState(ARMul_State* state)
26{
27 state->Emulate = RUN;
28 state->Mode = USER32MODE;
29
30 state->lateabtSig = HIGH;
31 state->bigendSig = LOW;
32
33 return state;
34}
35
36/***************************************************************************\
37* Call this routine to set ARMulator to model a certain processor *
38\***************************************************************************/
39
40void ARMul_SelectProcessor(ARMul_State* state, unsigned properties)
41{
42 state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) != 0;
43 state->is_v5 = (properties & ARM_v5_Prop) != 0;
44 state->is_v5e = (properties & ARM_v5e_Prop) != 0;
45 state->is_v6 = (properties & ARM_v6_Prop) != 0;
46 state->is_v7 = (properties & ARM_v7_Prop) != 0;
47}
48
49// Resets certain MPCore CP15 values to their ARM-defined reset values.
50static void ResetMPCoreCP15Registers(ARMul_State* cpu)
51{
52 // c0
53 cpu->CP15[CP15_MAIN_ID] = 0x410FB024;
54 cpu->CP15[CP15_TLB_TYPE] = 0x00000800;
55 cpu->CP15[CP15_PROCESSOR_FEATURE_0] = 0x00000111;
56 cpu->CP15[CP15_PROCESSOR_FEATURE_1] = 0x00000001;
57 cpu->CP15[CP15_DEBUG_FEATURE_0] = 0x00000002;
58 cpu->CP15[CP15_MEMORY_MODEL_FEATURE_0] = 0x01100103;
59 cpu->CP15[CP15_MEMORY_MODEL_FEATURE_1] = 0x10020302;
60 cpu->CP15[CP15_MEMORY_MODEL_FEATURE_2] = 0x01222000;
61 cpu->CP15[CP15_MEMORY_MODEL_FEATURE_3] = 0x00000000;
62 cpu->CP15[CP15_ISA_FEATURE_0] = 0x00100011;
63 cpu->CP15[CP15_ISA_FEATURE_1] = 0x12002111;
64 cpu->CP15[CP15_ISA_FEATURE_2] = 0x11221011;
65 cpu->CP15[CP15_ISA_FEATURE_3] = 0x01102131;
66 cpu->CP15[CP15_ISA_FEATURE_4] = 0x00000141;
67
68 // c1
69 cpu->CP15[CP15_CONTROL] = 0x00054078;
70 cpu->CP15[CP15_AUXILIARY_CONTROL] = 0x0000000F;
71 cpu->CP15[CP15_COPROCESSOR_ACCESS_CONTROL] = 0x00000000;
72
73 // c2
74 cpu->CP15[CP15_TRANSLATION_BASE_TABLE_0] = 0x00000000;
75 cpu->CP15[CP15_TRANSLATION_BASE_TABLE_1] = 0x00000000;
76 cpu->CP15[CP15_TRANSLATION_BASE_CONTROL] = 0x00000000;
77
78 // c3
79 cpu->CP15[CP15_DOMAIN_ACCESS_CONTROL] = 0x00000000;
80
81 // c7
82 cpu->CP15[CP15_PHYS_ADDRESS] = 0x00000000;
83
84 // c9
85 cpu->CP15[CP15_DATA_CACHE_LOCKDOWN] = 0xFFFFFFF0;
86
87 // c10
88 cpu->CP15[CP15_TLB_LOCKDOWN] = 0x00000000;
89 cpu->CP15[CP15_PRIMARY_REGION_REMAP] = 0x00098AA4;
90 cpu->CP15[CP15_NORMAL_REGION_REMAP] = 0x44E048E0;
91
92 // c13
93 cpu->CP15[CP15_PID] = 0x00000000;
94 cpu->CP15[CP15_CONTEXT_ID] = 0x00000000;
95 cpu->CP15[CP15_THREAD_UPRW] = 0x00000000;
96 cpu->CP15[CP15_THREAD_URO] = 0x00000000;
97 cpu->CP15[CP15_THREAD_PRW] = 0x00000000;
98
99 // c15
100 cpu->CP15[CP15_PERFORMANCE_MONITOR_CONTROL] = 0x00000000;
101 cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS] = 0x00000000;
102 cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS] = 0x00000000;
103 cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE] = 0x00000000;
104 cpu->CP15[CP15_TLB_DEBUG_CONTROL] = 0x00000000;
105}
106
107/***************************************************************************\
108* Call this routine to set up the initial machine state (or perform a RESET *
109\***************************************************************************/
110void ARMul_Reset(ARMul_State* state)
111{
112 VFPInit(state);
113
114 state->Reg[15] = 0;
115 state->Cpsr = INTBITS | SVC32MODE;
116 state->Mode = SVC32MODE;
117 state->Bank = SVCBANK;
118
119 ResetMPCoreCP15Registers(state);
120
121 state->NresetSig = HIGH;
122 state->NfiqSig = HIGH;
123 state->NirqSig = HIGH;
124 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
125 state->abortSig = LOW;
126
127 state->NumInstrs = 0;
128}
HIC SVNT DRACONES