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1/* armemu.h -- ARMulator emulation macros: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17#ifndef __ARMEMU_H__
18#define __ARMEMU_H__
19
20#include "common.h"
21#include "armdefs.h"
22//#include "skyeye.h"
23
24extern ARMword isize;
25
26/* Condition code values. */
27#define EQ 0
28#define NE 1
29#define CS 2
30#define CC 3
31#define MI 4
32#define PL 5
33#define VS 6
34#define VC 7
35#define HI 8
36#define LS 9
37#define GE 10
38#define LT 11
39#define GT 12
40#define LE 13
41#define AL 14
42#define NV 15
43
44/* Shift Opcodes. */
45#define LSL 0
46#define LSR 1
47#define ASR 2
48#define ROR 3
49
50/* Macros to twiddle the status flags and mode. */
51#define NBIT ((unsigned)1L << 31)
52#define ZBIT (1L << 30)
53#define CBIT (1L << 29)
54#define VBIT (1L << 28)
55#define SBIT (1L << 27)
56#define IBIT (1L << 7)
57#define FBIT (1L << 6)
58#define IFBITS (3L << 6)
59#define R15IBIT (1L << 27)
60#define R15FBIT (1L << 26)
61#define R15IFBITS (3L << 26)
62
63#define POS(i) ( (~(i)) >> 31 )
64#define NEG(i) ( (i) >> 31 )
65
66#ifdef MODET /* Thumb support. */
67/* ??? This bit is actually in the low order bit of the PC in the hardware.
68 It isn't clear if the simulator needs to model that or not. */
69#define TBIT (1L << 5)
70#define TFLAG state->TFlag
71#define SETT state->TFlag = 1
72#define CLEART state->TFlag = 0
73#define ASSIGNT(res) state->TFlag = res
74#define INSN_SIZE (TFLAG ? 2 : 4)
75#else
76#define TBIT (1L << 5)
77#define INSN_SIZE 4
78#define TFLAG 0
79#endif
80
81/*add armv6 CPSR feature*/
82#define EFLAG state->EFlag
83#define SETE state->EFlag = 1
84#define CLEARE state->EFlag = 0
85#define ASSIGNE(res) state->NFlag = res
86
87#define AFLAG state->AFlag
88#define SETA state->AFlag = 1
89#define CLEARA state->AFlag = 0
90#define ASSIGNA(res) state->NFlag = res
91
92#define QFLAG state->QFlag
93#define SETQ state->QFlag = 1
94#define CLEARQ state->AFlag = 0
95#define ASSIGNQ(res) state->QFlag = res
96
97/* add end */
98
99#define NFLAG state->NFlag
100#define SETN state->NFlag = 1
101#define CLEARN state->NFlag = 0
102#define ASSIGNN(res) state->NFlag = res
103
104#define ZFLAG state->ZFlag
105#define SETZ state->ZFlag = 1
106#define CLEARZ state->ZFlag = 0
107#define ASSIGNZ(res) state->ZFlag = res
108
109#define CFLAG state->CFlag
110#define SETC state->CFlag = 1
111#define CLEARC state->CFlag = 0
112#define ASSIGNC(res) state->CFlag = res
113
114#define VFLAG state->VFlag
115#define SETV state->VFlag = 1
116#define CLEARV state->VFlag = 0
117#define ASSIGNV(res) state->VFlag = res
118
119#define SFLAG state->SFlag
120#define SETS state->SFlag = 1
121#define CLEARS state->SFlag = 0
122#define ASSIGNS(res) state->SFlag = res
123
124#define IFLAG (state->IFFlags >> 1)
125#define FFLAG (state->IFFlags & 1)
126#define IFFLAGS state->IFFlags
127#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
128#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;
129
130#define PSR_FBITS (0xff000000L)
131#define PSR_SBITS (0x00ff0000L)
132#define PSR_XBITS (0x0000ff00L)
133#define PSR_CBITS (0x000000ffL)
134
135#if defined MODE32 || defined MODET
136#define CCBITS (0xf8000000L)
137#else
138#define CCBITS (0xf0000000L)
139#endif
140
141#define INTBITS (0xc0L)
142
143#if defined MODET && defined MODE32
144#define PCBITS (0xffffffffL)
145#else
146#define PCBITS (0xfffffffcL)
147#endif
148
149#define MODEBITS (0x1fL)
150#define R15INTBITS (3L << 26)
151
152#if defined MODET && defined MODE32
153#define R15PCBITS (0x03ffffffL)
154#else
155#define R15PCBITS (0x03fffffcL)
156#endif
157
158#define R15PCMODEBITS (0x03ffffffL)
159#define R15MODEBITS (0x3L)
160
161#ifdef MODE32
162#define PCMASK PCBITS
163#define PCWRAP(pc) (pc)
164#else
165#define PCMASK R15PCBITS
166#define PCWRAP(pc) ((pc) & R15PCBITS)
167#endif
168
169#define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS))
170#define R15INT (state->Reg[15] & R15INTBITS)
171#define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS))
172#define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS))
173#define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS))
174#define R15PC (state->Reg[15] & R15PCBITS)
175#define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS))
176#define R15MODE (state->Reg[15] & R15MODEBITS)
177
178#define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28) | (SFLAG << 27))
179#define EINT (IFFLAGS << 6)
180#define ER15INT (IFFLAGS << 26)
181#define EMODE (state->Mode)
182
183//#ifdef MODET
184//#define CPSR (ECC | EINT | EMODE | (TFLAG << 5))
185//#else
186//#define CPSR (ECC | EINT | EMODE)
187//#endif
188
189#ifdef MODE32
190#define PATCHR15
191#else
192#define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC
193#endif
194
195#define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE))
196#define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS)
197#define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS)
198#define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS)
199#define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS)
200
201#define SETR15PSR(s) \
202 do \
203 { \
204 if (state->Mode == USER26MODE) \
205 { \
206 state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE; \
207 ASSIGNN ((state->Reg[15] & NBIT) != 0); \
208 ASSIGNZ ((state->Reg[15] & ZBIT) != 0); \
209 ASSIGNC ((state->Reg[15] & CBIT) != 0); \
210 ASSIGNV ((state->Reg[15] & VBIT) != 0); \
211 } \
212 else \
213 { \
214 state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)); \
215 ARMul_R15Altered (state); \
216 } \
217 } \
218 while (0)
219
220#define SETABORT(i, m, d) \
221 do \
222 { \
223 int SETABORT_mode = (m); \
224 \
225 ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \
226 ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \
227 | (i) | SETABORT_mode)); \
228 state->Reg[14] = temp - (d); \
229 } \
230 while (0)
231
232//#ifndef MODE32
233#define VECTORS 0x20
234#define LEGALADDR 0x03ffffff
235#define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
236#define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig)
237//#endif
238
239#define INTERNALABORT(address) \
240 do \
241 { \
242 if (address < VECTORS) \
243 state->Aborted = ARMul_DataAbortV; \
244 else \
245 state->Aborted = ARMul_AddrExceptnV; \
246 } \
247 while (0)
248
249#ifdef MODE32
250#define TAKEABORT ARMul_Abort (state, ARMul_DataAbortV)
251#else
252#define TAKEABORT \
253 do \
254 { \
255 if (state->Aborted == ARMul_AddrExceptnV) \
256 ARMul_Abort (state, ARMul_AddrExceptnV); \
257 else \
258 ARMul_Abort (state, ARMul_DataAbortV); \
259 } \
260 while (0)
261#endif
262
263#define CPTAKEABORT \
264 do \
265 { \
266 if (!state->Aborted) \
267 ARMul_Abort (state, ARMul_UndefinedInstrV); \
268 else if (state->Aborted == ARMul_AddrExceptnV) \
269 ARMul_Abort (state, ARMul_AddrExceptnV); \
270 else \
271 ARMul_Abort (state, ARMul_DataAbortV); \
272 } \
273 while (0);
274
275
276/* Different ways to start the next instruction. */
277#define SEQ 0
278#define NONSEQ 1
279#define PCINCEDSEQ 2
280#define PCINCEDNONSEQ 3
281#define PRIMEPIPE 4
282#define RESUME 8
283
284/************************************/
285/* shenoubang 2012-3-11 */
286/* for armv7 DBG DMB DSB instr*/
287/************************************/
288#define MBReqTypes_Writes 0
289#define MBReqTypes_All 1
290
291#define NORMALCYCLE state->NextInstr = 0
292#define BUSUSEDN state->NextInstr |= 1 /* The next fetch will be an N cycle. */
293#define BUSUSEDINCPCS \
294 do \
295 { \
296 if (! state->is_v4) \
297 { \
298 /* A standard PC inc and an S cycle. */ \
299 state->Reg[15] += isize; \
300 state->NextInstr = (state->NextInstr & 0xff) | 2; \
301 } \
302 } \
303 while (0)
304
305#define BUSUSEDINCPCN \
306 do \
307 { \
308 if (state->is_v4) \
309 BUSUSEDN; \
310 else \
311 { \
312 /* A standard PC inc and an N cycle. */ \
313 state->Reg[15] += isize; \
314 state->NextInstr |= 3; \
315 } \
316 } \
317 while (0)
318
319#define INCPC \
320 do \
321 { \
322 /* A standard PC inc. */ \
323 state->Reg[15] += isize; \
324 state->NextInstr |= 2; \
325 } \
326 while (0)
327
328#define FLUSHPIPE state->NextInstr |= PRIMEPIPE
329
330/* Cycle based emulation. */
331
332#define OUTPUTCP(i,a,b)
333#define NCYCLE
334#define SCYCLE
335#define ICYCLE
336#define CCYCLE
337#define NEXTCYCLE(c)
338
339/* Macros to extract parts of instructions. */
340#define DESTReg (BITS (12, 15))
341#define LHSReg (BITS (16, 19))
342#define RHSReg (BITS ( 0, 3))
343
344#define DEST (state->Reg[DESTReg])
345
346#ifdef MODE32
347#ifdef MODET
348#define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC) : (state->Reg[LHSReg]))
349#define RHS ((RHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC) : (state->Reg[RHSReg]))
350#else
351#define LHS (state->Reg[LHSReg])
352#define RHS (state->Reg[RHSReg])
353#endif
354#else
355#define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]))
356#define RHS ((RHSReg == 15) ? R15PC : (state->Reg[RHSReg]))
357#endif
358
359#define MULDESTReg (BITS (16, 19))
360#define MULLHSReg (BITS ( 0, 3))
361#define MULRHSReg (BITS ( 8, 11))
362#define MULACCReg (BITS (12, 15))
363
364#define DPImmRHS (ARMul_ImmedTable[BITS(0, 11)])
365#define DPSImmRHS temp = BITS(0,11) ; \
366 rhs = ARMul_ImmedTable[temp] ; \
367 if (temp > 255) /* There was a shift. */ \
368 ASSIGNC (rhs >> 31) ;
369
370#ifdef MODE32
371#define DPRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
372 : GetDPRegRHS (state, instr))
373#define DPSRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
374 : GetDPSRegRHS (state, instr))
375#else
376#define DPRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
377 : GetDPRegRHS (state, instr))
378#define DPSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
379 : GetDPSRegRHS (state, instr))
380#endif
381
382#define LSBase state->Reg[LHSReg]
383#define LSImmRHS (BITS(0,11))
384
385#ifdef MODE32
386#define LSRegRHS ((BITS (4, 11) == 0) ? state->Reg[RHSReg] \
387 : GetLSRegRHS (state, instr))
388#else
389#define LSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
390 : GetLSRegRHS (state, instr))
391#endif
392
393#define LSMNumRegs ((ARMword) ARMul_BitList[BITS (0, 7)] + \
394 (ARMword) ARMul_BitList[BITS (8, 15)] )
395#define LSMBaseFirst ((LHSReg == 0 && BIT (0)) || \
396 (BIT (LHSReg) && BITS (0, LHSReg - 1) == 0))
397
398#define SWAPSRC (state->Reg[RHSReg])
399
400#define LSCOff (BITS (0, 7) << 2)
401#define CPNum BITS (8, 11)
402
403/* Determine if access to coprocessor CP is permitted.
404 The XScale has a register in CP15 which controls access to CP0 - CP13. */
405//chy 2003-09-03, new CP_ACCESS_ALLOWED
406/*
407#define CP_ACCESS_ALLOWED(STATE, CP) \
408 ( ((CP) >= 14) \
409 || (! (STATE)->is_XScale) \
410 || (read_cp15_reg (15, 0, 1) & (1 << (CP))))
411*/
412//#define CP_ACCESS_ALLOWED(STATE, CP) \
413// (((CP) >= 14) \
414// || (!(STATE)->is_XScale) \
415// || (xscale_cp15_cp_access_allowed(STATE, 15, CP)))
416
417#define CP_ACCESS_ALLOWED(STATE, CP) false // Disabled coprocessor shit /bunnei
418
419/* Macro to rotate n right by b bits. */
420#define ROTATER(n, b) (((n) >> (b)) | ((n) << (32 - (b))))
421
422/* Macros to store results of instructions. */
423#define WRITEDEST(d) \
424 do \
425 { \
426 if (DESTReg == 15) \
427 WriteR15 (state, d); \
428 else \
429 DEST = d; \
430 } \
431 while (0)
432
433#define WRITESDEST(d) \
434 do \
435 { \
436 if (DESTReg == 15) \
437 WriteSR15 (state, d); \
438 else \
439 { \
440 DEST = d; \
441 ARMul_NegZero (state, d); \
442 } \
443 } \
444 while (0)
445
446#define WRITEDESTB(d) \
447 do \
448 { \
449 if (DESTReg == 15){ \
450 WriteR15Branch (state, d); \
451 } \
452 else{ \
453 DEST = d; \
454 } \
455 } \
456 while (0)
457
458#define BYTETOBUS(data) ((data & 0xff) | \
459 ((data & 0xff) << 8) | \
460 ((data & 0xff) << 16) | \
461 ((data & 0xff) << 24))
462
463#define BUSTOBYTE(address, data) \
464 do \
465 { \
466 if (state->bigendSig) \
467 temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff; \
468 else \
469 temp = (data >> ((address & 3) << 3)) & 0xff; \
470 } \
471 while (0)
472
473#define LOADMULT(instr, address, wb) LoadMult (state, instr, address, wb)
474#define LOADSMULT(instr, address, wb) LoadSMult (state, instr, address, wb)
475#define STOREMULT(instr, address, wb) StoreMult (state, instr, address, wb)
476#define STORESMULT(instr, address, wb) StoreSMult (state, instr, address, wb)
477
478#define POSBRANCH ((instr & 0x7fffff) << 2)
479#define NEGBRANCH ((0xff000000 |(instr & 0xffffff)) << 2)
480
481
482/* Values for Emulate. */
483#define STOP 0 /* stop */
484#define CHANGEMODE 1 /* change mode */
485#define ONCE 2 /* execute just one interation */
486#define RUN 3 /* continuous execution */
487
488/* Stuff that is shared across modes. */
489extern unsigned ARMul_MultTable[]; /* Number of I cycles for a mult. */
490extern ARMword ARMul_ImmedTable[]; /* Immediate DP LHS values. */
491extern char ARMul_BitList[]; /* Number of bits in a byte table. */
492
493#define EVENTLISTSIZE 1024L
494
495/* Thumb support. */
496typedef enum
497{
498 t_undefined, /* Undefined Thumb instruction. */
499 t_decoded, /* Instruction decoded to ARM equivalent. */
500 t_branch /* Thumb branch (already processed). */
501}
502tdstate;
503
504/*********************************************************************************
505 * Check all the possible undef or unpredict behavior, Some of them probably is
506 * out-of-updated with the newer ISA.
507 * -- Michael.Kang
508 ********************************************************************************/
509#define UNDEF_WARNING ERROR_LOG(ARM11, "undefined or unpredicted behavior for arm instruction.\n");
510
511/* Macros to scrutinize instructions. */
512#define UNDEF_Test UNDEF_WARNING
513//#define UNDEF_Test
514
515//#define UNDEF_Shift UNDEF_WARNING
516#define UNDEF_Shift
517
518//#define UNDEF_MSRPC UNDEF_WARNING
519#define UNDEF_MSRPC
520
521//#define UNDEF_MRSPC UNDEF_WARNING
522#define UNDEF_MRSPC
523
524#define UNDEF_MULPCDest UNDEF_WARNING
525//#define UNDEF_MULPCDest
526
527#define UNDEF_MULDestEQOp1 UNDEF_WARNING
528//#define UNDEF_MULDestEQOp1
529
530//#define UNDEF_LSRBPC UNDEF_WARNING
531#define UNDEF_LSRBPC
532
533//#define UNDEF_LSRBaseEQOffWb UNDEF_WARNING
534#define UNDEF_LSRBaseEQOffWb
535
536//#define UNDEF_LSRBaseEQDestWb UNDEF_WARNING
537#define UNDEF_LSRBaseEQDestWb
538
539//#define UNDEF_LSRPCBaseWb UNDEF_WARNING
540#define UNDEF_LSRPCBaseWb
541
542//#define UNDEF_LSRPCOffWb UNDEF_WARNING
543#define UNDEF_LSRPCOffWb
544
545//#define UNDEF_LSMNoRegs UNDEF_WARNING
546#define UNDEF_LSMNoRegs
547
548//#define UNDEF_LSMPCBase UNDEF_WARNING
549#define UNDEF_LSMPCBase
550
551//#define UNDEF_LSMUserBankWb UNDEF_WARNING
552#define UNDEF_LSMUserBankWb
553
554//#define UNDEF_LSMBaseInListWb UNDEF_WARNING
555#define UNDEF_LSMBaseInListWb
556
557#define UNDEF_SWPPC UNDEF_WARNING
558//#define UNDEF_SWPPC
559
560#define UNDEF_CoProHS UNDEF_WARNING
561//#define UNDEF_CoProHS
562
563#define UNDEF_MCRPC UNDEF_WARNING
564//#define UNDEF_MCRPC
565
566//#define UNDEF_LSCPCBaseWb UNDEF_WARNING
567#define UNDEF_LSCPCBaseWb
568
569#define UNDEF_UndefNotBounced UNDEF_WARNING
570//#define UNDEF_UndefNotBounced
571
572#define UNDEF_ShortInt UNDEF_WARNING
573//#define UNDEF_ShortInt
574
575#define UNDEF_IllegalMode UNDEF_WARNING
576//#define UNDEF_IllegalMode
577
578#define UNDEF_Prog32SigChange UNDEF_WARNING
579//#define UNDEF_Prog32SigChange
580
581#define UNDEF_Data32SigChange UNDEF_WARNING
582//#define UNDEF_Data32SigChange
583
584/* Prototypes for exported functions. */
585extern unsigned ARMul_NthReg (ARMword, unsigned);
586extern int AddOverflow (ARMword, ARMword, ARMword);
587extern int SubOverflow (ARMword, ARMword, ARMword);
588/* Prototypes for exported functions. */
589#ifdef __cplusplus
590 extern "C" {
591#endif
592extern ARMword ARMul_Emulate26 (ARMul_State *);
593extern ARMword ARMul_Emulate32 (ARMul_State *);
594#ifdef __cplusplus
595 }
596#endif
597extern unsigned IntPending (ARMul_State *);
598extern void ARMul_CPSRAltered (ARMul_State *);
599extern void ARMul_R15Altered (ARMul_State *);
600extern ARMword ARMul_GetPC (ARMul_State *);
601extern ARMword ARMul_GetNextPC (ARMul_State *);
602extern ARMword ARMul_GetR15 (ARMul_State *);
603extern ARMword ARMul_GetCPSR (ARMul_State *);
604extern void ARMul_EnvokeEvent (ARMul_State *);
605extern unsigned int ARMul_Time (ARMul_State *);
606extern void ARMul_NegZero (ARMul_State *, ARMword);
607extern void ARMul_SetPC (ARMul_State *, ARMword);
608extern void ARMul_SetR15 (ARMul_State *, ARMword);
609extern void ARMul_SetCPSR (ARMul_State *, ARMword);
610extern ARMword ARMul_GetSPSR (ARMul_State *, ARMword);
611extern void ARMul_Abort26 (ARMul_State *, ARMword);
612extern void ARMul_Abort32 (ARMul_State *, ARMword);
613extern ARMword ARMul_MRC (ARMul_State *, ARMword);
614extern void ARMul_MRRC (ARMul_State *, ARMword, ARMword *, ARMword *);
615extern void ARMul_CDP (ARMul_State *, ARMword);
616extern void ARMul_LDC (ARMul_State *, ARMword, ARMword);
617extern void ARMul_STC (ARMul_State *, ARMword, ARMword);
618extern void ARMul_MCR (ARMul_State *, ARMword, ARMword);
619extern void ARMul_MCRR (ARMul_State *, ARMword, ARMword, ARMword);
620extern void ARMul_SetSPSR (ARMul_State *, ARMword, ARMword);
621extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword);
622extern ARMword ARMul_Align (ARMul_State *, ARMword, ARMword);
623extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword);
624extern void ARMul_MSRCpsr (ARMul_State *, ARMword, ARMword);
625extern void ARMul_SubOverflow (ARMul_State *, ARMword, ARMword, ARMword);
626extern void ARMul_AddOverflow (ARMul_State *, ARMword, ARMword, ARMword);
627extern void ARMul_SubCarry (ARMul_State *, ARMword, ARMword, ARMword);
628extern void ARMul_AddCarry (ARMul_State *, ARMword, ARMword, ARMword);
629extern tdstate ARMul_ThumbDecode (ARMul_State *, ARMword, ARMword, ARMword *);
630extern ARMword ARMul_GetReg (ARMul_State *, unsigned, unsigned);
631extern void ARMul_SetReg (ARMul_State *, unsigned, unsigned, ARMword);
632extern void ARMul_ScheduleEvent (ARMul_State *, unsigned int,
633 unsigned (*)(ARMul_State *));
634/* Coprocessor support functions. */
635extern unsigned ARMul_CoProInit (ARMul_State *);
636extern void ARMul_CoProExit (ARMul_State *);
637extern void ARMul_CoProAttach (ARMul_State *, unsigned, ARMul_CPInits *,
638 ARMul_CPExits *, ARMul_LDCs *, ARMul_STCs *,
639 ARMul_MRCs *, ARMul_MCRs *, ARMul_MRRCs *, ARMul_MCRRs *,
640 ARMul_CDPs *, ARMul_CPReads *, ARMul_CPWrites *);
641extern void ARMul_CoProDetach (ARMul_State *, unsigned);
642extern ARMword read_cp15_reg (unsigned, unsigned, unsigned);
643
644extern unsigned DSPLDC4 (ARMul_State *, unsigned, ARMword, ARMword);
645extern unsigned DSPMCR4 (ARMul_State *, unsigned, ARMword, ARMword);
646extern unsigned DSPMRC4 (ARMul_State *, unsigned, ARMword, ARMword *);
647extern unsigned DSPSTC4 (ARMul_State *, unsigned, ARMword, ARMword *);
648extern unsigned DSPCDP4 (ARMul_State *, unsigned, ARMword);
649extern unsigned DSPMCR5 (ARMul_State *, unsigned, ARMword, ARMword);
650extern unsigned DSPMRC5 (ARMul_State *, unsigned, ARMword, ARMword *);
651extern unsigned DSPLDC5 (ARMul_State *, unsigned, ARMword, ARMword);
652extern unsigned DSPSTC5 (ARMul_State *, unsigned, ARMword, ARMword *);
653extern unsigned DSPCDP5 (ARMul_State *, unsigned, ARMword);
654extern unsigned DSPMCR6 (ARMul_State *, unsigned, ARMword, ARMword);
655extern unsigned DSPMRC6 (ARMul_State *, unsigned, ARMword, ARMword *);
656extern unsigned DSPCDP6 (ARMul_State *, unsigned, ARMword);
657
658
659#endif
HIC SVNT DRACONES