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Diffstat (limited to 'src/core/arm/interpreter/armemu.cpp')
-rw-r--r--src/core/arm/interpreter/armemu.cpp14
1 files changed, 10 insertions, 4 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index 43b1ba40e..12166bf79 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -6470,17 +6470,23 @@ L_stm_s_takeabort:
6470 6470
6471 if (BITS(12, 15) != 15) { 6471 if (BITS(12, 15) != 15) {
6472 state->Reg[rd_idx] += state->Reg[ra_idx]; 6472 state->Reg[rd_idx] += state->Reg[ra_idx];
6473 ARMul_AddOverflowQ(state, product1 + product2, state->Reg[ra_idx]); 6473 if (ARMul_AddOverflowQ(product1 + product2, state->Reg[ra_idx]))
6474 SETQ;
6474 } 6475 }
6475 6476
6476 ARMul_AddOverflowQ(state, product1, product2); 6477 if (ARMul_AddOverflowQ(product1, product2))
6478 SETQ;
6477 } 6479 }
6478 // SMUSD and SMLSD 6480 // SMUSD and SMLSD
6479 else { 6481 else {
6480 state->Reg[rd_idx] = product1 - product2; 6482 state->Reg[rd_idx] = product1 - product2;
6481 6483
6482 if (BITS(12, 15) != 15) 6484 if (BITS(12, 15) != 15) {
6483 state->Reg[rd_idx] += state->Reg[ra_idx]; 6485 state->Reg[rd_idx] += state->Reg[ra_idx];
6486
6487 if (ARMul_AddOverflowQ(product1 - product2, state->Reg[ra_idx]))
6488 SETQ;
6489 }
6484 } 6490 }
6485 6491
6486 return 1; 6492 return 1;